Symmetrically compensated fully differential folded-cascode OTA

A symmetric compensation technique that improves the phase response for fully differential folded-cascode operational transconductance amplifiers (OTA) is proposed. Theory and simulated results show that the magnitude response and settling time for symmetrically compensated OTAs are also improved in comparison with those of compensated and typical OTAs     

An OTA gain enhancement technique for low power biomedical applications

The performance requirement of an operational trans-conductance amplifier (OTA) for the high gain and low power neural recording frontend has been addressed in this paper. A novel split differential pair technique is proposed to improve the gain of the OTA without any additional bias current requirements. The design demonstrates a significant performance enhancement when compared to existing techniques, such as gain-boosting and recycling. A qualitative and quantitative treatment is presented to explore the impact of the split ratio on the performance parameters of gain, bandwidth, and linearity. A prototype implemented in TSMC 65 nm CMOS technology achieved 68 dB open loop-gain (13 dB higher than the conventional circuit) and a 17 kHz 3-dB bandwidth. A linearity of ? 62 dB has been achieved with 7 mV pk–pk signal at the input. The circuit operates from a 1 V supply and draws 0.6 uA static current. The prototype occupies 3300 um² silicon area.     

Slew rate enhancement method for folded-cascode amplifiers

A new circuit is proposed to enhance the slew rate (SR) of the folded-cascode amplifier (FCA). The proposed circuit is automatically activated during the slewing phase. Simulation results show a fourtimes improvement in the SR and close to 40% reduction in the settling time, compared to a conventional FCA     

Design and analysis of DC gain and transconductance boosted recycling folded cascode OTA

A new technique for improving the transconductance and low frequency output impedance of recycling folded cascode (RFC) amplifiers is presented. This enhancement was achieved by using a positive feedback and upgrading the recycling structure. The new structure profits from better transconductance, slew rate, and DC gain in comparison with conventional folded cascode (FC) amplifier. Moreover, the input referred noise is reduced and the phase-margin improved. The enhanced amplifier, simulated in 0.18 μm CMOS technology, exhibits a DC gain enhancement of 16.3 dB as well as 115.5 MHz increase in gain bandwidth compared to conventional FC configuration. The amplifier consumes 360 μW @ 1.2 V which makes it suitable for low-voltage applications.     

一款高性能共源共栅运算放大器设计

基于CSMC 0.5μm标准CMOS工艺,采用复用型折叠式共源共栅结构,设计一种折叠式共源共栅运算放大器。该电路在5V电源电压下驱动5pF负载电容,采用Cadence公司的模拟仿真工具Spectre对电路进行仿真。结果表明,电路开环增益达到了71.7dB,单位增益带宽为52.79MHz,开环相位裕度为60.45°。     

Phase-margin enhancement technique for recycling folded cascode amplifier

A novel circuit technique for enhancing the phase-margin of the recycling folded cascode amplifier is presented. Compared to the conventional recycling folded cascade, using a high-speed current mirror, the proposed amplifier offers the advantage of cancellation of the first non-dominant pole, allowing the phase-margin to be enhanced without affecting the bandwidth. The proposed amplifier was implemented in CSMC standard 0.18 μm CMOS process. Simulation results show that the phase-margin enhancement of 20° is achieved without limiting the bandwidth.     

An enhanced fully differential folded-cascode op amp

An enhanced fully differential folded-cascode operational-amplifier topology that achieves improved DC gain and common-mode rejection without sacrificing slew rate is presented. The large-signal operation of the new topology is completely symmetric, providing equal positive and negative slew-rate behavior by making use of current mirrors rather than current sources as normally found in full differential folded-cascode op-amps. An additional advantage of the enhanced topology is that its common-mode output impedance is a factor of g_mr_o (typically 1-2 orders of magnitude) lower than the differential-mode output impedance, significantly improving the common-mode rejection ratio. The predicted performance is verified by simulations and preliminary experimental results     

一种高性能Folded-Cascode运算放大器的设计

介绍了一种高性能Foldcd-Cascode运放的电路结构,它具有先进的偏置电源结构以调节输出动态幅度、动态开关电容反馈电路用于控制运放输出端的稳定性、合理地关断电路以降低电路非工作时的功耗等特点.运用HSPICE对电路进行了模拟,并给出了结果.     

A novel class of complementary folded-cascode opamps for low voltage

Three novel complementary folded-cascode operational amplifiers (opamps) with high gain, large bandwidth, and rail-to-rail input range for low-voltage operation will be presented. These opamps feature high bandwidth due to minimum internal nodes. The output swing is increased by properly adjusting the output cascode transistor gate voltages close to the power supply voltages. The opamps have been fabricated with a standard 0.8-/spl mu/m CMOS technology. Measurements show the amplification is between 60.1 and 72.4 dB, and the unity gain bandwidth is 14 MHz for a 5-pF load, 2.5-V power supply, and 150-/spl mu/A bias current.     

OTA linearity enhancement technique for high frequency applications with IM3 below -65 dB

A technique to enhance the linearity of continuous-time operational transconductance amplifiers (OTA)-C filters working at high frequencies is proposed. Each OTA consumes 10.5 mW and the transconductance can be tuned from 70 to 160 /spl mu/A/V while the IM3 remains below -70 dB up to 50 MHz for a 1.3-V/sub pp/ differential input. For a 20-MHz low-pass second-order filter implementation, the measured IM3 with an input voltage of 1.3 V/sub pp/ is below - 65 dB. The supply voltage is 3.3 V. Experimental results of the circuit, fabricated in a standard CMOS 0.35-/spl mu/m technology, are presented.     

基于电流模施密特触发器的OTA—C张驰振荡器及其PSPICE仿真研究

提出了基于电流模施密特触发器的OTA-C张驰振荡器。该电路的振荡信号周期可由接地可容线性改变,而频率则与OTA的跨导成正比。经PSPICE仿真模拟,其结果与理论计算值一致。     

Feedforward-Regulated Cascode OTA for Gigahertz Applications

A very high-frequency operational transconductance amplifier (OTA) with a new feedforward-regulated cascode topology is demonstrated in this paper. Experimental results show a bandwidth of 10 GHz and a large transconductance of 11 mS. A theoretical analysis of the OTA is provided which is in very good agreement with the measured results. We also carry out a Monte Carlo simulation to determine the effect of transistor mismatches and process variations on the transconductance and input/output parasitic capacitances of the OTA. The linearity and intermodulation distortion properties of the OTA, which are of particular interest in microwave applications, are experimentally determined using a purpose-built single-stage amplifier. For high-frequency demonstration purposes we built a larger circuit: an inductorless microwave oscillator. The fabricated oscillator operates at 2.89 GHz and has a significantly larger output voltage swing and better power efficiency than other inductorless oscillators reported in the literature in this frequency range. It also has a very good phase noise for this type of oscillators: ${-}116$ dBc/Hz at 1-MHz offset.      

一种高CMRR和PSRR的共源共栅放大器

针对传统运算放大器共模抑制比和电源抑制比低的问题,设计了一种差分输入结构的折叠式共源共栅放大器。本设计采用两级结构,第一级为差分结构的折叠式共源共栅放大器,并采用MOS管作为电阻,进一步提高增益、共模抑制比和电源电压抑制比;第二级采用以NMOS为负载的共源放大器结构,提高增益和输出摆幅。基于LITE—ON40V1．0μm工艺,采用Spectre对电路进行仿真。仿真结果表明,电路交流增益为125．8dB,相位裕度为62.8°,共模抑制比140．9dB,电源电压抑制比125．5dB。     

Double pass technique for fabricating compact optical fibre rockingfilters

By using the photosensitivity of Ge-doped birefringent fibres, efficient narrowband rocking filters have been fabricated that, to the authors' knowledge, are the shortest in length per unit beat length to date. This has been achieved by using a point-by-point external writing process in which a UV beam periodically exposes sections of an elliptically-cored fibre. Alternate sections are exposed from opposite sides of the fibre, effectively doubling the coupling strength per beat length. Alignment with the fibre axes is assisted by use of a keyed optical fibre     

用于Sigma-Delta调制器的低电压跨导运算放大器

跨导运算放大器是模拟电路中的重要模块,其性能往往会决定整个系统的效果.这里设计了一种适用于高阶单环Sigma-Delta调制器的全差分折叠式共源共栅跨导运算放大器.该跨导运算放大器采用经典的折叠式共源共栅结构,带有一个开关电容共模反馈电路.运算放大器使用SIMC 0.18 μm CMOS混合信号工艺设计,使用Spectre对电路进行整体仿真,仿真结果表明,负载电容为5 pF时,该电路直流增益可达72 dB、单位增益带宽91.25 MHz、相位裕度83.35°、压摆率35.1 V/μs、功耗仅为1.41 mW.本设计采用1.8 V低电源电压供电,通过对电路参数的优化设计,使得电路在低电压条件下仍取得良好的性能,能满足Sigma Delta调制器高精度的要求.     

CTIA OTA认可中无线终端暗室纹波测量解析

美国无线通信和互联网协会(CTIA)制定的无线终端OTA测试标准,对于移动通信手机等产品的测试具有一定参考意义。该标准中最重要的内容是对暗室纹波性能的测量。通过CTIA OTA实验室认可对我国移动通信手机等产品的出口有益。在CTIA OTA 实验室认可中,OTA暗室的纹波性能是一个非常重要的指标,直接影响着OTA测试结果的不确定度。主要叙述了CTIA OTA实验室认可中的暗室纹波性能测量技术,具体描述了测量原理、测量方法、所用仪器及遇到问题的解决方法,研究工作对获取CTIA OTA实验室资质有着积极的意义。     

Low-voltage high-gain differential OTA for SC circuits

A new differential operational transconductance amplifier (OTA) for SC circuits that operates with a supply voltage of less than two transistor threshold voltages is presented. Its simplicity relies on the use of a low-voltage regulated cascode circuit, which achieves very high output impedance under low-voltage restrictions. The OTA has been designed to operate with a supply voltage of V/sub DD/=1.5 V, using a 0.6 /spl mu/m CMOS technology with transistor threshold voltages of V/sub TN/=0.75 V and V/sub TP/=-0.85 V. Post-layout simulation results for a load capacitance (C/sub L/) of 2 pF show a 75 MHz gain-bandwidth product and 100 dB DC gain with a quiescent power consumption of 750 /spl mu/W.     

Reverberation Chamber技术应用于手机OTA量测

一般混响室多用于EMC测试中,文章针对手机的OTA全辐射功率与全性灵敏度在混响室中测试方法提出说明,并针对小型的多输入多输出天线于多重路径环境测试测试方式说明。