共查询到19条相似文献,搜索用时 125 毫秒
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基于带隙基准原理,通过优化电路结构和采用BiCMOS技术,提出一种精度高、噪声小的带隙基准源电路。利用具有高开环增益的折叠式共源共栅放大器,提高了低频电压抑制比;应用低跨导PMOS对管及电路输出端低通滤波器,实现了更低的噪声输出;合理的版图设计减小了失调电压带来的影响。Hspice仿真结果表明,在3V电源电压下,输出基准电压为1.2182mV,温度系数为1.257×10-5/℃;频率从103~105 Hz变化时,输出噪声最大值的变化量小于5μV。流片测试结果表明,该基准源输出基准电压的电源抑制比高,温度系数小,噪声与功耗低。 相似文献
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针对传统运算放大器共模抑制比和电源抑制比低的问题,设计了一种差分输入结构的折叠式共源共栅放大器。本设计采用两级结构,第一级为差分结构的折叠式共源共栅放大器,并采用MOS管作为电阻,进一步提高增益、共模抑制比和电源电压抑制比;第二级采用以NMOS为负载的共源放大器结构,提高增益和输出摆幅。基于LITE—ON40V1.0μm工艺,采用Spectre对电路进行仿真。仿真结果表明,电路交流增益为125.8dB,相位裕度为62.8°,共模抑制比140.9dB,电源电压抑制比125.5dB。 相似文献
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低噪声高共模抑制比的运算放大器是将套筒式共源共栅结构、差分输出和共模负反馈相结合,设计出的一种新型运算放大器.基于SMIC0.18 μm工艺模型对电路进行设计,仿真结果表明该电路的开环增益为82.3 dB,相位裕度为66°,共模抑制比为122 dB,增益平坦带宽为15 MHz,噪声为7.781 nV/sqrt (Hz),达到设计要求. 相似文献
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在微机变电站综合自动化系统中,为了保证数字信号处理子系统采集到的信号有精度的频率、相位和足够的幅度,采用实验的手法,去观察和分析传感器输出信号、前置放大电路输出信号、电压比较电路输出信号、系统电源输出电压的波形等.根据不同电路信号频率、幅度和相位的特点与实际需要,利用LC低通无源滤波器和乘法器方式的功率因数纠正电路来过滤采集信号中含的杂波.利用窗口电压比较器使采集信号幅度位于两个指定的门限(参考电平)之间.使用这些措施得到结果是微机变电站综合自动化系统处理信号能力更准确、更快、更安全、更稳定. 相似文献
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Hyunseok Nam Youngkook Ahn Jeongjin Roh 《Analog Integrated Circuits and Signal Processing》2012,71(2):327-332
This letter proposes a new adaptive on-time pulse-frequency modulation (PFM) circuit that operates at a wide range of supply
voltage levels and that can generate various output voltage levels compared to conventional circuits. The circuit’s peak inductor
current is well-controlled; the magnitude of the output ripple voltage is constant, even when the supply and output voltage
levels are significantly different. Since the ripple voltage is a noise component, constant ripple voltage is important for
predictable noise of a power management system. 相似文献
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电压基准在模拟电路中提供一个受电源或温度等影响较小的参考电压,以保证整个电路正常工作。设计了一种低温漂低功耗带隙基准电压源,采用不受电源影响的串联电流镜做偏置.利用PTAT电压的正向温度系数和基极发射极电压的负向温度系数特性,以适当的系数加权构造零温度系数的电压量。该设计避开了运放的应用.结构简易,原理清晰,便于入门级的同学在短时间内学习掌握。0-70℃范围内,温漂系数为16.4ppm/℃。供电电压在5-6V范围内变化时,电源抑制比达57.7dB。总输出噪声为140.3μV,功耗为300.6μW。 相似文献
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利用反向带隙电压原理,采用基于CMOS阈值电压的自偏置共源共栅电流镜技术,设计了一种低压低噪声基准电压源.该电压基准源没有外加滤波电容的情况下,通过双极型晶体管大的输出阻抗特性,实现了更低的噪声输出,提高了输出电压的精度.Hspice仿真结果表明,在0.95V电源电压下,输出基准电压为233.9 mV,温度系数为7.6... 相似文献
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A High-Performance CMOS Voltage-Controlled Oscillator for Ultra-Low-Voltage Operations 总被引:2,自引:0,他引:2
Hsieh-Hung Hsieh Liang-Hung Lu 《Microwave Theory and Techniques》2007,55(3):467-473
In this paper, a novel circuit topology of voltage-controlled oscillators (VCOs) suitable for ultra-low-voltage operations is presented. By utilizing the capacitive feedback and the forward-body-bias (FBB) technique, the proposed VCO can operate at reduced supply voltage and power consumption while maintaining remarkable circuit performance in terms of phase noise, tuning range, and output swing. Using a standard 0.18-mum CMOS process, a 5.6-GHz VCO is designed and fabricated for demonstration. Consuming a dc power of 3 mW from a 0.6-V supply voltage, the VCO exhibits a frequency tuning range of 8.1% and a phase noise of -118 dBc/Hz at 1-MHz offset frequency. With an FBB for the cross-coupled transistors, the fabricated circuit can operate at a supply voltage as low as 0.4 V. The measured tuning range and phase noise are 6.4% and -114 dBc/Hz, respectively 相似文献
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本电源是基于高频高压交流母线具有多组输出的直流电源,它具有高达200kHz的开关频率,后级的整流电路由于高频交流母线的存在,使得变压器和电感的设计变得简单,滤波电容的选择也更容易。本电源由PFC电路提供400V的高压直流输入,再由MOSFET组成全桥逆变电路,在固定额率的PWM发生电路和IR2110 MOSFET驱动电路作用下,只加—个谐振电感就可实现开关管的零电压开通,可在大大降低开关损耗和噪声的同时实现直流交流的变换。整流部分采用倍流整流电路以提高原边电压的利用率,可输出低压大电流。由于采用肖特基管,—方面可使得二板管的损耗可以接受,另外—方面还避免了采用同步整流电路所面临的电路结构复杂和驱动困难。 相似文献
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结合电荷泵型LED驱动器的工作要求,从减小输出电压纹波、稳定输出电压出发,设计了一款误差放大器。该误差放大器具有较大的工作电压范围,使电荷泵型LED驱动器高效率低噪声工作。基于CHRT0.35μm CMOS MIXED SIGNAL TECHNOLOGY进行仿真,结果表明,在2.7~5V工作电压范围内,开环电压增益约等于72dB,相位裕度约等于65°,单位增益带宽约等于4.6MHz,共模抑制比CMRR约等于113dB,电源抑制比PSRR约等于100dB。 相似文献
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Yong Hoon Kang Jin-Kook Kim Sang Won Hwang Joon Young Kwak Jun-Yong Park Daeyong Kim Chan Ho Kim Jong Yeol Park Yong-Taek Jeong Jong Nam Baek Su Chang Jeon Pyungmoon Jang Sang Hoon Lee You-Sang Lee Min-Seok Kim Jin-Yub Lee Yun Ho Choi 《Solid-State Circuits, IEEE Journal of》2008,43(2):507-517
High-voltage analog circuits, including a novel high-voltage regulation scheme, are presented with emphasis on low supply voltage, low power consumption, low area overhead, and low noise, which are key design metrics for implementing NAND Flash memory in a mobile handset. Regulated high voltage generation at low supply voltage is achieved with optimized oscillator, high-voltage charge pump, and voltage regulator circuits. We developed a design methodology for a high-voltage charge pump to minimize silicon area, noise, and power consumption of the circuit without degrading the high-voltage output drive capability. Novel circuit techniques are proposed for low supply voltage operation. Both the oscillator and the regulator circuits achieve 1.5 V operation, while the regulator includes a ripple suppression circuit that is simple and robust. Through the paper, theoretical analysis of the proposed circuits is provided along with Spice simulations. A mobile NAND Flash device is realized with an advanced 63 nm technology to verify the operation of the proposed circuits. Extensive measurements show agreement with the results predicted by both analysis and simulation. 相似文献