共查询到20条相似文献,搜索用时 15 毫秒
1.
《Circuits and Systems II: Express Briefs, IEEE Transactions on》2006,53(8):692-696
Temperature-dependent subthreshold and gate-oxide leakage power characteristics of domino logic circuits under the influence of process parameter variations are evaluated in this paper. Preferred input vectors and node voltage states that minimize the total leakage power consumption are identified at the lower and upper extremes of a typical die temperature spectrum. New low-leakage circuit design guidelines are presented based on the results. Significantly increased gate dielectric tunneling current, as described in this paper, dramatically changes the leakage power characteristics of dynamic circuits in deeply scaled nanometer CMOS technologies. Contrary to the previously published techniques, a charged dynamic-node voltage state with low inputs is preferred for reducing the total leakage power consumption in the most widely used types of single- and dual-threshold voltage domino gates, particularly at low die temperatures. Furthermore, leakage power savings provided by the dual-threshold voltage domino logic circuit techniques based on input gating are all together reduced due to the significance of gate dielectric tunneling in sub-45-nm CMOS technologies. 相似文献
2.
Centurelli F. Monsurro P. Pennisi S. Scotti G. Trifiletti A. 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2009,56(6):459-463
Solutions for the design of low-voltage sample-and-hold (S/H) circuits in CMOS nanometer technologies are presented. As a design example, a 0.8-V supply S/H is designed and simulated using a 130-nm CMOS process. It dissipates 0.5 mW at dc and provides almost a rail-to-rail signal swing. When clocked at 40 MS/s and with a 1.4- VPP differential input signal, the simulated spurious-free dynamic range, signal-to-noise ratio, and total harmonic distortion are 57, 67, and -56 dB (9 equivalent bits), respectively, with low sensitivity to supply, temperature, process, and mismatch variations. The proposed solution employs a three-stage low-voltage amplifier without a tail current source in the differential pair and a switch topology, which combines clock voltage doubling and dummy switches. 相似文献
3.
《IEEE transactions on circuits and systems. I, Regular papers》2008,55(9):2608-2618
4.
CMOS驱动电路中信号延迟的精确计算 总被引:1,自引:0,他引:1
本文提出了树形网络CMOS驱动电路中信号延迟相对精确的计算表达式,它考虑了不同延迟定义下CMOS驱动电路等老头儿 导通电阻及负功电容的影响,可用于VLSI互连延迟的计算及时间驱动布图系统信号延迟计算中。 相似文献
5.
对当前纳米级低功耗设计中静态功耗的产生机理以及各种降低漏电流功耗的电路设计理论及其特点做详细的论述.以期为相关研究:设计人员提供有益参考。 相似文献
6.
7.
本文较为详细地阐述了体硅CMOS结构中的闩锁效应,分析了CMOS结构中的闩锁效应的起因,提取了用于分析闩锁效应的集总组件模型,给出了产生闩锁效应的必要条件与闩锁的触发方式。通过分析表明,只要让CMOS电路工作在安全区,闩锁效应是可以避免的,这可以通过版图设计规则和工艺技术,或者两者相结合的各种措施来实现。本文最后给出了防止闩锁效应的关键设计技术。 相似文献
8.
Magdy A. El-Moursy Eby G. Friedman 《Analog Integrated Circuits and Signal Processing》2004,41(1):5-11
Interconnect resistance dissipates a portion of the total transient power in CMOS circuits. Conduction losses increase with larger interconnect resistance. It is shown in this paper that these losses do not add to the total power dissipation of a CMOS circuit through I
2
R losses. Interconnect resistance can, however, increase the short-circuit power of both the driver and load gates. 相似文献
9.
本文给出了CMOS倒相器的高温等效电路,分析了它的高温直流传输特性和瞬态特性,文章还讨论了CMOS静态数字集成电路高温电学特性的分析方法。本文提出了的CMOS数字集成电路的高温学特性模型和实验结果相接近。 相似文献
10.
本文详细地分析了LDD结构高温CMOS集成电路闩锁效应.文中提出了亚微米和深亚微米CMOS集成电路闩锁效应的模型.在该模型中,针对器件的尺寸和在芯片上分布情况,我们认为CMOS IC闩锁效应的维持电流有两种模式:大尺寸MOST的寄生双极晶体管是长基区,基区输运因子起主要作用;VLSI和ULSI中MOST的寄生双极晶体管是短基区,发射效率起主要作用.但是他们的维持电流都与温度是负指数幂关系.文章给出了这两种模式下的维持电流与温度关系,公式在25℃至300℃之间能与实验结果符合. 相似文献
11.
《Electromagnetic Compatibility, IEEE Transactions on》2009,51(2):351-357
12.
A Body biasing technique has recently been proposed for microprocessors in sub-100 nm technology generations [11, 12]. It
is shown that forward body bias (FBB) reduces the leakage power and suppresses the effect of process variation while reducing
the complexity of dualVth technology. In this paper, we study the effect of body bias on the delay fault testing of CMOS circuits. We analyze the impact
of both fixed and adaptive body biasing techniques on test cost and the quality of test. Statistical analysis on several benchmark
circuits shows that the adaptive body biasing design will have the most effective impact on delay fault by maintaining the
test cost at its minimum under process variation while ensuring the test quality at its highest level.
Bipul C. Paul received B.Tech. and M.Tech. degrees in radiophysics and electronics, from the University of Calcutta and the Ph.D. degree
from Indian Institute of Science (IISc), Bangalore, India.
After his graduation, he joined Alliance Semiconductor (India), where he worked on synchronous DRAM design. In 2000, he joined
Purdue University, West Lafayette, USA, as a Post Doctoral Fellow, where he worked on low-power electronic design of nanoscale
circuits (both bulk and SOI technologies), statistical design under process variation, VLSI testing, verification and noise
analysis. He has also developed device and circuit optimization techniques for ultra-low power digital sub-threshold operation.
Dr. Paul is presently with Toshiba Research, where he is working on post-silicon devices and technology and nano-architecture.
He is also a Visiting Scientist at Stanford University, USA.
Dr. Paul received National scholarship (India) in 1984, the senior research fellowship award from CSIR, India in 1995 and
the Best Thesis of the Year award in 1999. He is a senior member of IEEE.
Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology,
Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at
Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked
on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty at
Purdue University, West Lafayette, IN, in 1993, where he is currently a Professor. His research interests include VLSI design/CAD
with particular emphasis in low-power electronics for portable computing and wireless communications, VLSI testing and verification,
and reconfigurable computing. Dr. Roy has published more than 200 papers in refereed journals and conferences, holds 5 patents,
and is a co-author of a book on Low Power CMOS VLSI Design (John Wiley).
Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent
Foundation award, best paper awards at 1997 International Test Conference and 2000 International Symposium on Quality of IC
Design, and is currently a Purdue University faculty scholar professor. He is in the editorial board of IEEE Design and Test,
IEEE Transactions on Circuits and Systems, and IEEE Transactions on VLSI Systems. He was Guest Editor for Special Issue on
Low-Power VLSI in the IEEE Design and Test (1994) and IEEE Transactions on VLSI Systems (June 2000). Dr. Roy is fellow of
IEEE. 相似文献
13.
两种新型CMOS带隙基准电路 总被引:5,自引:2,他引:5
文章介绍了两种CMOS带隙基准电路.它们在传统带隙基准电路的基础上,采用了低压共源共栅电流镜提供偏置电流,降低了功耗,减小了沟道长度调制效应带来的误差并使电路可以工作在较低的电源电压下;采用运放的输出作为共源共栅电流镜的偏置电压,使基准电压不受电源电压变化的影响.其中一种电路,还通过两个串联二极管的原理提高△VBE,从而减小了运放失调的影响.仿真结果表明,在工艺偏差、电源电压变化±10%以及温度在-20至125℃范围内变化的情况下,两种CMOS带隙基准的输出电压分别是1.228+0.003V和1.215±0.003V,温度系数仅为33.7ppm/℃和34.1ppm/℃;在电源电压分别大于2V和2.8V时,电源电压的变化对这两种基准的输出电压几乎没有影响;在33v电源电压下两个电路的功耗分别小于0.1mW和0.34mW. 相似文献
14.
Minimum energy operation for digital circuits typically requires scaling the power supply below the device threshold voltage. Advanced technologies offer improved integration, performance, and active-energy efficiency for minimum energy sub-Vt circuits, but are plagued by increased variation and reduced ION/IOFF ratios, which degrade the fundamental device characteristics critical to circuit operation by several orders of magnitude. This paper investigates those characteristics and presents design methodologies and circuit topologies to manage their severe degradation. The issues specific to both general logic and dense static random access memories are analyzed, and solutions that address their distinct design metrics are presented. 相似文献
15.
Evaluating Transient Error Effects in Digital Nanometer Circuits 总被引:1,自引:0,他引:1
Chong Zhao Xiaoliang Bai Sujit Dey 《Reliability, IEEE Transactions on》2007,56(3):381-391
Radiation-induced transient errors have become a great threat to the reliability of nanometer circuits. The need for cost-effective robust circuit design mandates the development of efficient reliability metrics. We present a novel ldquonoise impact analysisrdquo methodology to evaluate the transient error effects in static CMOS digital circuits. With both the circuit, and the transient noise abstracted in the format of matrices, the circuit-noise interaction is modeled by a series of matrix transformations. During the transformation, factors that potentially affect the propagation & capture of transient errors are modeled as matrix operations. Finally, a ldquonoise capture ratiordquo is computed as the probability of a sequential element capturing transient noise inside the combinational logics, It is used as a measure of the transient noise effects in the circuit. Comparison with SPICE simulation demonstrates that our technique can accurately, yet quickly estimate the probability of transient errors causing observable error effects. The proposed methodology will greatly facilitate the economic design of robust nanometer circuits. 相似文献
16.
《Solid-State Circuits, IEEE Journal of》2008,43(9):1991-2002
17.
18.
Unique designs for CMOS analog arithmetic circuits are presented which perform addition (V1 + V2), subtraction (V2 – V1), add/invert –(V1 + V2), and multiply (V1 × V2). The circuit operation is based on the inherent square law of MOS transistor drain current when operating in the saturation region. Key features include: good linearity and accuracy, single ended voltage inputs and output, wide input and output range and no input bias voltages. The circuits can be directly coupled (no buffer) and serve as basic building blocks for analog signal processing implementations such as analog filters and adaptive equalizers. All circuits were implemented in 1.2 m CMOS technology. 相似文献
19.
本文介绍目前正在研发、将来终将成为主流射频收发器的CMOS射频电路的体系结构和电路设计,设计实例将展示CMOS射频电路的良好性能,并预示CMOS射频集成电路取代砷化镓和SiGe电路实现系统集成。 相似文献
20.
对全耗尽 SOI(FD SOI) CMOS器件和电路进行了研究 ,硅膜厚度为 70 nm.器件采用双多晶硅栅结构 ,即NMOS器件采用 P+多晶硅栅 ,PMOS器件采用 N+多晶硅栅 ,在轻沟道掺杂条件下 ,得到器件的阈值电压接近0 .7V.为了减小源漏电阻以及防止在沟道边缘出现空洞 (V oids) ,采用了注 Ge硅化物工艺 ,源漏方块电阻约为5 .2Ω /□ .经过工艺流片 ,获得了性能良好的器件和电路 .其中当工作电压为 5 V时 ,0 .8μm 10 1级环振单级延迟为 45 ps 相似文献