Significantly improved performance of MOSFETs on silicon carbideusing the 15R-SiC polytype

Recent studies regarding MOSFETs on SiC reveal that 4H-SiC devices suffer from a low inversion layer mobility, while in 6H-SiC, despite a higher channel mobility the bulk mobility parallel to the c-axis is too low, making this polytype unattractive for power devices. This work presents experimental mobility data of MOSFETs fabricated on different polytypes as well as capacitance-voltage (C-V) measurements of corresponding n-type MOS structures which give evidence that the low inversion channel mobility in 4H-SiC is caused by a high density of SiC-SiO₂ interface states close to the conduction band. These defects are believed to be inherent to all SiC polytypes and energetically pinned at around 2.9 eV above the valence band edge. Thus, for polytypes with band gaps smaller than 4H-SiC like 6H-SiC and 15R-SiC, the majority of these states will become resonant with the conduction band at room temperature or above, thus remarkably suppressing their negative effect on the channel mobility. In order to realize high performance power MOSFETs the results reveal that 15R-SiC is the best candidate among all currently accessible SiC polytypes     

Characterization of inversion and accumulation layer electrontransport in 4H and 6H-SiC MOSFETs on implanted P-type regions

The silicon carbide double implanted vertical MOSFET (SiC DIMOS) is a promising candidate for high power switching applications due to the absence of high electric field corners and compatibility with planar IC technology. In this work, we report on the channel mobility behavior in 4H and 6H-SiC MOSFETs fabricated with a low thermal budget process sequence, on implanted p-type regions which mirror the lateral carrier transport region in the DIMOS device. Channel mobilities are higher by an order of magnitude in 6H-SiC compared to 4H-SiC MOSFET's suggesting the 6H-SiC polytype is better suited for fabricating the DIMOS structure in spite of the superior vertical bulk conduction in 4H-SiC. Moreover, channel mobility on accumulated surfaces is higher than values obtained on inverted surfaces. A strong correlation between the observed threshold voltages and channel mobilities is consistently explained by a modified MOSFET conductance formulation in the presence of slowly decaying bandtail states toward the SiC band edges     

High-voltage lateral RESURF MOSFETs on 4H-SiC

High-voltage lateral RESURF MOSFETs have been fabricated on 4H-SiC with both nitrogen and phosphorus as source/drain and RESURF region implants. Blocking voltages as high as 1200 V and specific on-resistances of 4 Ω cm² have been obtained, with the high on-resistance attributed to poor inversion layer mobility. Phosphorus is most appropriate for the source/drain implants due to low sheet resistance and contact resistance with low temperature anneals. However, poor activation of low dose phosphorus implants at 1200°C makes nitrogen the preferred choice for the RESURF region     

Comparative hall measurements on wet- and dry-oxidized 4H-SiC MOSFETs

Hall measurements have been used to compare the properties of 4H-SiC inversion-mode MOSFETs with “wet” and “dry” gate oxides. While the field-effect mobilities were approximately 3–5 cm²/Vs, the Hall mobilities in 4H-SiC MOSFETs in the wet and dry oxide samples were approximately 70–80 cm²/Vs. The dry-oxidized metal oxide semiconductor field effect transistors (MOSFETs) had a higher transconductance, improved threshold voltage, improved subthreshold slope, and a higher inversion carrier concentration compared to the wet-oxidized MOSFETs. The difference in characteristics between the wet- and the dry-oxidized MOSFETs is attributed to the larger fixed oxide charge in the dry oxide sample and a higher interface trap density in the wet oxide sample.     

Strong dependence of the inversion mobility of 4H and 6H SiC(0001)MOSFETs on the water content in pyrogenic re-oxidation annealing

The inversion channel mobility of 4H and 6H-SiC(0001) metal-oxide-semiconductor field-effect transistors (MOSFETs) has been evaluated for its dependence on the re-oxidation annealing (ROA) conditions in a wet oxidizing ambient. The wet ambient was supplied by the pyrogenic reaction of hydrogen and oxygen gas (pyrogenic ROA), where the water vapor content (ρ(H₂O)) was controlled by adjusting the hydrogen/oxygen gas flow rate. Not only the annealing temperature and the time, but also ρ(H₂O) are found to be the critical parameters for improving channel mobility. As a result, field-effect channel mobilities as high as 47 cm²/Vs for 4H and 95 cm²/Vs for 6H-SiC MOSFETs were achieved by pryrogenic ROA treatment with a ρ(H₂O) of 50%     

Nitrogen Plasma Processing of SiO2/4H-SiC Interfaces

A nitrogen plasma annealing process for gate dielectric applications in 4H-SiC metal oxide semiconductor (MOS) technology has been investigated. This process results in substantially greater interfacial N coverage at the SiO₂/4H-SiC interface and lower interface trap densities than the state-of-the-art nitric oxide (NO) annealing process. Despite these exciting results, the field-effect mobility of MOS field-effect transistors (MOSFETs) fabricated by use of this process is very similar to that of NO-annealed MOSFETs. These results emphasize the importance of understanding mobility-limiting mechanisms in addition to charge trapping in next-generation 4H-SiC MOSFETs.     

Experimental and theoretical investigations on short-channel effects in 4H-SiC MOSFETs

In this paper, a fundamental investigation on short-channel effects (SCEs) in 4H-SiC MOSFETs is given. Planar MOSFETs with various channel lengths have been fabricated on p-type 4H-SiC (0001), (0001) and (1120) faces. In the fabricated MOSFETs, SCEs such as punchthrough behavior, decrease of threshold voltage, deterioration of subthreshold characteristics, and saturation of transconductance occur by reducing channel length. The critical channel lengths below which SCEs occur are analyzed as a function of p-body doping and oxide thickness by using device simulation. The critical channel lengths obtained from the device simulation is in good agreement with the empirical relationship for Si MOSFETs. The critical channel lengths in the fabricated SiC MOSFETs are slightly longer than simulation results. The dependence of crystal face orientations on SCEs is hardly observed. Impacts of interface charge on the appearance of SCEs are discussed.     

Static Performance of 20 A, 1200 V 4H-SiC Power MOSFETs at Temperatures of −187°C to 300°C

Silicon carbide (4H-SiC) power metal–oxide–semiconductor field-effect transistors (MOSFETs) have been attracting tremendous attention for high-power applications at a wide range of operating temperatures, owing to their normally-off characteristics, high-speed switching operation, avalanche capability, and low on-resistance. To optimize performance of 4H-SiC MOSFETs for various applications at different temperatures, it is important to understand the mechanisms of temperature dependence of the key parameters, such as on-resistance, threshold voltage, and metal–oxide–semiconductor (MOS) channel mobility. We report on the temperature dependence of the on-resistance of 20 A, 1200 V 4H-SiC power MOSFETs for temperatures ranging from −187°C to 300°C. The MOSFET showed normally-off characteristics throughout the entire experimental temperature range. Different temperature dependences of the total on-resistance in different temperature regimes have been observed. Due to the poor MOS channel mobility and the low free carrier concentration in the inversion channel of the 4H-SiC MOSFET, the MOS channel resistance is the dominant part of the total on-resistance. This was also found to be true in a 4H-SiC long-channel lateral MOSFET.     

Design and fabrication of RESURF MOSFETs on 4H-SiC(0001), (112~0), and 6H-SiC(0001)

Design and fabrication of lateral SiC reduced surface field (RESURF) MOSFETs have been investigated. The doping concentration (dose) of the RESURF and lightly doped drain regions has been optimized to reduce the electric field crowding at the drain edge or in the gate oxide by using device simulation. The optimum oxidation condition depends on the polytype: N/sub 2/O oxidation at 1300/spl deg/C seems to be suitable for 4H-SiC, and dry O/sub 2/ oxidation at 1250/spl deg/C for 6H-SiC. The average inversion-channel mobility is 22, 78, and 68 cm/sup 2//Vs for 4H-SiC(0001), (112~0), and 6H-SiC(0001) MOSFETs, respectively. RESURF MOSFETs have been fabricated on 10-/spl mu/m-thick p-type 4H-SiC(0001), (112~0), and 6H-SiC(0001) epilayers with an acceptor concentration of 1/spl times/10/sup 16/ cm/sup -3/. A 6H-SiC(0001) RESURF MOSFET with a 3-/spl mu/m channel length exhibits a high breakdown voltage of 1620 V and an on-resistance of 234 m/spl Omega//spl middot/cm/sup 2/. A 4H-SiC(112~0) RESURF MOSFET shows the characteristics of 1230 V-138 m/spl Omega//spl middot/cm/sup 2/.     

Low frequency noise in 6H-SiC MOSFET's

The noise spectra for n-channel, depletion-mode MOSFETs fabricated in 6H-SiC material were measured from 1-10⁵ Hz at room temperature. Devices were biased in the linear regime, where the noise spectra was found to be dependent upon the drain-to-source bias current density. At a drain-to-source current of 50 μA for MOSFETs with a W/L of 400 μm/4 μm, the measured drain-to-source noise power spectral density was found to be A/(f^λ), with A being 2.6×10^-12 V², and λ being between 0.73 and 0.85, indicating a nonuniform spatial trap density skewed towards the oxide-semiconductor interface. The measured Hooge parameter (α_H) was 2×10^-5. This letter represents the first reported noise characterization of 6H-SiC MOSFET's     

氧化后退火技术对SiO2/4H-SiC界面态密度的影响

采用等离子体增强化学气相沉积(PECVD)低温处理和高温快速退火的技术,研究了退火条件对SiO2/4H-SiC界面态密度的影响.在n型4H-SiC外延片上高温干氧氧化50 nm厚的SiO2层并经N2原位退火,随后在PECVD炉中对样品进行350℃退火气氛为PH3,N2O,H2和N2的后退火处理,之后进行高温快速退火,最后制备Al电极4H-SiC MOS电容.I-V和C-V测试结果表明,各样品的氧化层击穿场强均大于9 MV/cm,PH3处理可以降低界面有效负电荷和近界面氧化层陷阱电荷,但PH3处理样品的界面态密度比N2O处理的结果要高.经N2O氛围PECVD后退火样品在距离导带0.2和0.4 eV处的界面态密度分别约为1.7× 1012和4×1011eV-1·cm-2,有望用于SiC MOSFET器件的栅氧处理.     

Accumulation-layer electron mobility in n-channel 4H-SiC MOSFETs

Accumulation-layer electron mobility in n-channel depletion-mode metal oxide semiconductor field effect transistors (MOSFETs) fabricated in 4H-SiC was investigated using Hall-measurements. The accumulation-layer mobility showed a smooth transition from the bulk value (~350 cm²/V-s) in the depletion regime into accumulation (~200 cm²/V-s). In contrast, the field-effect mobility, extracted from the transconductance, was found to be much lower (~27 cm²/V-s), due to the trapping of the field-induced carriers by interface states. Though the current in depletion/accumulation-mode MOSFETs can be high due to the contribution of bulk conduction resulting in low on-resistance, carrier trapping will cause the transconductance to be low in the accumulation regime     

1580-V–40-$hbox{m}Omegacdot hbox{cm}^{2}$ Double-RESURF MOSFETs on 4H-SiC $(hbox{000}bar{hbox{1}})$

Double-reduced-surface-field (RESURF) MOSFETs with $hbox{N}_{2}hbox{O}$ -grown oxides have been fabricated on the 4H-SiC $(hbox{000} bar{hbox{1}})$ face. The double-RESURF structure is effective in reducing the drift resistance, as well as in increasing the breakdown voltage. In addition, by utilizing the 4H-SiC $(hbox{000}bar{hbox{1}})$ face, the channel mobility can be increased to over 30 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, and hence, the channel resistance is decreased. As a result, the fabricated MOSFETs on 4H-SiC $( hbox{000}bar{hbox{1}})$ have demonstrated a high breakdown voltage $(V_{B})$ of 1580 V and a low on-resistance $(R_{rm ON})$ of 40 $hbox{m}Omega cdothbox{cm}^{2}$. The figure-of-merit $(V_{B}^{2}/R_{rm ON})$ of the fabricated device has reached 62 $hbox{MW/cm}^{2}$, which is the highest value among any lateral MOSFETs and is more than ten times higher than the “Si limit.”      

Low-power and high-stability SRAM technology using alaser-recrystallized p-channel SOI MOSFET

Laser recrystallization of p-channel SOI MOSFETs on an undulated insulating layer is demonstrated for SRAMs with low power and high stability. Self-aligned p-channel SOI MOSFETs for loads are stacked over bottom n-channel bulk MOSFETs for both drivers and transfer gates. A sufficient laser power assures the same leakage currents between SOI MOSFETs fabricated on an undulated insulating layer in memory cell regions and on an even insulating layer in field regions. The on/off ratio of the SOI MOSFETs is increased by a factor of 10⁴, and the source-drain leakage current is decreased by a factor of 10-10² compared with those of polysilicon thin-film transistors (TFTs) fabricated by using low-temperature regrowth of amorphous silicon. A test 256-kb SRAM fabricated this technology shows improved stand-by power dissipation and cell stability. The process steps can be decreased to 83% of those TFT load SRAMs if both the peripheral circuit and memory cells are made with p-channel SOI and n-channel bulk MOSFETs     

High channel mobility in normally-off 4H-SiC buried channel MOSFETs

We have fabricated buried channel (BC) MOSFETs with a thermally grown gate oxide in 4H-SiC. The gate oxide was prepared by dry oxidation with wet reoxidation. The BC region was formed by nitrogen ion implantation at room temperature followed by annealing at 1500°C. The optimum doping depth of the BC region has been investigated. For a nitrogen concentration of 1×10¹⁷ cm^-3, the optimum depth was found to be 0.2 μm. Under this condition, a channel mobility of 140 cm²/Vs was achieved with a threshold voltage of 0.3 V. This channel mobility is the highest reported so far for a normally-off 4H-SiC MOSFET with a thermally grown gate oxide     

Effects of wet oxidation/anneal on interface properties ofthermally oxidized SiO2/SiC MOS system and MOSFET's

Effects of wet atmosphere during oxidation and anneal on thermally oxidized p-type and n-type MOS interface properties were systematically investigated for both 4H- and 6H-SiC. Deep interface states and fixed oxide charges were mainly discussed. The wet atmosphere was effective to reduce a negative flatband shift caused by deep donor-type interface states in p-type SiC MOS capacitors. Negative fixed charges, however, appeared near the interface during wet reoxidation anneal. In n-type SIC MOS capacitors, the flatband shift indicated a positive value when using wet atmosphere. The relation between interface properties and characteristics of n-channel planar 6H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs) was also investigated. There was little relation between the interface properties of p-type MOS capacitors and the channel mobility of MOSFETs. The threshold voltage of MOSFETs processed by wet reoxidation anneal was higher than that of without reoxidation anneal. A clear relation between the threshold voltage and the channel mobility was observed in MOSFETs fabricated on the same substrate     

Effect of process variations and ambient temperature on electron mobility at the SiO/sub 2//4H-SiC interface

We report the effect of processing variables on the inversion layer electron mobility of (0001)-oriented 4H-SiC n-channel MOSFETs. The process variables investigated include: i) implant anneal temperature and ambient; ii) oxidation procedure; iii) postoxidation annealing in nitric oxide (NO); iv) type of gate material, and v) high-temperature ohmic contact anneal. Electron mobility is significantly increased by a postoxidation anneal in NO, but other process variations investigated have only minor effects on the channel mobility. We also report the temperature dependence of electron mobility for NO and non-NO annealed n-channel MOSFETs.     

4H-SiC MOSFETs utilizing the H2 surface cleaningtechnique

The H₂ cleaning technique was examined as the precleaning of the gate oxidation for 4H-SiC MOSFETs. The device had a channel width and length of 150 and 100 μm, fabricated on the p-type epitaxial layer of 3×10¹⁶ cm^-3. The gate oxidation was performed after the conventional RCA cleaning, and H₂ annealing at 1000°C. The obtained channel mobility depends on the pre-cleaning process strongly, and was achieved 20 cm²/N s in the H₂ annealed sample. The effective interface-state density was also measured by the MOS capacitors fabricated on the same chips, resulting 1.8×10¹² cm^-2 from the photo-induced C-V method     

A 475-V high-voltage 6H-SiC lateral MOSFET

High-voltage lateral MOSFET's on 6H- and 4H-SiC have been fabricated with 400-475 V breakdown voltage using the RESURF principle. An MOS electron inversion layer mobility of about 50 cm²/V-s is obtained on 6H-SiC wafers. This mobility is high enough such that the specific on-resistance of the 6H-SiC MOSFET's (~0.29-0.77 Ω-cm²) is limited by the resistance of the drift layer, as desired. However, the implanted drift layer resistance is about ten times higher than expected for the implant dose used. Design and process changes are described to decrease the on-resistance and increase the breakdown voltage. For 4H-SiC, extremely low mobility was obtained, which prevents satisfactory device operation     

High channel mobility in inversion layers of 4H-SiC MOSFETs byutilizing (112¯0) face

A dramatic improvement of inversion channel mobility in 4H-SiC MOSFETs was successfully achieved by utilizing the (112¯0) face: 17 times higher (95.9 cm²/Vs) than that on the conventional (0001) Si-face (5.59 cm²/Vs). A low threshold voltage of MOSFETs on the (112¯0) face indicates that the (112¯0) MOS interface has fewer negative charges than the (0001) MOS interface. Small anisotropy of channel mobility in 4H-SiC MOSFETs (μ_(11¯00)/μ₍₀₀₀₁₎=0.85) reflects the small anisotropy in bulk electron mobility