A straightforward analytical method for extraction of semiconductor device transient thermal parameters

Most of the thermal characterization of packaged semiconductor devices is carried out in the time domain by measuring and recording the values of a temperature sensitive electrical parameter (TSEP) as a function of time, during the heating or cooling transient caused by the application of a given power function, generally a step, to the device. Although this time response contains, within measurement resolution, all the relevant information about device thermal behaviour, the “packed” form of this information is not so convenient for its immediate use when we want to obtain a thermal model for further simulation or extract some information on device structure. Real and imaginary parts of device frequency response are a better way of dealing with measurement results because its “unpacked” form leads easily to thermal model and structural information.In this paper we derive a direct analytical calculation of the frequency response from the scalar time domain response as well as an approximate method to obtain an equivalent thermal model.     

A new technique in the global reliability of cyclic communications network

The global reliability of a communications network is the probability that given any pair of nodes, there exists a viable path between them. A characterization of connectivity, for a given class of networks, can enable one to find this reliability. Such a characterization is described for a useful class of undirected networks called “daisy-chained” or “braided” networks. This leads to a new method of quickly computing the global reliability of these networks. Asymptotic behavior in terms of component reliability is related to geometric properties of the given graph. Generalization of the technique is discussed.     

Generic qualification of semi-custom IC product families

The problem of verifying the integrity, and quantifying the reliability of semi-custom IC product families is addressed, and one possible approach to efficient “generic qualification” is outlined. The approach used relies on qualification via a set of chips specifically designed for this purpose, rather than via one or more “product” chips. Key features integrated into these test vehicles are that the entire “cell library” is represented, as well as that the “worst case” features are maximized.     

Reliability of microBGA assembly using no-flow underfill

In this paper, the reliability of the microBGA assembly using no-flow underfill is studied by thermal shock and bending cycle. Recently, a more promising underfill technology so-called “no-flow underfill” has been invented to cope with the limitations, which promises low cost assembly. The research results of self-alignment about no-flow underfill show that the self-alignment of microBGA using no-flow underfill is inferior to that using flux. There is residual displacement more or less in various offset volumes. Therefore, the effect of no-flow underfill on reliability of microBGA assembly needs to be investigated systematically. In this study, samples are reflowed with an optimized “rapid ramp” temperature profile, and using flux and no-flow underfill, respectively. One group of samples are subjected to thermal shock at temperature −40–125°C, and dwell time 15 min. Another group of samples is subjected to cyclic bending at a bending speed of 300 mm/min between 500 and −500 μ at the center of a microBGA package. The fatigue lifetime distribution is examined with the aid of “Weibull” method to investigate the effect of no-flow underfill on the reliability of microBGA assembly, and the failure mechanism is investigated by using the scanning electron microscope. Our experiment results show that the no-flow underfill can greatly enhance the mechanical fatigue lifetime. The underfilled material improves the stress distribution in solder joints. For assemblies with no underfills, the fracture always occurs in the outermost solder joint. The issue is improved by underfilling with no-flow underfill. However, the no-flow underfill cannot improve the thermal reliability of microBGA assembly, because the coefficient of thermal expansion (CTE) of no-flow underfill is too great at present. It is necessary to reduce the no-flow underfill CTE, so as to apply actually to BGA and CSP etc. Moreover, it is displayed that the fatigue lifetime of the residual displacement solder is less than 50% of that of the non-misaligned solder. The residual displacement is formed when the misalignment is >25% during mounting. Therefore, when the no-flow underfill is used in microBGA assembly, care must be taken to keep the mount position, and misalignment <25%.     

Temperature acceleration of breakdown and quasi-breakdown phenomena in ultra-thin oxides

A study of the electric field and temperature dependence of the breakdown and quasi-breakdown phenomena is presented for 3.5 nm ultra-thin SiO₂ gate oxides. Using à methodology based on the competing mecanism concept between breakdown and quasi-breakdown processes, quasi-breakdown activation energy as well as acceleration factor are determined. It is demonstrated on these 3.5nm gate oxides that the quasi-breakdown temperature activation energy is almost temperature independent on the contrary to the breakdown one. Moreover, it has been shown that the temperature dependence of the breakdown acceleration factor and the electric field dependence of the temperature activation energy cannot be explained by a pure “E” and “1/E” models, but can be interpreted by the “E” model if at least two types of molecular defect states are considered.     

SiLK™ etch optimization and electrical characterization for 0.13 μm interconnects

This paper is focused on the optimization of reactive ion etching (RIE) process of low-k polymeric spin-on dielectric (SOD) material, SiLK™ (Trade mark of Dow Chemical, USA), for 0.13 μm Cu-low-k interconnects technology and subsequent electrical characterization of the metallization. Damascene metallization of SiLK™ film was integrated with dual hardmask scheme and “trench first” approach. Etch processes for single damascene metal trench and dual damascene via and metal2 trench structures were developed and evaluated. Effect of SiN and SiC films used as one of the hard mask layers and copper cap layers for single and dual damascene formation were also evaluated. The advantages of using SiC over SiN layer as one of the (bottom) dual hardmask layers were demonstrated through the results of electrical performance. Integration issues related to process development were analyzed and discussed. Electrical and reliability performance of testing vehicles associated to different etch criteria were studied. Electrical yield of >90% was obtained for the structures under study, which indicated the wide process margin. The consistency of processes was further demonstrated through the successful integration of eight metal layers with SiLK™ dielectric film.     

Stress effects of epoxy adhesives on ceramic substrates and magnetics

Conventional, high T_g adhesives can result in cracking of magnetics (transformers and inductors) and ceramic substrates after cure or after thermal cycling and extended stress screens. Cracking in substrates may result in electrical “opens” in underlying circuitry.Cracks in large (1.8×3.650 in.²) substrates under magnetics (ferrite cores/inductors and wire-wound transformers) have been observed after screen testing. Cracks in the substrates are most likely due to stress transfer in centrifuge in combination with “off-axis” stresses in thermal cycling and environmental stress screening. Cracks are also observed in the epoxy fillet. Stress modeling is often difficult or impossible due to complex routines that are required and the lack of material characteristics such as Young’s modulus, Poisson’s ratio, and stress/strain curves for materials. Direct comparison of materials is often not possible due to missing vendor data or data from different vendors performed under different cure conditions using varying test methods.A series of materials with varying room-temperature modulus characteristics ranging from over 1×10⁶ to approximately 19,000 psi were evaluated for material characteristics and reliability in screen testing using sequential thermal cycling and centrifuge. Test vehicles were constructed using four sets of magnetics in packaged low-temperature co-fired ceramic (LTCC) substrates.The specific objectives of this work were to select, evaluate, and recommend a new adhesive for core-and-coil attachment. Evaluations performed for the materials selected include (1) material testing and preliminary, first-order stress calculations, (2) testing and evaluation of actual parts, and (3) correlation of results using NASTRAN (NASA structural analysis) mechanical modeling.This material was, in part, previously presented at the 1999 International Microelectronics and Packaging Society (IMAPS), is copyright 1999 by IMAPS, and is reprinted with permission from the Proceedings of the 1999 International Symposium on Microelectronics, pp. 896–902, 26–28 October, 1999.     

Redundancy optimization problems for systems with dependent failure rates

The present study is concerned with some redundancy optimization models for “load-sharing” devices. The models considered here enable one to examine the extent to which the optimal allocation of redundancies is affected if a model based on the assumption of mutual independence of components is used in situations where there is actual “load-sharing”.     

Cost-benefit analysis of a two-server, two-unit, warm standby system with different types of failure

This paper deal with a two-server, two-unit redundant system in which one unit is operative and the other is a warm standby. The operative unit can fail completely, either directly from the normal state or via a partial failure, while the warm standby unit only fails due to minor faults within it. One repairman is “regular”, he always remains with the system, and the other is an “expert” who is called when needed. The system has been analysed to determine the various reliability measures by using semi-Markov processes and regenerative processes. Numerical results and some graphs pertaining to a particular case are also included.     

Characterization of bump arrays at RF/microwave frequencies

A systematic procedure for the characterization of complex bump configurations at RF and microwave frequencies, is presented. Beginning with simple arrangements—single- and two-coupled bumps—full-wave electromagnetic (EM) field analysis, circuit simulations and RF measurements were used for the development and validation of their respective equivalent circuit models. These models were then extended to characterize three-coupled bumps, both in linear and triangular configurations. Finally, a combination of all the electrical parameters obtained from these simple bump configurations was used to characterize a complete bump array, taking into consideration that for pitches used in most high-speed packages, EM coupling between a bump and its “next but one” neighbor can be neglected.     

Compound semiconductor activation energy in humidity

Product reliability investigations typically include accelerated humidity testing. Originally, the “standard” test was a biased 85 °C/85% relative humidity (RH) lifetest for 1000 h. Recently, a substitute accelerated version of this test has been used. The accelerated version is called highly accelerated stress test (HAST). The HAST conditions are also biased, at 130 °C, 85%RH, and approximately 18 PSI overpressure. The duration of the HAST test is normally 96–100 h – to be equivalent to the 85/85 test. This study is intended to investigate thermal acceleration and show that equivalent HAST tests on compound semiconductors are more highly accelerated and could be conducted with much shorter durations.     

Determination of the thermal conductivity of composite low-k dielectrics for advanced interconnect structures

The increasing use of low-k dielectrics as inter/intralevel insulation materials and the aggressive scaling of advanced interconnects generate new challenges for thermal and electromigration (EM) solutions. Accurate specification of design rules and EM reliability modeling for interconnect systems require knowledge of the thermal behavior of the systems. A key parameter that characterizes thermal behavior is the thermal conductivity of the inter/intralevel dielectric (ILD). In practical, very large scale integration (VLSI) applications, the metal interconnects are fully embedded in a stacked, composite ILD media, which present challenges for the accurate determination of thermal conductivity. This article uses the “effective thermal conductivity” concept to model such complicated composite media, and to introduce a simple methodology that accurately measures effective and bulk thermal conductivities of various thin dielectric layers in integrated circuits (IC). We present measured effective conductivities of several composite media, including various Cu/low-k dielectric configurations: Cu/SiCOH, Cu/spin-on organic dielectric (SOD), Cu/fluorinated silicate glass (FSG), and a hybrid stack with Cu lines in SOD and Cu vias in undoped silicate glass (USG). Recorded temperature measurements ranged from 30 to 120 °C using a unique combination of fully embedded Cu lines as heater/thermometers, wafer-level temperature–voltage–power measurements, and the Harmon–Gill (H–G) quasi-analytical heat conduction model. We demonstrated optimal agreement between an experimental method and a finite element simulation, which suggests that this unique technique yields accurate and simple thermal conductivity measurements for complicated systems. Our observations show that thermal conductivities of all films in this study increased with rising substrate temperature.     

Software quality assurance considerations

Very few articles dealing with software quality assurance have been published over the past few years; these have been primarily from the military and medical industries. It is interesting to note that many of the topics included or suggested in these articles are presently not in use and the concepts are “relatively unknown”. Effective statistical techniques are basically lacking unfortunately. The “real key” is to understand that software quality assurance is “10 years behind the hardware” as stated by an SWQA department manager in a large military products (DOD) facility. Thus the intent of these offerings is to share some ideas in a very complex and challenging arena; this concept, this methodology has not been able to keep up with the rapid advances required of it and imposed by the primary systems.     

Design of a new test structure for the study of electromigration with early resistance change measurements

A new test structure has been designed in order to perform accurate early resistance change measurements in metal lines submitted to high current stress. This test structure integrates both advantages of the so-called “absolute” and “bridge” techniques, resulting in accurate resistance measurements with a high resolution for both the current-stressed and reference strip. Due to the improved measurement configuration, the aging kinetics of a metal line under current stress can be studied in more detail.     

Generalized formulation of yield, variability, minimax and Taguchi circuit optimization problems

A generalized formulation of several circuit design problems, such as manufacturing yield optimization, circuit performance variability minimization, deterministic and statistical minimax design, Income Index maximization, Taguchi approach, etc., is developed. Several other “intermediate” problems can be defined in a sense similar to the one used in Zadeh's fuzzy set theory. A specific problem is identified by the selection of a generalized membership function ω(·) of the acceptability region, and a sequence of the values of the “smoothing” parameter β. Generalized gradient formulas are developed, and various possible algorithmic implementations discussed. As a result, trade-offs between different design strategies can be investigated by circuit designers, within one coherent methodology.     

Mechanisms of noise sources in microelectromechanical systems

It is well known that several mechanisms of noise generation appear in microelectronic devices, causing thermal noise, shot noise, generation–recombination noise and 1/f noise. Besides these noises, in the case of microelectromechanical systems, specific additional noises appear as a consequence of the fact that the “building blocks” (microcantilevers or membranes) of micromechanical systems have very small geometrical dimensions and mass. Most often, these noises are the consequences of temperature fluctuations caused by dissipative processes in various vibrational structures within the micromechanical systems. This work presents a methodology of calculation of noises, characteristic of microelectromechanical systems and applies it to the calculation of limiting performances of accelerometers, sensing probe cantilevers and thermal infrared detectors.     

Reliability assessment of multi-via Cu-damascene structures by wafer-level isothermal electromigration tests

In this paper, the isothermal wafer-level electromigration test method has been used to compare the resistance to electromigration damage of multi-level structures, realized by dual-damascene copper technology with a variable number of vias. “Upstream” and “downstream” structures have been defined, depending on the metal level where the line under test was located, with respect to the metal level where current and voltage taps were drawn. Not unexpectedly, the most critical current path for electromigration has been found in downstream structures, where the electron flow is entering the line under test. Worthy of note, a well defined dependence of the time to failure on the number of vias has been observed for these structures. Activation energy and current-density acceleration coefficient have been extracted and a quantitative relation is proposed to relate the lifetime expectancy to the number of vias.     

New assembling technique for BGA packages without thermal processes

A new assembling technique for flip-chip mounting without heating processes was developed. The proposed construction is an FR4 substrate with ring shaped connectors. It is a typical flip-chip technology. The chip is placed, with its active part face-down, directly on to the connecting areas of the substrate. The electrical connection is obtained through a mechanical contact between the ring-shaped clips and the chip bumps. The main advantage of the ring-clip-bump attachment technique is the possibility for multi-chip modules repairing without thermal processes. It is a lead-free assembling technology involving only “conventional” processes.     

An analytical effective channel-length modulation model for velocity overshoot in submicron MOSFETs based on energy-balance formulation

A compact analytical model for MOSFET channel-length modulation (CLM) based on momentum and energy-conservation of Boltzmann transport equation as well as quasi-2D formulation is presented. It is consistent with the generalized drift–diffusion formulation including the nonlocal electron temperature, which can be interpreted as being an effective CLM or effective velocity overshoot. The model has a simple familiar form of the “pinch-off” model, with one fitting parameter for the length- and bias-dependent effective saturation field and effective Early voltage. The model can be easily characterized with one measured I_ds–V_ds data and has been verified with submicron technology data for the full range of gate lengths and bias conditions.     

Dual phase probing technique for IC-internal failure analysis

New electron beam probing techniques have been developed which are based on either the subtraction of two stroboscopic phases at two test vectors during the recording of a single image, or the probing of two phases at a single physical point of interest. These are, respectively, the image-based dual phase image, and the point-probing-based dual phase measurement. These new techniques are perfect for IC-internal failure analysis as they enable the detection of “opens” and “stuck-at” errors and can be linked to fault simulation software and a fault dictionary.