一种基于目标延迟约束缓冲器插入的互连优化模型

基于分布式RLC传输线,提出在互连延迟满足目标延迟的条件下,利用拉格朗日函数改变插入缓冲器数目与尺寸来减小互连功耗和面积的优化模型. 在65nm CMOS工艺下,对两组不同类型的互连线进行计算比较,验证该模型在改善互连功耗与面积方面的优点. 此模型更适合全局互连线的优化,而且互连线越长,优化效果越明显,能够应用于纳米级SOC的计算机辅助设计和集成电路优化设计.     

Maximal Delay Reduction for RLC-Based Multi-Source Multi-Sink Bus with Repeater Insertion

Signal propagation delay on a multi-source multi-sink bidirectional bus has a dominant effect on high-performance chips. This work presents a novel greedy algorithm that minimizes the critical propagation delay of an RLC-based bus. Based on the topology of a multi-source multi-sink bus and the RLC delay model, the proposed algorithm inserts signal repeaters into the critical path of the RLC-based bus and adjusts their sizes to minimize the maximal propagation delay. This procedure is repeated until no additional improvement is needed. Several buses with various topologies are tested using the proposed algorithm in deep submicron technologies. Experimentally, the critical delay in an RLC-based bus can be reduced dramatically by up to 62.4% with inserted repeater sizes of 24 and execution time of 1.65 s on average. Moreover, average delay reduction, repeater sizes, and running time for 0.18 μm technology are 5.8%, 6.4%, and 26.2%, respectively, better than those of 0.35 μm. Additionally, the topologies of all of the RLC-based buses with inserted repeaters in deep submicron technologies are simulated using HSPICE. The error ratio in the critical delay of a bus with inserted repeaters determined by comparison with HSPICE is 2.7% on average. The proposed algorithm is simple and extremely practical.     

一种基于目标延迟约束缓冲器插入的互连优化模型

基于分布式RLC传输线,提出在互连延迟满足日标延迟的条件下,利用托格朗日函数改变插入缓冲器数目与尺寸来减小互连功耗和面积的优化模型.在65nm CMOS工艺下,对两组不同类型的互连线进行计算比较,验证该模型在改善互连功耗与面积方面的优点.此模碰更适合全局瓦连线的优化,而且互连线越长,优化效果越明显,能够应用于纳米级SoC的计算机辅助设计和集成电路优化设计.     

An Analysis of Reducing Communication Delay in Network-on-Chip Interconnect Architecture

This paper presents an Enhanced Clustered Mesh (EnMesh) topology for a Network-on-Chip architecture in order to reduce the communication delay between remote regions by considering the physical positions of remote nodes. EnMesh topology includes short paths between diagonal regions to ensure fast communication among remote nodes. The performance and silicon area overhead of EnMesh are analyzed and compared to those of state-of-the-art topologies such as Mesh, Torus, and Butterfly-Fat-Tree (BFT). Experimental results demonstrate that EnMesh outperforms other existing regular topologies in terms of throughput, latency, packet loss rate, and silicon area overhead.     

VLSI互联线的延时优化研究

首先对互连线模型进行了分析,介绍了插入缓冲器来减小长线延时的方法,然后通过具体计算分析了缓冲器插入的位置、数量,以及尺寸对连线延迟的影响,得出了理论上最理想的优化方案,并给出了结合实际物理设计的优化方案和算法.最后,对一条长互联线的延迟进行了仿真计算,结果证明所给出的算法可有效地减小延时.     

考虑温度分布效应的RLC互连延时分析

基于等效Elmore延时模型和分段分布参数思想提出了一种RLC互连延时解析模型,该模型同时考虑了瓦连线温度分布效应和电感效应对延时的影响,更加贴近实际情况,在实际应用中具有重要意义.仿真结果表明,对于简单的RLC互连树形结构而言,所提模型的延时误差在10%以内,且仿真效率高.     

考虑温度分布效应的RLC互连延时分析

基于等效Elmore延时模型和分段分布参数思想提出了一种RLC互连延时解析模型,该模型同时考虑了互连线温度分布效应和电感效应对延时的影响,更加贴近实际情况,在实际应用中具有重要意义. 仿真结果表明,对于简单的RLC互连树形结构而言,所提模型的延时误差在10%以内,且仿真效率高.     

考虑工艺波动影响的RLC互连统计延时

该文提出了一种考虑工艺波动的统计RLC互连延时分析方法。文中首先给出了考虑工艺波动的寄生参数和矩的构建方法,然后基于Weibull分布给出了RLC互连的统计延时模型。所提方法同样适用于已有的延时模型如Elmore模型,等效Elmore模型和D2M模型。通过对几种模型的比较,表明,基于Weibull分布的RLC互连的统计延时模型是最精确的,和HSPICE相比,50%延时误差最大0.11%,蒙特卡洛分析中的均值和平均偏差误差最大2.02%。     

互连线延时和串扰的估算方法

本文综述了集成电路中互连线的延时和串扰的估算方法，分析了各种估算方法的精度和复杂度，同时提出了今后互连线延时和串扰估算所需要解决的新问题。     

Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits

In this paper, the impact of thermal effects on low-power repeater insertion methodology is studied. An analytical methodology for thermal-aware repeater insertion that includes the electrothermal coupling between power, delay, and temperature is presented, and simulation results with global interconnect repeaters are discussed for 90- and 65-nm technology. Simulation results show that the proposed thermal-aware methodology can save 17.5% more power consumed by the repeaters compared to a thermal-unaware methodology for a given allowed delay penalty. In addition, the proposed methodology also results in a lower chip temperature, and thus, extra leakage power savings from other logic blocks.     

VDSM集成电路互连特性及RC延迟研究

利用多层金属导体寄生电容模型,详细分析了不同的金属互连线参数对寄生电容的影响,并采用一个闭合公式对超深亚微米级集成电路中的RC互连延迟进行估计.结果表明,当金属导线的纵横比接近2时,线间耦合电容对互连总电容的影响将占主导地位.在超深亚微米工艺条件下,当金属线宽和间距比例W/P的最优质值为0.5～0.6时,计算的互连延迟为最小.此外,还给出了低介电常数材料对互连线电容和延迟的影响,为超深亚微米级的集成电路设计与实现提供有益的参考.     

基于时域延时的 ISAR 二维调制转发干扰

对逆合成孔径雷达(ISAR)来说,弹道中段目标的微多普勒效应实际上是一种方位向上的余弦调相效应,余弦调相 函数能实现频谱搬移,在方位向上产生多假目标。针对工程上无法实现对ISAR 信号方位向余弦调相的难题和方位向余 弦调相对距离向不起作用的问题,提出了一种基于时域延时的ISAR 二维调制转发干扰。该干扰在实现方位向余弦调相 的同时,能在距离向上形成一种新型盲移频的条带式干扰。 仿真结果表明:合适的延时参数将使目标淹没在距离-方位向上形成的多个假目标带中。     

转发式欺骗干扰时延控制算法

无人机卫星导航欺骗技术在现代导航战中越来越受到广泛的关注，其中转发式欺骗干扰因其无需获得信号结构的先验知识，在军码导航领域比生成式欺骗干扰更具使用价值。目前的军码转发信号普遍以转发接收天线点的位置坐标作为基础进行定点静止转发，在对无人机欺骗干扰时，信号置信度不高，干扰效果不佳。提出一种转发干扰时延算法，根据转发坐标需求计算不同卫星信号的时延量，可根据欺骗策略实时调整转发坐标，提高干扰成功率。最后通过实验验证，提出的时延算法得到的转发坐标误差在米级范围，验证了算法的正确性。     

深亚微米集成电路设计中的互连线延迟问题

深亚微米集成电路的互连线延迟是设计中需十分重视并必须解决的问题。本文讨论了影响互连线延迟的因素并对深亚微米物理设计的关键步骤中如何考虑并解决互连线延迟问题进行叙述和讨论。     

VLSI互连线的全局优化算法

介绍了通过同时插入缓冲嚣和优化线宽达到互连线时延最小化的方法。为了同时插入缓冲器、优化缓冲嚣尺寸和优化线宽，可以扩展MASM(改进激活集合法)算法。计算结果表明，该算法非常有效。     

驱动复杂RLC互连树的逻辑门延时

提出了一个用于估计RL C互连树驱动点导纳的闭端等效π模型,并将其用于驱动复杂RL C互连树的逻辑门延时的估计中.与其他方法相比,它具有结构简单、精度较高的特点     

驱动复杂RLC互连树的逻辑门延时

提出了一个用于估计RLC互连树驱动点导纳的闭端等效π模型,并将其用于驱动复杂RLC互连树的逻辑门延时的估计中.与其他方法相比,它具有结构简单、精度较高的特点.     

Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models

Interconnects constitute a dominant source of circuit delay for modern chip designs. The variations of critical dimensions in modern VLSI technologies lead to variability in interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. In this paper, a practical interconnect delay and slew analysis technique is presented to facilitate efficient evaluation of wire performance variability. By harnessing a collection of computationally efficient procedures and closed-form formulas, process variations are directly mapped into the variability of the output delay and slew. An efficient method based on sensitivity analysis is implemented to calculate driving point models under variations for gate-level timing analysis. The proposed adjoint technique not only provides statistical performance variations of the interconnect network under analysis, but also produces delay and slew expressions parameterized in the underlying process variations in a quadratic parametric form. As such, it can be harnessed to enable statistical timing analysis while considering important statistical correlations. Our experimental results have indicated that the presented analysis is accurate regardless of location of sink nodes and it is also robust over a wide range of process variations.     

热效应致RLC互连延时变化研究

针对热效应导致RLC互连延时增加的现象进行了研究.提出了一种温度依赖的RLC互连延时模型.该模型可以用以量化热效应对互连延时的影响.仿真结果显示,对于RLC互连,温度每增加20℃,延时将会增加5%-6%.     

High-Density Solder Bump Interconnect for MEMS Hybrid Integration

An ultra high-density hybrid integration for micro-electromechanical system (MEMS) mirror chips with several thousand inputs/outputs has been developed. The integration scheme involving flip-chip assembly provides electrical signal to individual mirrors, which is compatible with postprocessing steps of selectively removing the silicon handle and releasing the MEMS mirrors. For the first time, to our knowledge, solder deposition and flip-chip bonding of 3-mum bumps on 5-mum centers of a large array has been demonstrated.