共查询到20条相似文献,搜索用时 0 毫秒
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Signal propagation delay on a multi-source multi-sink bidirectional bus has a dominant effect on high-performance chips. This
work presents a novel greedy algorithm that minimizes the critical propagation delay of an RLC-based bus. Based on the topology
of a multi-source multi-sink bus and the RLC delay model, the proposed algorithm inserts signal repeaters into the critical
path of the RLC-based bus and adjusts their sizes to minimize the maximal propagation delay. This procedure is repeated until
no additional improvement is needed. Several buses with various topologies are tested using the proposed algorithm in deep
submicron technologies. Experimentally, the critical delay in an RLC-based bus can be reduced dramatically by up to 62.4%
with inserted repeater sizes of 24 and execution time of 1.65 s on average. Moreover, average delay reduction, repeater sizes,
and running time for 0.18 μm technology are 5.8%, 6.4%, and 26.2%, respectively, better than those of 0.35 μm. Additionally,
the topologies of all of the RLC-based buses with inserted repeaters in deep submicron technologies are simulated using HSPICE.
The error ratio in the critical delay of a bus with inserted repeaters determined by comparison with HSPICE is 2.7% on average.
The proposed algorithm is simple and extremely practical. 相似文献
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Hasan Furhad Mohammad A. Haque Cheol-Hong Kim Jong-Myon Kim 《Wireless Personal Communications》2013,73(4):1403-1419
This paper presents an Enhanced Clustered Mesh (EnMesh) topology for a Network-on-Chip architecture in order to reduce the communication delay between remote regions by considering the physical positions of remote nodes. EnMesh topology includes short paths between diagonal regions to ensure fast communication among remote nodes. The performance and silicon area overhead of EnMesh are analyzed and compared to those of state-of-the-art topologies such as Mesh, Torus, and Butterfly-Fat-Tree (BFT). Experimental results demonstrate that EnMesh outperforms other existing regular topologies in terms of throughput, latency, packet loss rate, and silicon area overhead. 相似文献
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VLSI互联线的延时优化研究 总被引:3,自引:2,他引:1
首先对互连线模型进行了分析,介绍了插入缓冲器来减小长线延时的方法,然后通过具体计算分析了缓冲器插入的位置、数量,以及尺寸对连线延迟的影响,得出了理论上最理想的优化方案,并给出了结合实际物理设计的优化方案和算法.最后,对一条长互联线的延迟进行了仿真计算,结果证明所给出的算法可有效地减小延时. 相似文献
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Ja Chun Ku Ismail Y. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(8):963-970
In this paper, the impact of thermal effects on low-power repeater insertion methodology is studied. An analytical methodology for thermal-aware repeater insertion that includes the electrothermal coupling between power, delay, and temperature is presented, and simulation results with global interconnect repeaters are discussed for 90- and 65-nm technology. Simulation results show that the proposed thermal-aware methodology can save 17.5% more power consumed by the repeaters compared to a thermal-unaware methodology for a given allowed delay penalty. In addition, the proposed methodology also results in a lower chip temperature, and thus, extra leakage power savings from other logic blocks. 相似文献
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利用多层金属导体寄生电容模型,详细分析了不同的金属互连线参数对寄生电容的影响,并采用一个闭合公式对超深亚微米级集成电路中的RC互连延迟进行估计.结果表明,当金属导线的纵横比接近2时,线间耦合电容对互连总电容的影响将占主导地位.在超深亚微米工艺条件下,当金属线宽和间距比例W/P的最优质值为0.5~0.6时,计算的互连延迟为最小.此外,还给出了低介电常数材料对互连线电容和延迟的影响,为超深亚微米级的集成电路设计与实现提供有益的参考. 相似文献
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无人机卫星导航欺骗技术在现代导航战中越来越受到广泛的关注,其中转发式欺骗干扰因其无需获得信号结构的先验知识,在军码导航领域比生成式欺骗干扰更具使用价值。目前的军码转发信号普遍以转发接收天线点的位置坐标作为基础进行定点静止转发,在对无人机欺骗干扰时,信号置信度不高,干扰效果不佳。提出一种转发干扰时延算法,根据转发坐标需求计算不同卫星信号的时延量,可根据欺骗策略实时调整转发坐标,提高干扰成功率。最后通过实验验证,提出的时延算法得到的转发坐标误差在米级范围,验证了算法的正确性。 相似文献
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Xiaoji Ye Liu F.Y. Peng Li 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(8):913-926
Interconnects constitute a dominant source of circuit delay for modern chip designs. The variations of critical dimensions in modern VLSI technologies lead to variability in interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. In this paper, a practical interconnect delay and slew analysis technique is presented to facilitate efficient evaluation of wire performance variability. By harnessing a collection of computationally efficient procedures and closed-form formulas, process variations are directly mapped into the variability of the output delay and slew. An efficient method based on sensitivity analysis is implemented to calculate driving point models under variations for gate-level timing analysis. The proposed adjoint technique not only provides statistical performance variations of the interconnect network under analysis, but also produces delay and slew expressions parameterized in the underlying process variations in a quadratic parametric form. As such, it can be harnessed to enable statistical timing analysis while considering important statistical correlations. Our experimental results have indicated that the presented analysis is accurate regardless of location of sink nodes and it is also robust over a wide range of process variations. 相似文献
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Basavanhally N. Lopez D. Aksyuk V. Ramsey D. Bower E. Cirelli R. Ferry E. Frahm R. Gates J. Klemens F. Lai W. Low Yee Mansfield W. Chien-Shing Pai Papazian R. Pardo F. Sorsch T. Watson P. 《Advanced Packaging, IEEE Transactions on》2007,30(4):622-628
An ultra high-density hybrid integration for micro-electromechanical system (MEMS) mirror chips with several thousand inputs/outputs has been developed. The integration scheme involving flip-chip assembly provides electrical signal to individual mirrors, which is compatible with postprocessing steps of selectively removing the silicon handle and releasing the MEMS mirrors. For the first time, to our knowledge, solder deposition and flip-chip bonding of 3-mum bumps on 5-mum centers of a large array has been demonstrated. 相似文献