共查询到20条相似文献,搜索用时 15 毫秒
1.
Signal propagation delay on a multi-source multi-sink bidirectional bus has a dominant effect on high-performance chips. This
work presents a novel greedy algorithm that minimizes the critical propagation delay of an RLC-based bus. Based on the topology
of a multi-source multi-sink bus and the RLC delay model, the proposed algorithm inserts signal repeaters into the critical
path of the RLC-based bus and adjusts their sizes to minimize the maximal propagation delay. This procedure is repeated until
no additional improvement is needed. Several buses with various topologies are tested using the proposed algorithm in deep
submicron technologies. Experimentally, the critical delay in an RLC-based bus can be reduced dramatically by up to 62.4%
with inserted repeater sizes of 24 and execution time of 1.65 s on average. Moreover, average delay reduction, repeater sizes,
and running time for 0.18 μm technology are 5.8%, 6.4%, and 26.2%, respectively, better than those of 0.35 μm. Additionally,
the topologies of all of the RLC-based buses with inserted repeaters in deep submicron technologies are simulated using HSPICE.
The error ratio in the critical delay of a bus with inserted repeaters determined by comparison with HSPICE is 2.7% on average.
The proposed algorithm is simple and extremely practical. 相似文献
2.
Hasan Furhad Mohammad A. Haque Cheol-Hong Kim Jong-Myon Kim 《Wireless Personal Communications》2013,73(4):1403-1419
This paper presents an Enhanced Clustered Mesh (EnMesh) topology for a Network-on-Chip architecture in order to reduce the communication delay between remote regions by considering the physical positions of remote nodes. EnMesh topology includes short paths between diagonal regions to ensure fast communication among remote nodes. The performance and silicon area overhead of EnMesh are analyzed and compared to those of state-of-the-art topologies such as Mesh, Torus, and Butterfly-Fat-Tree (BFT). Experimental results demonstrate that EnMesh outperforms other existing regular topologies in terms of throughput, latency, packet loss rate, and silicon area overhead. 相似文献
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VLSI互联线的延时优化研究 总被引:1,自引:2,他引:1
首先对互连线模型进行了分析,介绍了插入缓冲器来减小长线延时的方法,然后通过具体计算分析了缓冲器插入的位置、数量,以及尺寸对连线延迟的影响,得出了理论上最理想的优化方案,并给出了结合实际物理设计的优化方案和算法.最后,对一条长互联线的延迟进行了仿真计算,结果证明所给出的算法可有效地减小延时. 相似文献
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Ja Chun Ku Ismail Y. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(8):963-970
In this paper, the impact of thermal effects on low-power repeater insertion methodology is studied. An analytical methodology for thermal-aware repeater insertion that includes the electrothermal coupling between power, delay, and temperature is presented, and simulation results with global interconnect repeaters are discussed for 90- and 65-nm technology. Simulation results show that the proposed thermal-aware methodology can save 17.5% more power consumed by the repeaters compared to a thermal-unaware methodology for a given allowed delay penalty. In addition, the proposed methodology also results in a lower chip temperature, and thus, extra leakage power savings from other logic blocks. 相似文献
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利用多层金属导体寄生电容模型,详细分析了不同的金属互连线参数对寄生电容的影响,并采用一个闭合公式对超深亚微米级集成电路中的RC互连延迟进行估计.结果表明,当金属导线的纵横比接近2时,线间耦合电容对互连总电容的影响将占主导地位.在超深亚微米工艺条件下,当金属线宽和间距比例W/P的最优质值为0.5~0.6时,计算的互连延迟为最小.此外,还给出了低介电常数材料对互连线电容和延迟的影响,为超深亚微米级的集成电路设计与实现提供有益的参考. 相似文献
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Basavanhally N. Lopez D. Aksyuk V. Ramsey D. Bower E. Cirelli R. Ferry E. Frahm R. Gates J. Klemens F. Lai W. Low Yee Mansfield W. Chien-Shing Pai Papazian R. Pardo F. Sorsch T. Watson P. 《Advanced Packaging, IEEE Transactions on》2007,30(4):622-628
An ultra high-density hybrid integration for micro-electromechanical system (MEMS) mirror chips with several thousand inputs/outputs has been developed. The integration scheme involving flip-chip assembly provides electrical signal to individual mirrors, which is compatible with postprocessing steps of selectively removing the silicon handle and releasing the MEMS mirrors. For the first time, to our knowledge, solder deposition and flip-chip bonding of 3-mum bumps on 5-mum centers of a large array has been demonstrated. 相似文献
10.
Xiaoji Ye Liu F.Y. Peng Li 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(8):913-926
Interconnects constitute a dominant source of circuit delay for modern chip designs. The variations of critical dimensions in modern VLSI technologies lead to variability in interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. In this paper, a practical interconnect delay and slew analysis technique is presented to facilitate efficient evaluation of wire performance variability. By harnessing a collection of computationally efficient procedures and closed-form formulas, process variations are directly mapped into the variability of the output delay and slew. An efficient method based on sensitivity analysis is implemented to calculate driving point models under variations for gate-level timing analysis. The proposed adjoint technique not only provides statistical performance variations of the interconnect network under analysis, but also produces delay and slew expressions parameterized in the underlying process variations in a quadratic parametric form. As such, it can be harnessed to enable statistical timing analysis while considering important statistical correlations. Our experimental results have indicated that the presented analysis is accurate regardless of location of sink nodes and it is also robust over a wide range of process variations. 相似文献
11.
Agarwal V. Jin Sun Wang J.M. 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2009,56(4):295-299
Traditional timing-variation reduction techniques are only able to decrease gate delay variation by incurring a delay overhead. In this brief, we propose a novel and effective splitting-based variation reduction technique for gates. We developed a new tool called Timing Uncertainty Reduction by Gate Splitting (TURGS), which reduces the timing variations of a circuit and presents little delay overhead at the primary output. Our experimental results show that TURGS achieves up to 20% improvement in timing variation for gates. 相似文献
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Manohararajah V. Chiu G.R. Singh D.P. Brown S.D. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(8):895-903
This paper studies the prediction of interconnect delay in an industrial setting. Industrial circuits and two industrial field-programmable gate-array (FPGA) architectures were used in this paper. We show that there is a large amount of inherent randomness in a state-of-the-art FPGA placement algorithm. Thus, it is impossible to predict interconnect delay with a high degree of accuracy. Furthermore, we show that a simple timing model can be used to predict some aspects of interconnect timing with just as much accuracy as predictions obtained by running the placement tool itself. Using this simple timing model in a two-phase timing driven physical synthesis flow can both improve quality of results and decrease runtime. Next, we present a metric for predicting the accuracy of our interconnect delay model and show how this metric can be used to reduce the runtime of a timing driven physical synthesis flow. Finally, we examine the benefits of using the simple timing model in a timing driven physical synthesis flow, and attempt to establish an upper bound on these possible gains, given the difficulty of interconnect delay prediction. 相似文献
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光纤延迟线对宽带成像雷达的转发式干扰 总被引:1,自引:0,他引:1
提出利用光纤延迟线对宽带成像雷达进行转发式干扰的方法,论述光纤延迟线的结构和原理,以及宽带成像雷达的工作原理,并对宽带成像雷达转发式干扰进行仿真。通过分析得到,利用光纤延迟线对雷达信号进行延时和移频,可以有效地对宽带成像雷达进行干扰。 相似文献
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Optimal Voltage Scaling, Repeater Insertion, and Wire Sizing for Wave-Pipelined Global Interconnects
Deodhar V.V. Davis J.A. 《IEEE transactions on circuits and systems. I, Regular papers》2008,55(4):1023-1030
The simultaneous application of voltage scaling, repeater insertion, and wire sizing is proposed in this paper to achieve high performance, low power, and low area on wave-pipelined interconnect circuits. Based on this methodology, design optimizations for three different types of applications are performed and different design metrics are used to obtain the optimal values of supply voltage, number of repeaters, and interconnect dimensions for these applications. The optimal supply voltage for low-power applications is shown to be twice the threshold voltage. In addition, an optimal throughput-per-energy-area (TPEA) design is compared with low-voltage differential signaling (LVDS). The optimal TPEA design is shown to reduce dynamic power by 10% and wire area by 70% compared to LVDS, without any loss of throughput performance. 相似文献
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This paper introduces an interconnect delay fault test (IDFT) controller on boards and system‐on‐chips (SoCs) with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be simultaneously tested with our technique. The proposed IDFT technique does not require any modification on boundary scan cells. Instead, a small number of logic gates needs to be plugged around the test access port controller. The IDFT controller is compatible with the IEEE 1149.1 and IEEE 1500 standards. The superiority of our approach is verified by implementation of the controller with benchmark SoCs with IEEE 1500 wrapped cores. 相似文献
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