n-Al0.15Ga0.85 N/p-6H–SiC heterostructure and based bipolar transistor

Heterojunction bipolar transistor (HBTs) based on Al0.15Ga0.85 N/6H–SiC heterojunction was fabricated. Room-temperature current–voltage (I–V) characteristics of n-Al0.15Ga0.85 N/p-6H–SiC emitter–base heterojunction exhibited good rectifying behavior with a forward current 5 × 10⁻² A and reverse current 3 × 10⁻⁹ A at 10 V and −10 V, respectively. Analysis of the temperature dependent I–V characteristics of this heterojunction revealed a barrier height of 1.1 eV. The fabricated n-Al0.15Ga0.85 N/p-SiC/n-SiC bipolar transistor did not exhibit common-emitter operation, however, common-base operation was observed with current gain β = IC/IB ranging in 75–100.     

An investigation of electrical and structural properties of Ni-germanosilicided Schottky diode

Ni-germanosilicided Schottky barrier diode has been fabricated by annealing the deposited Ni film on strained-Si and characterized electrically in the temperature range of 125 K–300 K. The chemical phases and morphology of the germanosilicided films were studied by using scanning electron microscopy (SEM), cross-sectional transmission electron microscopy (TEM) and energy dispersive spectroscopy (EDS). The Schottky barrier height (_b), ideality factor (n) and interface state density (D_it) have been determined from the current–voltage (I–V) and capacitance–voltage (C–V) characteristics. The current–voltage characteristics have also been simulated using SEMICAD device simulator to model the Schottky junction. An interfacial layer and a series resistance were included in the diode model to achieve a better agreement with the experimental data. It has been found that the barrier height values extracted from the I–V and C–V characteristics are different, indicating the existence of an in-homogeneous Schottky interface. Results are also compared with bulk-Si Schottky diode processed in the same run. The variation of electrical properties between the strained- and bulk-Si Schottky diodes has been attributed to the presence of out-diffused Ge at the interface.     

Electrical characterization of the hafnium oxide prepared by direct sputtering of Hf in oxygen with rapid thermal annealing

Electrical characterization of the hafnium oxide (HfO₂) gate dielectric films prepared by Hf sputtering in oxygen was conducted. By measuring the current–voltage (I–V) characteristics at temperature ranging from 300 to 500 K, several abnormalities in the I–V characteristics are recorded. For temperatures below 400 K, the current–voltage characteristics in high field region can be plotted with the Fowler–Nordheim law but a stronger temperature dependence was observed. Large flatband voltage shifts in the Al/HfO₂/Si capacitor were observed. The capacitance–voltage characteristics and flatband shifts are found to depend strongly on the post-deposition annealing temperature and duration. To study the reliability against high electric field, constant voltage stressing on the samples was conducted. We found that the trap energy levels are shallow and the oxide traps can be readily filled and detrapped at a low bias voltage.     

A detailed study of current–voltage characteristics in Au/SiO2/n-GaAs in wide temperature range

The forward and reverse-bias current–voltage (I–V) characteristics of Au/SiO₂/n-GaAs (MIS) type Schottky barrier diode (SBDs) have been investigated in the wide temperature range of 80–400 K. The zero-bias barrier height (_Bo) and ideality factor (n) assuming the thermionic emission (TE) mechanism show strong temperature dependence. While n decreases, _Bo increases with increasing temperature. Such temperature dependence of _Bo is an obvious disagreement with the reported negative temperature coefficient (α_temp) of barrier height. Therefore, we have reported a modification which includes the n and electron-tunneling parameter (αχ^1/2δ) in the expression of reverse-saturation current (I₀). After this modification, the value of α_temp obtained as −4 × 10⁻⁴ eV/K which is very close to α_temp of GaAs band-gap (−5.4 × 10⁻⁴ eV/K). Richardson plot of the ln(I₀/T²) versus 1/T has two linear region; the first region is (200–400 K) and the second region (80–150 K). The values of the activation energy (E_a) and Richardson constant were obtained from this plot and the values of E_a and Richardson constants (A^*) are much lower than the known values. These behaviors of the Au/SiO₂/n-GaAs (MIS) type (SBDs) have been interpreted by the assumption of a double-Gaussian distribution of barrier heights (BHs) at the metal–semiconductor interface giving a mean BHs () of 1.20 and 0.68 eV and standard deviation (σ_s) of 0.1503 and 0.0755 V, respectively. Thus the modified ln versus q/kT for two different temperature ranges (200–400 K and 80–150 K) plot then gives mean barrier heights and A^*, 1.18 and 0.66 eV and 7.08 and 3.81 A/cm² K², respectively. This value of the A^* 7.08 A/cm² K² is very close to the theoretical value of 8.16 A/cm² K² for n-type GaAs. Hence, all these behaviours of the forward-bias I–V characteristics of the Au/SiO₂/n-GaAs (MIS) type SBDs can be successfully explained on the basis of a TE mechanism with a double-Gaussian distribution of the BHs.     

Nanoscale electrical characterization of ultrathin high-k dielectric MOS stacks: A conducting AFM study

Extreme scaling in both silicon and alternative channel CMOS has highlighted the importance of localized characterization on the nanometer scale. We have used a conductive-contact atomic force microscopy (C-AFM) technique in ultra high vacuum (UHV) conditions to analyze and compare intrinsic stack degradation mechanisms leading to breakdown (BD) for ultrathin high-k dielectric films of (4 nm) Hf_xSiO_y/SiO₂ on Si and (2 nm) ZrO₂/GeO₂ on Ge. Simultaneous nanoscale current–voltage I–V characteristics, topography, tunneling current and relative tip–surface contact interactions as normal and lateral force maps revealed localized injected charge dependence on electrical stress. It is shown that the charge can propagate laterally. Successive voltage scanning is related to the overall post-BD conductivity for pre- to post-BD degradation propagation. In contrast with SiO₂ interface, an increased GeO₂ interlayer reactivity yielding more active interface defects is suggested.     

Reliability characteristics of high-k dielectrics

In this paper, recent results of Weibull slopes, area scaling factors, and breakdown behaviors observed for both soft breakdown and hard breakdown are discussed. These results would help to shed light on the breakdown mechanism of HfO₂ gate dielectrics. The Weibull slope β of the hard breakdown for both the area dependence and the time-to-dielectric-breakdown distribution was found to be β=2, whereas that of the soft breakdown was about 1.4 (EOT=14 Å). We also integrated the time-to-breakdown characteristics of HfO₂ under unipolar AC voltage stress on MOS capacitors. The results show that longer lifetime of HfO₂ has been observed when compared to constant voltage stress. Higher frequency and lower duty cycle in the AC stress resulted in longer lifetime. As thickness decreases, the amount of lifetime enhancement decreases. The enhancement of unipolar t_BD is attributed to less charge trapping during the “on time”, t_on and charge detrapping during the off time, t_off. It is proposed that time (τ_in) for charge to be trapped in HfO₂ is longer than t_on of unipolar stress under high frequency. In addition to experimental results, possible solutions are discussed.     

Determination of the electronic parameters of nanostructure SnO2/p-Si diode

The current–voltage and capacitance–voltage characteristics of the nanostructure SnO₂/p-Si diode have been investigated. The optical band gap and microstructure properties of the SnO₂ film were analyzed by optical absorption method and scanning electron microscopy, respectively. The optical band of the film was found to be 3.58 eV with a direct optical transition. The scanning electron microcopy results show that the SnO₂ film has the nanostructure. The ideality factor, barrier height and series resistance values of the nanostructure SnO₂/p-Si diode were found to be 2.1, 0.87 eV and 36.35 kΩ, respectively. The barrier height obtained from C–V measurement is higher than obtained from I–V measurement and this discrepancy can be explained by introducing a spatial distribution of barrier heights due to barrier height inhomogeneities, which are available at the nanostructure SnO₂/p-Si interface. The interface state density of the diode was determined by conductance technique and was found to be 8.41 × 10¹⁰ eV⁻¹ cm⁻².It is evaluated that the nanostructure of the SnO₂ film has an important effect on the ideality factor, barrier height and interface state density parameters of SnO₂/p-Si diode.     

Extraction of interface states at emitter–base heterojunctions in AlGaAs/GaAs heterostructure bipolar transistors using sub-bandgap photonic excitation

Distribution of interface states at the emitter–base heterojunctions in heterostructure bipolar transistors (HBTs) is characterized by using current–voltage characteristics using sub-bandgap photonic excitation. Sub-bandgap photonic source with a photon energy E_ph which is less than the energy bandgap E_g (E_g,GaAs = 1.42, E_g,AlGaAs = 1.76 eV) of emitter, base, and collector of HBTs, is employed for exclusive excitation of carriers only from the interface states in the photo-responsive energy range at emitter–base heterointerface. The proposed method is applied to an Al_0.3Ga_0.7As/GaAs HBT (A_E = W_E × L_E = 250 × 100 μm²) with E_ph = 0.943 eV and P_opt = 3 mW. Extracted interface trap density D_it was observed to be D_it,max  4.2 × 10¹² eV⁻¹ cm⁻² at emitter–base heterointerface.     

Influence of the manufacturing process on the electrical properties of thin (<4 nm) Hafnium based high-k stacks observed with CAFM

In this work, the dependence of the electrical characteristics of some thin (<4 nm) HfO₂, HfSiO and HfO₂/SiO₂ stacks on their manufacturing process is studied at the nanoscale. Topography, current maps and current–voltage (I–V) characteristics have been collected by conductive atomic force microscope (CAFM), which show that their conductivity depends on some manufacturing parameters. Increasing the annealing temperature, physical thickness or Hafnium content makes the structure less conductive.     

ZrAlO ternary oxide as a candidate for high-k dielectrics

ZrAlO thin films were prepared by the pyrosol process. Four different cases were considered taking as basis a solution of 0.025 M zirconium acetylacetonate (ZrAAc) and 5 at% of aluminum acetylacetonate (AlAAc) dissolved in pure methanol. Films of case A, were deposited with the mentioned solution and subjected to rapid thermal annealing (RTA). For case B, a small volume of water was added to start solution. Case C, were similar samples of case B, but with a post-deposition RTA. Case D, were Si/Al₂O₃/ZrAlO/Al stacks with post-deposition RTA, using water in the start solution. XPS profiles show that the relative chemical composition of deposited materials is affected by the volume of water added (Vw). The aluminum concentration in the films acquires values as high as or higher than zirconium concentration for increasing Vw. All the prepared samples were amorphous as indicated by the X-ray diffraction (XRD) spectra, even for large integration times. Current–voltage (I–V) and capacitance measurements were carried out in metal–insulator–metal (MIM) devices (Corning-glass/TCO/ZrAlO/Al) and I–V and simultaneous capacitance–voltage (C–V) measurements were performed in metal–oxide–semiconductor (MOS) devices (Si/ZrAlO/Al and Si/Al₂O₃/ZrAlO/Al). Leakage currents of the order of 10⁻⁴ A/cm², were typically obtained in MIM devices, whereas for some MOS devices, leakage currents of the order of 10⁻⁷ A/cm² were obtained. Dielectric constant (k) values of the order of 24 were calculated for MIM devices and k values ranging from 12.5 up to 17 were calculated for MOS devices.     

Probing stress effects in HfO2 gate stacks with time dependent measurements

Effects of constant voltage stress (CVS) on gate stacks consisting of an ALD HfO₂ dielectric with various interfacial layers were studied with time dependent sensing measurements: DC I–V, pulse I–V, and charge pumping (CP) at different frequencies. The process of injected electron trapping/de-trapping on pre-existing defects in the bulk of the high-κ film was found to constitute the major contribution to the time dependence of the threshold voltage (V_t) shift during stress. The trap generation observed with the low frequency CP measurements is suggested to occur within the interfacial oxide layer or the interfacial layer/high-κ interface, with only a minor effect on V_t.     

Evaluation of SiGe:C HBT intrinsic reliability using conventional and step stress methodologies

The reliability of SiGe:C HBT devices fabricated using the Freescale’s 0.35-μm RF-BICMOS process was evaluated using both conventional and step stress methodologies. This device technology was assessed to determine its capability for various power amplifier applications (e.g., WLAN, Bluetooth, and cellular phone), which are more demanding than conventional circuit designs. The step stress method was developed to allow a rapid evaluation of product reliability, as well as, a quick method to monitor product reliability. For all tests the collector current I_C and collector voltage V_C were kept constant throughout the test, and the current gain β (I_C/I_B) was continuously monitored. The nominal bias condition was V_C = 3.5-V and J_C = 50-kA/cm² (or 0.5-mA/μm²). The “failure criterion” for all reliability evaluations was −10% degradation in β from the initial value at the start of each stress test or interval. The median time to failure (MTTF) at a junction temperature (T_JCN) of 150 °C for the conventional stress test was 1.86E6-h, and the thermal activation energy was 1.33-eV. In contrast for the temperature step stress tests the combined results gave an MTTF at T_JCN = 150 °C of 5.2E6-h and a thermal activation energy of 1.44-eV. Considering the differences in the two test methods, these results are quite close to one another. The intrinsic reliability of this device at the nominal bias condition and T_JCN = 150 °C is more than adequate for a 5-year system life.     

Circuit implications of gate oxide breakdown

A model for the oxide breakdown (BD) current–voltage (I–V) characteristics has been experimentally verified on CMOS inverters. The implications of oxide BD on the performance of various CMOS circuit elements are discussed. Examples are shown of cell stability and bitline differentials in static memory (SRAM), signal timing, and inverter chains.     

High temperature characterization of high-κ dielectrics on SiC

We have fabricated thin catalytic metal–insulator–silicon carbide based structure with palladium (Pd) gates using TiO₂ as the dielectric. The temperature stability of the capacitor is of critical importance for use in the fabrication of electronics for deployment in extreme environments. We have evaluated the response to temperatures in excess of 450 °C in air and observed that the characteristics are stable. Results of high temperature characterization are presented here with extraction of interface state density up to 650 °C. The results show that at temperatures below 400 °C the capacitors are stable, with a density of interface traps of approximately 6×10¹¹ cm² eV⁻¹. Above this temperature the C–V and G–V characteristics show the influence of a second set of traps, with a density around 1×10¹³ cm² eV⁻¹, which is close to that observed for slow states near the conduction band edge. The study of breakdown field as a function of temperature shows two distinct regions, below 300 °C where the breakdown voltage has a strong temperature dependence and above 300, where it is weaker. We hypothesize that the oxide layer dominates the breakdown voltage at low temperature and the TiO₂ layer above 300 °C. These results at high temperatures confirms the suitability of the Pd/TiO₂/SiO₂/SiC capacitor structure for stable operation in high temperature environments.     

Electrical and structural properties of hafnium silicate thin films

Thin (4 nm) hafnium silicate (HfO₂)_x(SiO₂)_1−x/SiO₂ gate stacks (0 < x < 1) grown by metal organic chemical vapour deposition (MOCVD) are investigated in this study. The focus is on extracting the optical constants, and hence bandgaps as well as dielectric constants. The VUV (vacuum ultraviolet) spectroscopic ellipsometry (VUV-SE) technique in the spectral range 140–1700 nm, together with current–voltage and capacitance–voltage techniques were used for studying the optical and electrical properties of the layers, respectively. The bandgap was found to increase from 5.24 eV for HfO₂ to 6 eV for Hf-silicate with 30% Hf. The permittivity was reduced from 21 for HfO₂ layers to 8 for Hf-silicate with x = 0.3. The results suggest that the optimal Hf content is above 0.6, for which the permittivity higher than 10 can be achieved.     

Electrical measurements of voltage stressed Al2O3/GaAs MOSFET

Electrical characteristics of GaAs metal–oxide–semiconductor field effect transistor with atomic layer deposition deposited Al₂O₃ gate dielectric have been investigated. The IV characteristics were studied after various constant voltage stress (CVS) has been applied. A power law dependence of the gate leakage current (I_g) on the gate voltage (V_g) was found to fit the CVS data of the low positive V_g range. The percolation model well explains the degradation of I_g after a high positive V_g stress. A positive threshold voltage (V_th) shift for both +1.5 V and +2 V CVS was observed. Our data indicated that positive mobile charges may be first removed from the Al₂O₃ layer during the initial CVS, while the trapping of electrons by existing traps in the Al₂O₃ layer is responsible for the V_th shift during the subsequent CVS.     

Breakdown and reliability of p-MOS devices with stacked RPECVD oxide/nitride gate dielectric under constant voltage stress

In this work, the effects of voltage and temperature on the TDDB characteristics of 2.0 nm stacked oxide/nitride (O/N) dielectric, prepared by remote plasma enhanced CVD (RPECVD), has been investigated. The breakdown characteristics and time-to-breakdown (t_BD) are recorded from p⁺-poly/n-Si capacitors under constant voltage stress (CVS) at different temperatures. The t_BD cumulative distributions exhibit a single Weibull slope β of 1.9 for different applied voltages. The charge-to-breakdown (Q_BD) is integrated from the gate current as a function of stress times, and can be used to extract the defect generation rate. The activation energy of 0.39 eV is determined from the Arrhenius law, and the average temperature acceleration factor is about 45 between 25 and 125 °C for a constant gate voltage. The extrapolation of the TDDB lifetime with low percentile failure rate of 0.01% provides a 10-year projection for a total gate area of 0.1 cm² on a chip at 125 °C with the Poisson area-scaling law and a constant voltage acceleration factor of 14.83 V⁻¹. It is projected that the maximum safe operating voltage is 1.9 V for 2.07 nm O/N gate dielectric.     

Characterization by Internal Photoemission Spectroscopy of Single-Crystal CVD Diamond Schottky Barrier Diodes

Internal photoemission spectroscopy measurements have been performed to study the electrical characteristics of Schottky diodes on boron-doped single-crystalline chemical vapor deposited (SC-CVD) diamond. These measurements were compared with current–voltage (I–V) and current–temperature (I–T) measurements. Schottky contact barrier heights and ideality factors have been measured on Schottky contacts formed on four samples with Au, Ni, and Al contact metallizations. I–V and I–T measurements were performed in the temperature range from 300 K to 500 K. The internal photoemission method, which is less influenced by local variations in the Schottky barrier height than the other two methods, yielded the highest values of Schottky barrier heights to p-type material: Φ_B = 1.78 eV to 2.10 eV, depending on the choice of contact metal and sample boron concentration.     

Effect of annealing on the properties of low-k nanoporous SiO2 films prepared by sol–gel method with catalyst HF

Using hydrofluoric acid (HF) as catalyst, nanoporous SiO₂ thin film was synthesized by sol–gel method. By scanning electron microscopy, Fourier transform infrared spectra, thermo gravimetric and differential thermal analysis, ellipsometry, capacitance–voltage and current–voltage measurements, the effects of annealing on film properties were discussed in detail. The introduction of HF results in the less polarizability, the preferable microstructures and the improved thermal stability of the nanoporous silica films. After thermal annealing at 450 °C, the crack-free films with strong hydrophobicity, ultra-low dielectric constant of 1.65, porosity of 78%, and leakage current density of 1.3 × 10⁻⁸ A cm⁻² were obtained.