Using a Genetic Algorithm to Optimize Capacitance Ratio Approximations in SC Filters

Accurate capacitance matching is one of the main design issues in switched-capacitor (SC) filters. Using identical unit capacitors in parallel to implement each filter capacitor, combined with a careful layout design, can provide an accuracy of 0.1% in the filter coefficients. The disadvantage of this technique is the fact that it can be directly applied only if the coefficients can be expressed as ratios of integer numbers. As a result, coefficient approximations are required, leading to frequency response errors. In this paper, a genetic algorithm (GA) is used to find the optimum capacitance ratio approximations by rational numbers that minimize the total number of unit capacitors for a given error tolerance in the frequency response. Design examples in 0.35 μm CMOS are presented and simulated to illustrate the proposed approach and verify its effectiveness.     

High-speed single-channel SAR ADC with a novel control logic in 65 nm CMOS

This paper presents an 8-bit 320 MS/s single-channel successive approximation register (SAR) analog-to-digital converter (ADC) with low power consumption. Through a procedure of splitting all the most significant bit (MSB) capacitors except the least significant bit (LSB) capacitor into two equal sub-capacitors and reusing the terminal capacitor, the average switching energy and total capacitance can be reduced by about 87 and 50% respectively compared to the conventional procedure. Meanwhile, high-speed operation can be achieved by using a novel SAR control logic featuring efficient hardware cost and small critical path delay. In addition, this paper analyzes how to obtain the value of the unit capacitance which exhibits trade-offs between conversion rate, power consumption and linearity performance. The SAR ADC is simulated in 65 nm CMOS technology. It can achieve 48.63 dB SNDR, 63.61 dB SFDR at a supply voltage of 1.2 V and sampling frequency of 320 MS/s for near-Nyquist input, consuming 2.59 mW of power and with a FoM of 37 fJ/conversion-step.     

具有混合反馈的高Q和/或高fs开关电容带通滤波器

本文提出了一种减少电容分布和总电容的高Q和/或高f_s开关电容(SC)带通滤波器。在传统的双二次SC滤波器结构中,引入部分正反馈并改变前馈网络可使总电容和电容分布得到大幅度的减少。举例说明了二阶高Q(=50)SC带通滤波器设计,并比较了不同滤波器结构的性能参数。     

电容的分数阶等效电路建模与分析

实际的电容器件都是非理想的,其特性受到各种因素的影响,建立精确的电容模型对于电路系统分析与设计十分必要。考虑到电容的分数阶微积分特性,文中基于传统的电容整数阶等效电路模型,提出电容的分数阶等效电路模型,并采用差分进化算法辨识出模型参数,然后将该模型应用于Buck电路进行纹波电压的分析。仿真结果表明,同传统整数阶等效电路模型相比,分数阶等效电路模型拟合电容实际数据的准确度更高,验证了该电容分数阶等效电路模型的有效性。     

Design and analysis of high speed capacitive pipeline DACs

Design of a high speed capacitive digital-to-analog converter (SC DAC) is presented for 65 nm CMOS technology. SC pipeline architecture is used followed by an output driver. For GHz frequency operation with output voltage swing suitable for wireless applications (300 mV_pp) the DAC performance is shown to be limited by the clock feed-through and settling effects in the SC array rather than by the capacitor mismatch or kT/C noise, which appear negligible in this application. While it is possible to design a highly linear output driver with HD3 < ?70 dB and HD2 < ?90 dB over 0.5–5 GHz band as we show, the maximum SFDR of the SC DAC is 45 dB with 8-bit resolution and Nyquist sampling of 3 GHz. The capacitor array is designed based on the DAC design area defined in terms of the switch size and unit capacitance value. A tradeoff between the DAC bandwidth and resolution accompanied by SFDR is demonstrated. High linearity of the output driver is attained by a combination of two techniques, the derivative superposition (DS) and resistive source degeneration. In simulations the complete DAC achieves SFDR of 45 dB with 8-bit resolution for signal bandwidth 1.36 GHz with Nyquist sampling. With 6-bit and 5.5 GHz bandwidth 33 dB SFDR is attained. The total power consumption of the SC DAC is 90 mW with 1.2 V supply and clock frequency of 3 GHz.     

A two-stage monolithic IF amplifier utilizing a Ta2O5capacitor

A two-stage monolithic IF amplifier incorporating a sputtered Ta2O5capacitor has been fabricated. The monolithic capacitor is based on a composite layer structure consisting of Au, Ta, Ta2O5, Ta, and Au. This layered structure is sequentially deposited in a single sputtering run, which eliminates particulate contamination. As a result, a thin pinhole-free dielectric layer can be deposited over large areas, and 140-pF capacitors have been fabricated with excellent yields. The large unit area capacitance of 1500 pF/mm²available with the present process has the potential for reducing the size of matching and bias circuits in microwave monolithic circuits and hybrid thin-film circuits. The monolithic amplifiers exhibit a gain of 17.5 ± 1.0 dB from 1.2 to 2.6 GHz and a minimum noise figure of ∼ 2.7 dB, with an associated gain of 17.5 dB at 1.7 GHz.     

A 900 MHz low power LC-VCO with improved phase noise performance

In this paper, we present the design and development of a low-power LC-VCO with improved phase noise performance by implementing a new capacitor divider varactor configuration and a 2nd order notch filter. We propose a new time-weighted approach to model the effective capacitance experienced by the oscillating signal over the oscillation period. The modeled effective capacitance is used in the calculation of the oscillation frequency, which agrees well with the simulation results. Two VCOs are designed and fabricated in TSMC 0.18 μm technology. The oscillation frequency is tunable from 759 to 910 MHz with a tuning range of 18%. At 900 MHz carrier, the measured phase noise is ?126.1 dBc/Hz at 1 MHz frequency offset with 4.5 mW power consumption.     

A CMOS micro power switched-capacitor DC–DC step-up converter for indoor light energy harvesting applications

This paper presents a micro power light energy harvesting system for indoor environments. Light energy is collected by amorphous silicon photovoltaic (a-Si:H PV) cells, processed by a switched capacitor (SC) voltage doubler circuit with maximum power point tracking (MPPT), and finally stored in a large capacitor. The MPPT fractional open circuit voltage (V_OC) technique is implemented by an asynchronous state machine (ASM) that creates and dynamically adjusts the clock frequency of the step-up SC circuit, matching the input impedance of the SC circuit to the maximum power point condition of the PV cells. The ASM has a separate local power supply to make it robust against load variations. In order to reduce the area occupied by the SC circuit, while maintaining an acceptable efficiency value, the SC circuit uses MOSFET capacitors with a charge sharing scheme for the bottom plate parasitic capacitors. The circuit occupies an area of 0.31 mm² in a 130 nm CMOS technology. The system was designed in order to work under realistic indoor light intensities. Experimental results show that the proposed system, using PV cells with an area of 14 cm², is capable of starting-up from a 0 V condition, with an irradiance of only 0.32 W/m². After starting-up, the system requires an irradiance of only 0.18 W/m² (18 μW/cm²) to remain operating. The ASM circuit can operate correctly using a local power supply voltage of 453 mV, dissipating only 0.085 μW. These values are, to the best of the authors’ knowledge, the lowest reported in the literature. The maximum efficiency of the SC converter is 70.3 % for an input power of 48 μW, which is comparable with reported values from circuits operating at similar power levels.     

电力电子变换器中滤波电容参数设计方法

在电力电子变换器中,滤波电容可以抑制电压脉动,消除谐波,其参数大小对变换器的性能有着重要影响。本文首先分析滤波电容器的特性,得出影响电容器滤波效果的各个因素,然后介绍了几种常用的滤波电容器参数设计方法,最后通过一个全桥变换器进行了仿真验证,有助于学生更好地掌握滤波电容器的参数设计。     

Experimental implementation of a 14 bit 80 kSPS non-binary cyclic ADC

This paper presents a prototype of 14 bit 80 kSPS non-binary cyclic ADC without high accuracy analog components and complicated digital calibration. Since the redundancy of non-binary ADC tolerates the non-idealities of analog components such as capacitor mismatch and finite amplifier DC gain, the design consideration of this high accuracy ADC can be only focused on the capacitance of sampling capacitor to satisfy the overall kT/C noise target, the drivability and linearity of amplifier without any high accuracy analog components. The proposed proof-of-concept cyclic ADC has been designed and fabricated in TSMC 90 nm CMOS technology. Measured SNDR = 81.9 dB is achieved at Fs = 80 kSPS with a simple radix-value estimation technique. No other complicated digital calibration is used to compensate the non-linearity of ADC caused by MOM capacitors and a poor gain of the amplifier as low as 66 dB. Measured DNL is ? 0.6/+ 0.67 LSB and INL is ? 1.2/+ 1.6 LSB. Prototype ADC dissipates 8mW at supply voltage is 3.3 V in analog circuits.     

A 6.7-fF//spl mu/m/sup 2/ bias-independent gate capacitor (BIGCAP) with digital CMOS process and its application to the loop filter of a differential PLL

A linear bias-independent gate capacitor (BIGCAP) with large intrinsic capacitance and low parasitic capacitance is proposed. BIGCAP is composed of a pair of accumulation-mode n-poly gate capacitors in an n-well and a pair of pMOS gate capacitors, which requires no additional fabrication process steps. Measured results with 1.5-V 0.13-/spl mu/m digital CMOS technology show that the intrinsic capacitance is 6.7 fF//spl mu/m/sup 2/ (6.7 times bigger than that of typical MIM capacitors) and the parasitic capacitance is 1.9% of the intrinsic capacitance (1/5 that of typical MIM capacitors). The linearity is /spl plusmn/2.9% and capacitance variation across a wafer is as small as /spl sigma/= 0.096%. For a 0.1-V threshold voltage variation, the capacitance variation was only /spl sigma/= 0.69% and the linearity ranged from /spl plusmn/2.84% to /spl plusmn/2.93%. For three types of BIGCAP using 1.5-V, 2.5-V, and 3.3-V MOSFETs, less than /spl plusmn/4% linearity is achievable by optimizing the ratio (x) of the pMOS gate capacitors' area to the area of the n-poly gate capacitors, and the optimum x value is within a range of 15%-25%. BIGCAP has been applied to the loop filter of a differential phase-locked loop (PLL) and reduces the gate area of the largest loop filter capacitor to only 35% of that of the conventional design while achieving reasonable jitter of 7.0 ps (rms) and 74.4 ps (peak-to-peak) at 840 MHz with a 1.5-V supply.     

A high performance MIM capacitor using HfO2 dielectrics

Metal-insulator-metal (MIM) capacitors with a 56 nm thick HfO₂ high-κ dielectric film have been fabricated and demonstrated for the first of time with a low thermal budget (~200°C). Voltage linearity, temperature coefficients of capacitance, and electrical properties are all characterized. The results show that the HfO₂ MIM capacitor can provide a higher capacitance density than Si₃N₄ MIM capacitor while still maintaining comparable voltage and temperature coefficients of capacitance. In addition, a low leakage current of 2×10^-9 A/cm² at 3 V is achieved. All of these make the HfO ₂ MIM capacitor to be very suitable for use in silicon RF and mixed signal IC applications     

A 12-bit 250 MS/s pipeline ADC with 78 dB SFDR in 0.13-µm CMOS

A 12-bit 250 MS/s pipeline ADC is presented and implemented in 0.13 µm CMOS process. To reduce the load capacitance of each pipeline stage and save area, the inter-metal capacitors are adopted as input sampling capacitors of the comparators. A fully integrated reference buffer associated with a simulation scheme is proposed to improve the settling speed and PSRR of the differential reference voltage. To reduce the overall power a low cost foreground calibration for capacitor mismatches is employed. The single-stage telescopic with gain-boosting amplifiers and an improved bias is applied in each stage due to its high power efficiency. Additionally, the timing in the sampling phase is optimised to achieve high sampling linearity. Even harmonics induced by parasitic capacitance are analysed profoundly and mitigated at the level of layout. The measured SNDR and SFDR are 63 and 78 dB with 38.1 MHz input, respectively, and remain 63 and 77 dB with Nyquist input. The ADC core area is 1.6 mm² and consumes 165 mW (reference buffer included, LVDS excluded) at 250 MS/s under 1.3 V.     

Analysis and performance of a light-sensitive capacitor

A comprehensive study has been made of a duo-dielectric capacitor in which one of the dielectrics is photoconducting and the other inert. Under dark conditions, device capacitance per unit area is set by the respective dielectric coefficients, conductivities, and thicknesses. Illumination causes device capacitance to change, and decreases the interfacial polarization relaxation time. Analysis reveals the means to optimize device performance, and the existence of a light-dark capacitance ratio-cutoff frequency limitation. A fabricated unit, utilizing CdS with BaTiO3, exhibited a capacitance change of 2500 times and a frequency span extending to 0.22 Mc/s. A CdS:silicone plastic unit showed a maximum capacitance change of 20 times and a frequency span of ∼10 Mc/s, but had degraded dark performance attributed to electron traps, and an interesting piezo-electric resonance that affected both capacitance and dissipation factor at 0.315 Mc/s. Applications of this type of a light-sensitive capacitor are limited to specialized situations where a maximizing dissipation factor and a varying frequency bandwidth can be tolerated.     

Capacity limits and matching properties of integrated capacitors

Theoretical limits for the capacitance density of integrated capacitors with combined lateral and vertical field components are derived. These limits are used to investigate the efficiency of various capacitive structures such as lateral flux and quasifractal capacitors. This study leads to two new capacitor structures with high lateral-field efficiencies. These new capacitors demonstrate larger capacities, superior matching properties, tighter tolerances, and higher self-resonance frequencies than the standard horizontal parallel plate and previously reported lateral-field capacitors, while maintaining comparable quality factors. These superior qualities are verified by simulation and experimental results     

A compact and high performance dual-band bandpass filter based on unbalanced composite right/left-handed transmission lines for WLANs applications

In this paper, a novel compact microstrip dual-band (DB) bandpass filter with high selectivity for wireless local area networks applications is proposed. The design procedure is based on unbalanced composite right/left-handed (UCRLH) transmission lines (TLs). The DB features can be achieved by unbalancing the CRLH transmission line. The necessary conditions to obtain a discontinuous transition between the left- and right-handed bands, intended to provide UCRLLH TL, are investigated. The application of this technique to design of compact DB filters is illustrated. The structure of the proposed DB filter is implemented by a series interdigital capacitor located between two microstrip lines that shorted to the ground plane by vias. The vias with microstrip lines acting as a shunt connected inductor while the series capacitor is realized by interdigital capacitor. The design procedure based on a simple equivalent circuit is also introduced. The proposed filter has advantages such as compact size, easy fabrication, high selectivity, low insertion loss, high return loss and, design flexibility. To validate the proposed technique, the proposed DB filter has been fabricated and tested. Good agreement has been found between simulation and measurement results. The total size of the proposed UCRLH DB filter is 0.17 λ_g × 0.048 λ_g, where λ_g is the guided wavelength of the lower pass-band. The size of the proposed DB filter is more compact in comparison with known similar filters.     

适合集成开关电容DC-DC变换器的浮地电容倍增器

针对在集成电路中制作大容量电容器的困难，提出了一种利用电流传输器提高集成电容器容量的方法，称之为连续可变浮地电容倍增器。分析了电容倍增的机理，建立了相应的关系式，在此基础上对用此浮地电容构成的一阶滤波器和开关电容DC-DC变换器进行了理论分析和PSPICE仿真。结果表明，利用电流传输器的阻抗变换作用，可使小容量的电容等效变换为较大容量的浮地电容，从而便于开关电容DC-DC变换器实现全单片集成。     

Une méthode d’optimisation discrète pour les filtres cascade à capacités commutées

A discrete optimization method using a noninteraction property between the different sections of cascade switched-capacitor filter is described. The optimization, realized with a reduced set of intermediate parameters caracterizing each section, yields to a non minimum capacitive area structure, but which has very accurate capacitor ratios and which could be realized with minimum unit capacitors. This method may be applied to switched-current filters (aspect ratios of transistor discretization). An eighth order band-pass Cauer filter and a fifth order low-pass Cauer filter show the effectiveness of this method.     

Fractal capacitors

A linear capacitor structure using fractal geometries is described. This capacitor exploits both lateral and vertical electric fields to increase the capacitance per unit area. Compared to standard parallel-plate capacitors, the parasitic bottom-plate capacitance is reduced. Unlike conventional metal-to-metal capacitors, the capacitance density increases with technology scaling. A classic fractal structure is implemented with 0.6-μm metal spacing, and a factor of 2.3 increase in the capacitance per unit area is observed. It is shown that capacitance boost factors in excess of ten may be possible as technology continues to scale. A computer-aided-design tool to automatically generate and analyze custom fractal layouts has been developed     

Series/Parallel Time-Multiplexed Switched-Capacitor Filters with Programmability Based on Non-Uniform Sampling

This paper presents an improved scheme for programmable time-multiplexed (TM) switched-capacitor (SC) filters. The proposed approach uses a novel sampling technique, which eliminates the need for resolution/area tradeoffs. The programmability of each processing channel is based on the use of non-uniform clock signals with noise-shaped sampling energy. No capacitor values are modified for programming frequency response parameters and, hence, the performance of the TM SC filter is not sacrificed for programmability. Such a sampling technique not only leads to an accurate frequency response control, but also allows the design procedures and the resulting SC circuit implementation to be simplified. A test-chip including a programmable second-order TM SC filter with a multiplexing order of four, which operates in series or in parallel mode, was fabricated in conventional CMOS technology. Measurement results demonstrate the effectiveness and versatility of the proposed technique.