High performance analog VLSI computational circuits

Simple linear voltage/current-controlled voltage-to-current (V-T) converters, which are to first-order insensitive to the threshold voltage variation, are introduced. The circuits can be used as basic building blocks to construct simple analog computational circuits, which can perform functions such as square rooting, squaring, multiplication, sum of squares, difference of squares, etc. Some of the key features are: good linearity, floating inputs [high common-mode rejection ratio (CMRR)], simplicity, and good transconductance tuning range. The circuits can be realized with CMOS devices in saturation, however, BiCMOS devices extend their speed and input voltage range. Realistic simulations and experimental results clearly demonstrate the claims     

Design and applications of tunable analog BiCMOS circuits

Discusses the design, merits, and applications of tunable BiCMOS circuits. Although the BiCMOS technology offers higher design flexibility due to the presence of more types of active devices than the standard CMOS or bipolar technologies, it is also costlier. Hence, its use can be justified only if the salient features of BiCMOS are taken advantage of adequately. The analysis discusses one possible approach that cannot be easily and economically duplicated in other technologies.<>     

Design principles for low-voltage low-power analog integrated circuits

In this paper it is argued that there are good reasons to choose current as the information-carrying quantity in the case of low-voltage low-power design constraints. This paper focuses on the influence of the transfer quality on that choice. To obtain power-efficient transfer quality, indirect feedback is shown to be a good alternative to traditional feedback techniques.     

单电源模拟设计技术及虚地发生器的应用

对单电源模拟电路设计中的核心部件单纯源放大器进行了分析并提出几点应注意的问题;介绍了TI公司的虚地发生器（TLE2425/2426）在单电源模拟电路设计中的应用,并与一般的电压参考进行了比较。     

On the generalization of composite memristive network structures for computational analog/digital circuits and systems

The unique adaptive properties of memory resistors (memristors) are ideal for use in computational architectures. Multiple interconnected memristors demonstrate complicated overall behavior which significantly improves the efficiency of logic operations via massive parallelism. Nowadays, within an ever-growing variety of memristive systems, most of the research has so far focused on the properties of the individual devices; little is known about the extraordinary features of complex memristive networks and their application prospects. The composite characteristics of regular and irregular memristive networks are explored in this work. A generalized concept for the construction of composite memristive systems, efficiently built out of individual memristive devices, is presented. A new type of threshold-dependent programmable memristive switches, presenting different electrical characteristics from their structural elements, is proposed. As an example of the introduced approach, a SPICE simulation-based evaluation of several programmable analog circuits is presented. The proposed circuit design approach constitutes a step forward towards novel memristor-based nanoelectronic computational systems and architectures.     

Pulse-modulated analog neuron circuits

Analog neuron circuits based on both frequency modulation and pulse modulation are investigated. The circuits are compared in terms of size, power, performance, and reliability; frequency modulation shows advantages in each area. Test circuits were designed and fabricated in 2μm CMOS technology. The frequency modulated neuron has an operational frequency of 3.125 MHz and a dynamic range of 17 bits. Our results indicate that this circuit technique may provide substantial advantages in high-performance, low-power neural systems.     

Design of voltage-mode and current-mode computational circuits using floating-gate MOS transistors

In this paper, we present voltage-mode and current-mode computational circuits using floating-gate MOS (FGMOS) transistors, operating in saturation region. The circuits are designed using two FGMOS basic-cells, each one formed by three floating-gate transistors with common source. The first basic cell is connected in voltage mode, while the second one is connected in current-mode configuration in order to implement voltage and current-mode circuits, respectively. Using the basic FGMOS cells, voltage and current squarers, four-quadrant multipliers and a current square rooter are designed. Mismatches and distortion analysis for the proposed circuits have been elaborated. The most important advantages are, rail-to-rail dynamic input range, low distortion and ability for either differential or single-ended input signals. Simulation results demonstrate the feasibility and the accuracy of the circuits.     

Pulse-modulated analog neuron circuits

Analog neuron circuits based on both frequency modulation and pulse modulation are investigated. The circuits are compared in terms of size, power, performance, and reliability; frequency modulation shows advantages in each area. Test circuits were designed and fabricated in 2µm CMOS technology. The frequency modulated neuron has an operational frequency of 3.125 MHz and a dynamic range of 17 bits. Our results indicate that this circuit technique may provide substantial advantages in high-performance, low-power neural systems.     

CMOS异或电路的设计与应用

设计了四种CMOS"异或"单元电路,通过模拟仿真分析了它们各自的性能特点,并讨论了它们在奇偶检测电路、微处理器系统加法器电路以及单片机全加电路等设计中的不同应用.     

Fault diagnosis of analog circuits

In this paper, various fault location techniques in analog networks are described and compared. The emphasis is on the more recent developments in the subject. Four main approaches for fault location are addressed, examined, and illustrated using simple network examples. In particular, we consider the fault dictionary approach, the parameter identification approach, the fault verification approach, and the approximation approach. Theory and algorithms that are associated with these approaches are reviewed and problems of their practical application are identified. Associated with the fault dictionary approach we consider fault dictionary construction techniques, methods of optimum measurement selection, different fault isolation criteria, and efficient fault simulation techniques. Parameter identification techniques that either utilize linear or nonlinear systems of equations to identify all network elements are examined very thoroughly. Under fault verification techniques we discuss node-fault diagnosis, branch-fault diagnosis, subnetwork testability conditions as well as combinatorial techniques, the failure bound technique, and the network decomposition technique. For the approximation approach we consider probabilistic methods and optimization-based methods. The artificial intelligence technique and the different measures of testability are also considered. The main features of the techniques considered are summarized in a comparative table. An extensive, but not exhaustive, bibliography is provided.     

精密程控电流源的设计及应用

精密程控电流源采用USB通信模式,具有温度测量和输出电流非线性温度补偿功能,输出电流的准确度高、性能稳定可靠.文中介绍此电流源的电路设计、控制软件设计及其应用.     

Trimming analog circuits using floating-gate analog MOS memory

A floating-gate MOS analog memory circuit that can be electrically programmed for positive and negative voltage changes and that can be fabricated in a standard CMOS IC process is described. Unlike existing electrically erasable floating-gate memory circuits, this circuit does not require special fabrication techniques like ultrathin tunneling oxides or textured polysilicon. Instead, mask geometry is used to cause field-enhanced Fowler-Nordheim tunneling of electrons from a floating gate. Retention measurements at elevated temperatures indicate that the loss of floating-gate charge should be less than 0.1% over a ten-year period at temperatures below 100°C. One limitation of this structure is that the rate of change of the floating-gate voltage can be quite small (e.g. 10 mV/s). A general trimming circuits, whose novel feature is that any number of trimming circuits can be independently and simultaneously adjusted across an entire IC, has been incorporated into a prototype CMOS op amp to decrease its input offset voltage from 10 mV to less than 0.5 mV     

Performance comparison of analog and digital circuits

It is the purpose of this paper to compare analog and digital semiconductor circuits. Using simple models, performance of these circuits will be evaluated as far as signal-to-noise ratio, power dissipation, bandwidth, and system capacity are concerned.     

GaAs HBT's for analog circuits

Silicon bipolar integrated circuit (IC) technology has dominated the analog IC world for over two decades. As the push for wider bandwidths with higher precision continues, the emergence of GaAs HBT technology is destined to challenge silicon bipolar's domination at the high end of the analog market. This paper discusses the analog application areas best suited to GaAs HBT technology, points out its unique characteristics for analog circuits, describes the design issues for key analog building block circuits, and provides comparative examples of demonstrated state-of-the-art analog circuits. Finally, a projection of future direction in this application area is provided     

Fault prediction for analog circuits

The main problems that are the major concern in network testing are fault detection, fault location, and fault prediction. In this paper a multiple-fault-prediction algorithm is proposed for analog circuits with inaccessible nodes. The components in the circuits may be nominals or may be deviated from the nominals within a prescribed tolerance.In the proposed prediction algorithm, the component values are evaluated according to the consecutive voltage measurements that are continuously monitored at the accessible test points at each periodic maintenance. The component values are used to locate the faulty components and/or to predict the components that are about to fail.This research was supported in part by AURI, Michigan State University, East Lansing, Michigan, and in part by Michigan Research Excellence/Economic Development Fund.     

Fault simulation of linear analog circuits

Research in the areas of analog circuit fault simulation and test generation has not achieved the same degree of success as its digital counterpart owing to the difficulty in modeling the more complex analog behavior. This article presents a novel approach to this problem by mapping the good and faulty circuits to thediscrete Zdomain. An efficient fault simulation is then performed on this discretized circuit for the given input test wave form. This simulator provides an order of magnitude speedup over traditional circuit simulators. An efficient fault simulator and the formulation of analog fault models opens up the ground for analog automatic test generation.Note 1. Test set 1 = {100, 200, 300, 400, 500, 600, 700, 800, 900, 1000}.Test set 2 = {1.00e+03, 3.16e+04, 1.18e+03, 1.16e+03, 1.06e+03, 1.56e+03, 1.54e+03, 1.26e+03, 2.16e+03, 1.99e+03, 2.83e+03, 7.33e+02, 2.34e+03, 2.47e+03, 3.75e+03, 4.66e+03, 3.02e+00, 3.85e+00, 3.95e+00, 3.80e+00, 4.37e+01}     

Fault simulation of linear analog circuits

Research in the areas of analog circuit fault simulation and test generation has not achieved the same degree of success as its digital counterpart owing to the difficulty in modeling the more complex analog behavior. This article presents a novel approach to this problem by mapping the good and faulty circuits to thediscrete Z-domain. An efficient fault simulation is then performed on this discretized circuit for the given input test wave form. This simulator provides an order of magnitude speedup over traditional circuit simulators. An efficient fault simulator and the formulation of analog fault models opens up the ground for analog automatic test generation.     

Testing analog circuits using spectral analysis

In this work a test strategy for analog circuits based on spectral analysis is proposed. The test strategy is blind, in the sense that only statistical information about the input signal is needed, but no sampling of the input signal is required. This feature allows the test of analog circuits with minimum analog hardware addition. In the context of Systems-on-Chip, this strategy needs only the inclusion of a small random signal generator, and transfers most of the signal processing to the digital domain, allowing the use of a purely digital tester or a digital BIST technique. This paper presents the underlying principle of the method and experimental test results for linear analog systems.     

Trimming analog circuits with solid-state devices

Although simple and inexpensive, trimming potentiometers can be awkward to reach or readjust in large systems. A new alternative is an electrically programmable analog device, called an Epad. The small floating-gate MOS device is programmed with an inexpensive instrument working with a PC. It may be configured to provide a trimmable voltage or resistance, which will hold its setting indefinitely or may be reprogrammed