Advanced digital receiver principles and technologies for PCS

The synergy between digital radio communications and VLSI signal processing is revolutionizing the design of wireless terminals. Driving this synergy are certain fundamental paradigms in modern communication theory, digital signal processing, and VLSI design. The authors discuss the modern centers-of-gravity model, which they believe is emerging as the basis for the successful design and implementation of advanced digital communication systems. Central to this model are design principles that enable engineers to systematically derive digital receiver structures and explore algorithm and architecture trade-offs using sophisticated tools. Digital signal processing technology is critical in the implementation of these digital receiver structures efficiently. Finally, CAD tools for digital communications system design and design space exploration are shown to be of crucial importance in the efficient execution of these designs     

A 2.4 GHz low power wireless transceiver analog front-end for endoscopy capsule system

This work presents the design and implementation of a 2.4 GHz low power wireless transceiver analog front-end for the endoscopy capsule system in 0.25 μm CMOS. The prototype integrates a low-IF receiver analog front-end (low noise amplifier, double-balanced down-converter, band-pass-filtered AGC loop, and ASK demodulator) and a direct-conversion transmitter analog front-end (20 MHz IF PLL with well-defined amplitude control circuit, ASK modulator, up-converter, and output buffer) on a single chip together with one integrated RF oscillator and two LO buffers. Trade-off has been made over the design boundaries of the different building blocks to optimize the overall system performance. All building blocks feature the circuit topologies that enable comfortable operation at low power consumption. As a result, the IC works at a 2.5 V power supply, while only consuming 15 mW in receiver (RX) mode and 14 mW in transmitter (TX) mode. To build a complete transceiver for the endoscopy capsule system, only an antenna, a duplexer, and a digital controller are needed besides the presented analog front-end chip.     

Transceiver with inductive coupling for wireless chip-to-chip communication using a 50-nm digital CMOS process

A wireless type of chip-to-chip communication (WCC) technology is proposed as the next generation of 3D semiconductor technology. To demonstrate the feasibility of this technology, we designed a coil, transmitter and receiver for wireless chip-to-chip communication using a 50-nm digital CMOS process. The coil is designed using inductive coupling with design parameters that include the number of turns, the metal width, and the space between adjacent metal lines. A differential transceiver structure is proposed for the WCC technology. The transmitter of the transceiver acts as a termination and bias circuit for the receiver while the transceiver is operating as a receiver. The receiver is designed with a typical differential amplifier and a latch to recover the transmitted original digital signal. The proposed transceiver and coil for the proposed WCC technology is implemented using commercial 50-nm digital CMOS technology. Experimental results successfully demonstrate the feasibility of the WCC technology.     

GPS接收机中的码分多址信号处理研究

介绍了基于码分多址信号处理的GPS(全球定位系统)接收机的算法和电路设计。GPS接收机电路的信号处理任务主要是对数字化后的基带扩频信号进行载波跟踪、解调、解扩、码跟踪,从而得到符号数据。着重讨论了GPS接收机中信号处理部分的COSTAS、码跟踪、帧同步生成电路三大模块的功能任务、原理、算法及其相应的电路设计。通过这些研究工作,可以进一步设计出当前应用日益普遍的GPS接收机电路,该电路具有功能全面、通用性好、可靠性高等特点。     

Design of a digital FM demodulator based on a 2nd-order all-digital phase-locked loop

Software-defined radio (SDR) is a revolution in radio design due to the ability to create radios that can self-adapt on the fly. In SDR devices, all of the signal processing is implemented in the digital domain, mainly on DSP blocks or by DSP software. By simply downloading a new program, a SDR device is able to interoperate with different wireless protocols, incorporate new services, and upgrade to new standards. Therefore, massively parallel signal processing at higher frequencies are needed to implement a realistic SDR. Thus, FPGAs have been used extensively for implementing essential functions in SDR architectures at lower frequencies. In this paper, we explore the design of a digital FM receiver using the approach of an All-Digital Phase Locked-Loop (ADPLL). The circuit is designed in VHDL, then synthesized and simulated using LeonardoSpectrum Level 3 and ModelSim SE 6, respectively. It operates at a frequency up to 150 MHz and occupies the area of roughly 15 K logic gates.     

Low power high data rate wireless endoscopy transceiver

A low power high data rate wireless endoscopy transceiver is presented. Transceiver architecture, circuit topologies and design trade-offs have been considered carefully to satisfy the tight requirements of the medical endoscopy capsule: lower power consumption, high integration degree and high data rate. The prototype, implemented in 0.25 μm CMOS, integrates a super-heterodyne receiver and a super-heterodyne transmitter on a single chip together with an integrated RF local oscillator and LO buffers. The digital modulation and demodulation is also implemented in analog field and no data converters are needed for the whole endoscopy capsule. The measured sensitivity of the receiver is about −70 dBm with a data rate 256 kbps, and the measured output power of the transmitter could achieve −23 dBm with a data rate 1 Mbps. The transceiver operates from a power supply of 2.5 V, while only consuming 15 mW in receiver (RX) mode and 14 mW in transmitter (TX) mode.     

数字下变频器HSP50214B在中频数字接收机中的应用

数字下变频器（DDC）对侦察接收机的软件化设计至关重要,给出中频数字接收机数字下变频电路实例．实现了数字侦察接收机对多种调制样式信号的高性能处理,展示了数字下变频器HSP50214B在中频数字接收机中的灵活应用。     

Direct-conversion radio transceivers for digital communications

Direct-conversion is an alternative wireless receiver architecture to the well-established superheterodyne, particularly for highly integrated, low-power terminals. Its fundamental advantage is that the received signal is amplified and filtered at baseband rather than at some high intermediate frequency. This means lower current drain in the amplifiers and active filters and a simpler task of image-rejection. There is considerable interest to use it in digital cellular telephones and miniature radio messaging systems. This paper briefly covers case studies in the use of direct-conversion receivers and transmitters and summarizes some of the key problems in their implementations. Solutions to these problems arise not only from more appropriate circuit design but also from exploiting system characteristics, such as the modulation format in the system. Baseband digital signal processing must be coupled to the analog front-end to make direct-conversion transceivers a practical reality     

HF-band radio receiver design based on digital signal processing

The authors address the design of an HF band receiver using commercially available technology, with the aim of producing a receiver whose performance is better than that available with the current purely analogue designs and which incorporates a significant element of digital signal processing. To give the reader an appreciation of some of the system, component and architectural constraints, they first review component limitations and candidate architectures. This is followed by a detailed analysis of a prototype HF band (0.1 to 30 MHz) receiver designed by the authors as part of a recent research programme     

Low-power transceiver analog front-end circuits for bidirectional high data rate wireless telemetry in medical endoscopy applications

State-of-the-art endoscopy systems require electronics allowing for real-time, bidirectional data transfer. Proposed are 2.4-GHz low-power transceiver analog front-end circuits for bidirectional high data rate wireless telemetry in medical endoscopy applications. The prototype integrates a low-IF receiver analog front-end [low noise amplifier (LNA), double balanced down-converter, bandpass-filtered automatic gain controlled (AGC) loop and amplitude-shift keying (ASK) demodulator], and a direct up-conversion transmitter analog front-end [20-MHz IF phase-locked loop (PLL) with well-defined amplitude control circuit, ASK modulator, up-converter, and power amplifier] on a single chip together with an internal radio frequency oscillator and local oscillating (LO) buffers. Design tradeoffs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low power consumption. The circuits have been implemented in a 0.25-microm CMOS process. The measured sensitivity of the receiver analog front-end is -70 dBm with a data rate of 256 kbps, and the measured output power of the transmitter analog front-end could achieve -23 dBm with a data rate of 1 Mbps. The integrated circuit consumes a current of 6 mA in receiver mode and 5.6 mA in transmitter mode with a power supply of 2.5 V. This paper shows the feasibility of achieving the analog performance required by the wireless endoscopy capsule system in 0.25 microm CMOS.     

Electromigration challenges for advanced on-chip Cu interconnects

As technology scales down, the gap between what circuit design needs and what technology allows is rapidly widening for maximum allowed current density in interconnects. This is the so-called EM crisis. This paper reviews the precautions and measures taken by the interconnect process development, circuit design and chip integration to overcome this challenge. While innovative process integration schemes, especially direct and indirect Cu/cap interface engineering, have proven effective to suppress Cu diffusion and enhance the EM performance, the strategies for circuit/chip designs to take advantage of specific layout and EM failure characteristics are equally important to ensure overall EM reliability and optimized performance. To enable future technology scaling, a co-optimization approach is essential including interconnect process development, circuit design and chip integration.     

数字下变频器HSP50214B在中频数字接收机中的应用

数字下变频器(DDC)对侦察接收机的软件化设计至关重要,给出中频数字接收机数字下变频电路实例,实现了数字侦察接收机对多种调制样式信号的高性能处理.展示了数字下变频器HSP50214B在中频数字接收机中的灵活应用.     

Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits

Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology based on superconductors that has emerged as a possible alternative to advanced semiconductor technologies for large scale ultra-high speed, very low power digital applications. Timing of RSFQ circuits at frequencies of tens to hundreds of gigahertz is a challenging and still unresolved problem. Despite the many fundamental differences between RSFQ and semi- conductor logic at the device and at the circuit level, timing of large scale digital circuits in both technologies is principally governed by the same rules and constraints. Therefore, RSFQ offers a new perspective on the timing of ultra-high speed digital circuits.This paper is intended as a comprehensive review of RSFQ timing, from the viewpoint of the principles, concepts, and language developed for semiconductor VLSI. It includes RSFQ clocking schemes, both synchronous and asynchronous, which have been adapted from semiconductor design methodologies as well as those developed specifically for RSFQ logic. The primary features of these synchronization schemes, including timing equations, are presented and compared.In many circuit topologies of current medium to large scale RSFQ circuits, single-phase synchronous clocking outperforms asynchronous schemes in speed, device/area overhead, and simplicity of the design procedure. Synchronous clocking of RSFQ circuits at multigigahertz frequencies requires the application of non-standard design techniques such as pipelined clocking and intentional non-zero clock skew. Even with these techniques, there exist difficulties which arise from the deleterious effects of process variations on circuit yield and performance. As a result, alternative synchronization techniques, including but not limited to asynchronous timing, should be considered for certain circuit topologies. A synchronous two-phase clocking scheme for RSFQ circuits of arbitrary complexity is introduced, which for critical circuit topologies offers advantages over previous synchronous and asynchronous schemes.     

Design and Performance of a Digital Multifrequency Receiver

An experimental multifrequency receiver for recognition of digitally encoded multifrequency signaling was designed, constructed and tested. The receiver is based on a quadrature detection technique that consists of digital demodulation followed by second-order, lowpass digital filtering. The post filtering processing produces an estimate of the amplitude of each of the six multifrequency tones and provides suitable information for thresholding and timing measurements. The receiver performs correctly even when subjected to severe environmental conditions including an analog signal range of 23 dB, 10 ms signal interruptions ('hits') and 20 ms signal spacings. The receiver's operation demonstrates the robustness of the digital signal processing techniques employed. The design of the receiver exploits the use of subsampling techniques to increase the efficiency of the hardware through greater multiplexing. When using subsampling, 128 multifrequency receivers with 16-bit words are realized with 6.5 dual-in-line packages per receiver; commercial TTL logic circuits, a 4-bit serial-parallel pipeline multiplier circuit, serial data and a 16.384 MHz clock are assumed.     

A single-chip tuner for DVB-T

A new architecture is presented for a single-chip tuner for digital terrestrial television, based on existing double conversion and direct conversion topologies. The new design forms part of a mixed-signal Digital Video Broadcasting-Terrestrial (DVB-T) receiver system, employing digital signal processing at baseband to ensure minimal performance requirements for the analog circuitry. To evaluate the potential performance of this new tuner/receiver system, high-level system simulations have been performed, followed by the construction of a prototype DVB-T receiver using a custom-designed analog ASIC which integrates all analog tuner blocks (including channel filtering) on one chip. Measured results from this chip, implemented in a 20-GHz bipolar technology, show an overall third-order input referred intercept point of 116 dB/spl mu/V, a noise figure of 14 dB and an automatic gain control range of 71.4 dB, drawing 250 mA at a 5-V supply.     

Advances ,n Digital Front-End and Software RF Processing： Part I

One of the biggest technology trends in wirelessbroadband, radar, sonar, and broadcasting systems issoftware radio frequency processing and digitalfront-end. This trend encompasses a broad range oftopics, from circuit design and signal processing to systemintegration. It includes digital up-conversion (DUC) and     

A Reconfigurable, 130 nm CMOS 108 pJ/pulse, Fully Integrated IR-UWB Receiver for Communication and Precise Ranging

This paper presents a fully integrated flexible ultra-low power UWB impulse radio receiver, capable of cm-accurate ranging. Ultra-low-power consumption is achieved by employing the quadrature analog correlating receiver architecture, by exploiting the duty-cycled nature of the system, by operating in the sub-1 GHz band as well as by careful circuit design. Two pulse rates, 39.0625 Mpulses per second (Mpps) and 19.531 Mpps, and a wide range of processing gains (0-18 dB) are supported. Also, the acquisition algorithm and accuracy can be adapted at run time. This flexible implementation allows to dynamically trade power consumption for performance depending on the operating conditions and the application requirements. The receiver prototype was manufactured in 130 nm CMOS and the active circuit area measures 4.52 mm². The IC contains a complete analog front-end, digital backend and implements the algorithms necessary for acquisition, synchronization, data reception and ranging. Consuming 4.2 mW when operating at 39.0625 Mpps, it achieves an energy efficiency of 108 pJ/pulse. A 1.3 Mb/s wireless link over more than 10 m in an office-like environment has been demonstrated under direct line-of-sight (LOS) conditions with a raw packet-error-rate (PER) less than 10% and cm-accurate ranging.     

基于GP2010的移动GPS射频前端设计

对GPS射频前端进行了研究与设计,实现了GPS信号射频到数字中频的转化过程。应用GP2010芯片设计出了符合要求的GPS射频前端,包括前端滤波器、低噪声放大器,以及中频滤波器。介绍测试系统的搭建,对实际制作的电路板进行调试,并得出测试结果,为后期基于FPGA实现GPS基带数字信号处理提供GPS数字中频信号,为自主设计GPS接收机奠定了基础。     

VLSI implementation of a signal recognition and code acquisitionalgorithm for CDMA packet receivers

The widespread application of direct-sequence spread-spectrum code division multiple access (DS/SS-CDMA) to wireless communication systems asks for ever faster and more reliable real-time signal processing operations to be performed by highly integrated and low-power consumption digital receivers. One of the most critical signal processing tasks to be performed by the DS/SS-CDMA receiver is signal presence detection and code epoch estimation. This paper deals with the design and realization of an application-specific integrated-circuit (ASIC) for fast signal recognition and code acquisition (SR/CA) in packet DS/SS-CDMA receivers operating in a satellite or terrestrial radio network. In particular, we show how a parallel acquisition circuit can be effectively implemented on a single-chip with a 1.0-μm CMOS technology according to the specifications of the ARCANET Ku-band CDMA VSAT satellite network sponsored by the European Space Agency (ESA). It is shown that the ASIC performance closely follows analytical predictions     

Designing asynchronous circuits for low power: an IFIR filter bankfor a digital hearing aid

This paper addresses the design of asynchronous circuits for low power through an example: a filter bank for a digital hearing aid. The asynchronous design re-implements an existing synchronous circuit which is used in a commercial product. For comparison, both designs have been fabricated in the same 0.7 μm CMOS technology. When processing typical data (less than 50 dB sound pressure), the asynchronous control and data-path logic, an improved RAM design, and by a mechanism that adapts the number range to the actual need (exploiting the fact that typical audio signals are characterized by numerically small samples). Apart from the improved RAM design, these measures are only viable in an asynchronous design. The principles and techniques explained in this paper are of a general nature, and they apply to the design of asynchronous low-power digital signal-processing circuits in a broader perspective. In fact, this understanding is one of the contributions of the paper. Finally, the paper can be read as an example-driven introduction to asynchronous low-power design