Techniques for evaluating harmonic distortion in class-AB output stages: A tutorial

In this paper, we discuss and provide a detailed tutorial of four different methods for analytically evaluating the harmonic distortion in class-AB stages. All the methods are suitable for pencil-and-paper analysis and are based on modeling the stage with a specific non-linear function. We analyze them in details and extend some of them for predicting harmonic distortion behavior in a wide range of input signal amplitude. Comparisons made by means of simulations, reveal that some methods are more precise than others but require more computational effort. On the contrary, some of them are simple to use but are less precise. Moreover, some are more appropriate for predicting HD₂ and others for HD₃, only. Results of the present paper may be used by designers to choose the more efficient method for analyzing distortion in class-AB stages. Gianluca Giustolisi was born in Catania, Italy, in 1971. He received the Laurea degree (cum laude) in electronic engineering and the Ph.D. degree in electrical engineering from University of Catania, Catania, Italy, in 1995 and 1999, respectively. Currently he is associate professor at Dipartimento di Ingegneria Elettrica Elettronica e dei Sistemi (DIEES), University of Catania. His research interests include analysis, modelling and design of analog integrated circuits and systems with particular emphasis on non-linear and low-voltage applications. Gianluca Giustolisi is IEEE Member. Gaetano Palumbo was born in Catania, Italy, in 1964. He received the laurea degree in Electrical Engineering in 1988 and a Ph.D. degree from the University of Catania in 1993. Since 1993 he conducts courses on Electronic Devices, Electronics for Digital Systems and basic Electronics. In 1994 he joined the DEES (Dipartimento Elettrico Elettronico e Sistemistico), now DIEES (Dipartimento di Ingegneria Elettrica Elettronica e dei Sistemi), at the University of Catania as a researcher, subsequently becoming associate professor in 1998. Since 2000 he is a full professor in the same department. His primary research interest has been analog circuits with particular emphasis on feedback circuits, compensation techniques, current-mode approach, low-voltage circuits. Then, his research has also embraced digital circuits with emphasis on bipolar and MOS current-mode digital circuits, adiabatic circuits, and high-performance building blocks focused on achieving optimum speed within the constraint of low power operation. In all these fields he is developing some the research activities in collaboration with STMicroelectronics of Catania. He was the co-author of three books “CMOS Current Amplifiers” and ”Feedback Amplifiers: theory and design” and “Model and Design of Bipolar and MOS Current-Mode Logic (CML, ECL and SCL Digital Circuits)” all by Kluwer Academic Publishers, in 1999, 2001 and 2004, respectively. He is a contributor to the Wiley Encyclopedia of Electrical and Electronics Engineering. He is the author of more than 250 scientific papers on referred international journals (over 100) and in conferences. Moreover he is co-author of several patents. In 1999/2001 and 2004/2005 he served as Associated Editor of the IEEE Transactions on Circuits and Systems part I for the topic “Analog Circuits and Filters” and “Digital Circuits and Systems”, respectively. In 2005 he was one of the 12 panelists in the scientific-disciplinare area 09 - industrial and information engineering of the CIVR (Committee for Evaluation of Italian Research), which has the aim to evaluate the Italian research in the above area for the period 2001–2003. In 2003 he received the Darlington award. Since 2006 he is serving as Associated Editor of the IEEE Transactions on Circuits and Systems part I. Prof. Palumbo is an IEEE Senior Member.     

Electronically tunable CMOS class-AB output stage

A new technique for CMOS class-AB output stages is introduced in this Letter. The technique uses a master–slave configuration of a complementary common-source output stage. It offers the advantage that the quiescent and minimum currents of the output stage can be independently tuned. The effectiveness of the proposed technique was verified by simulations using a standard n-well 0.18 μm CMOS process with 1 V supply voltage. A voltage buffer, that includes the proposed output stage, is able to drive a capacitive load of 0.5 nF obtaining −63 dB total harmonic distortion. The topology features also power efficiency of about 63% for a pure resistive output load equal to 50 Ω.     

Parallel feedforward class-AB control circuits for low-voltage bipolar rail-to-rail output stages of operational amplifiers

A new family of class-AB control circuits for bipolar rail-to-rail output stages of operational amplifiers is presented. Step by step, we report the development of five simple class-AB control circuits showing the advantages of using parallel feedforward. The circuits have been designed in such a way that temperature, supply voltage and process parameters have little influence. To test the output stages, one of them has been implemented in a very simple two-stage operational amplifier on a semi-custom chip. Measurements show a bandwidth of 2.5 MHz, a gain of 40 dB, a quiescent current of 23µA and a maximum output current of 250µA. Simulation results of three other simple operational amplifiers with the new class-AB control circuits are shown, which have a higher gain and maximum output current.     

Analysis of latch-up neighborhood effects in VLSI CMOS input and output stages

The influence of electron and hole injection from neighboring structures on the latch-up hardness of an inverter in non-epitaxial CMOS is measured on specially designed test structures and compared with the results of two-dimensional numerical simulation provided by the program BAMBI. An analysis of the basic effects is given and remedial measures to avoid neighborhood effects are described.     

一种恒流输出大屏幕LED驱动CMOS芯片的电路设计

LED显示屏已经成为各类户外户内的广告宣传展示的首选媒介。LED以其寿命长,功耗低节能环保的优点,深受照明和显示行业的欢迎。因此,LED的驱动芯片在市场上也有很大的需求。本文介绍了一种恒流输出大屏幕LED驱动CMOS芯片的设计,工作电压范围是3.3V-5.5V,工作温度范围是-40℃-125℃。该驱动芯片对恒流输出和各路匹配性进行针对性的设计。以外接电流共同调节16路恒流电流大小,串行数字输入输出分别控制16路使能状态,使能端输入PWM信号,对恒流输出进行脉宽调节。该芯片使用HSPICE软件仿真工具设计,并采用HYNIX0.5μm工艺制作,测试验证结果表明,各路恒流输出位间电流误差最大为±2%.     

Design model and guidelines for n-well guard ring in epitaxial CMOS

This work reports the development of design model for n-well guard rings in a CMOS process utilizing a low-doped epitaxial layer on a highly doped substrate. The validity of the model has been judged by a wide range of experimental data measured from the fabricated n-well guard ring structures with guard ring width as parameter. From the model developed, guidelines have been drawn to minimize the guard ring width while critically suppressing the amount of electrons escaping from the guard ring     

A CMOS power amplifier with a novel output structure

A two-stage op-amp with a novel output driver achieves 5.8-MHz GBW, 68° phase margin, and delivers 2.6 V_pp with a THD of 0.14% and 3.2 V_pp with a THD of 0.38% into 100 Ω at 20 kHz for a ±2.5-V supply. The output driver enables a very simple circuit measuring only 0.11 mm²     

Current-mode CMOS integrated circuits for analog computation and signal processing: A tutorial

This paper presents an overview of design techniques for a broad range of current-mode analog integrated circuits implemented in CMOS technology at a tutorial level. Primarily, emphasis is placed on circuit configurations, first-order analysis, and approximate design equations for analog integrated circuits operating in current domain for signal computation and processing applications.     

Design guidelines for the integration of Geiger-mode avalanche diodes in standard CMOS technologies

The goal of this paper is to provide some useful design guidelines at the device level regarding the main challenges to be typically faced in the design and integration of Geiger-mode avalanche diodes in a standard CMOS process. Different techniques are found in literature in order to avoid premature edge breakdown with the aim of limiting the electric field at the edges to be weaker than in the multiplication region. In this article, the use of such techniques, the conditions where they can effectively work and above all their limitations are studied by means of TCAD simulations for various diode architectures. Additionally, the noise performance is discussed by focusing on the band-to-band tunneling and shallow trench isolation enhanced dark count rates. Geiger-mode bias techniques as well as a synthesis on the pros and cons of the various avalanche diode architectures are finally presented aiming at facilitating future design choices.     

Speaker recognition: a tutorial

A tutorial on the design and development of automatic speaker-recognition systems is presented. Automatic speaker recognition is the use of a machine to recognize a person from a spoken phrase. These systems can operate in two modes: to identify a particular person or to verify a person's claimed identity. Speech processing and the basic components of automatic speaker-recognition systems are shown and design tradeoffs are discussed. Then, a new automatic speaker-recognition system is given. This recognizer performs with 98.9% correct decalcification. Last, the performances of various systems are compared     

Satellite-based Internet: a tutorial

In a satellite-based Internet system, satellites are used to interconnect heterogeneous network segments and to provide ubiquitous direct Internet access to homes and businesses. This article presents satellite-based Internet architectures and discusses multiple access control, routing, satellite transport, and integrating satellite networks into the global Internet     

Speaker verification: a tutorial

The task of speaker verification, a subset of the general problem of speaker recognition is defined. The feature selection and pattern matching steps of the recognition procedure are examined. Speaker verification system design and performance are discussed, and databases for evaluating them are briefly considered. An example of a speaker verification system is described. An overview of industry research in this area is given     

1.2-V CMOS op-amp with a dynamically biased output stage

A very low-voltage operational amplifier in a standard CMOS process with a 0.75 V threshold voltage is presented. It uses a novel dynamically biased output stage based on the switched-capacitor approach. Thanks to this, drive performance is greatly improved and accurate current control is also achieved. The amplifier is capable of working with a power supply as low as 1.2 V while providing a -74 dB total harmonic distortion with a 700 mV peak-to-peak output voltage into a 500 Ω and 20 pF output load. The open-loop gain and the gain-bandwidth product are higher than 90 dB and 2.2 MHz, respectively     

The Internet: a tutorial

The Internet is a world-wide packet-switched network that connects together well over 10 million computers in over 100 countries for the purpose of information sharing. This paper is a tutorial on Internet technology-how it works now and how it is changing as the network becomes more commercial. It covers the underlying design of the Internet, the `connectionless service model', and the applications that run over the network: the World Wide Web and other popular systems that have made the network growth so explosive in recent years     

一种低压差CMOS线性稳压器的设计

设计了一种输入电压范围为1.9~5 V,输出电压为1.8 V的LDO。采用零点-极点追踪频率补偿方案,补偿结构简单,可动态补偿输出极点;利用PMOS管与NMOS管阈值电压相互补偿的特性,设计了基准电压源,具有结构简单、版图面积小等优点。基于GSMC 0.18 μm CMOS工艺,采用Spectre软件对电路进行仿真。仿真结果表明,电路的带宽为4 MHz,低频段时电源抑制比达到125 dB,静态电流只有80 μA。     

一种高速CMOS电荷泵锁相环设计

文章描述了一种高速CMOS电荷泵锁相环设计与仿真。电路设计基于TSMC 2．5V 0．25μm CMOS工艺。用Cadence Artist Analog对电路仿真的结果显示,用它可以实现快速锁定和较低的功耗。     

一种高线性度CMOS混频器的设计

采用线性化技术改进的混频器结构提高了线性度.采用TSMC 0.18 μm RF CMOS模型进行了电路仿真.仿真结果:在电源电压为1.8 V时,输入三阶截断点(IIP3)为10.3 dBm,输入1dB压缩点(P-1dB)为-3.5 dBm,增益为9.2 dB,单边带噪声系数为17 dB.     

Parallel video servers: a tutorial

In conventional video-on-demand (VoD) systems, compressed digital video streams are stored in a video server for delivery to receiver stations over a communication network. This article introduces a framework for the design of parallel video server architectures and addresses three central architectural issues: video distribution architectures, server striping policies, and video delivery protocols     

Network computing: a tutorial review

Network computing is generally considered to be an unsuccessful initiative. It is strongly associated in the minds of many with the overhyped network computer that failed to capture a significant market share from PCs. However, network computing and network computers are not synonymous. In fact, one of the major benefits of network computing is the ability to tailor applications to the capabilities of heterogeneous client devices. Given the very fast growing mobile computing market, with its numerous and diverse terminal types, network computing could at last realise its full potential. This tutorial paper provides an overview of computing from the early mainframes to today's multiplicity of computing devices. The advantages of network computing are discussed and an overview is provided of some of the underpinning technologies. To provide an insight into the potential of network computing, two applications are described. Some overall conclusions are also given     

Network management: a tutorial overview

The difficulties of managing information networks is explored from the perspective of today's and tomorrow's typical enterprise, whether small and large businesses, government agencies, universities, or other organizations, and eventually even residential customers. A historical review of communication network management is given, beginning with the telephone network and moving on to computer and information networks. Customer needs and market segmentation are discussed. Industry response to network management issues and requirements are examined, covering the development of OSI (Open Systems Interconnection) standards for network management, specification of companion implementation agreements, and provision for conformance testing capability