512×512元高帧速可见光CCD

CCD具有低响应非线性、宽光谱响应、低噪声、高动态范围和测光精度,已被广泛应用于许多成像领域.本文介绍了利用三层多晶硅、埋沟、双层金属工艺研制的16抽头512×512元高帧速可见光CCD.测试结果表明,该器件具有高的光响应均匀性、高动态范围和低噪声,并已成功应用于高分辨率高速成像.     

Efficient arbitrary sampling rate conversion with recursivecalculation of coefficients

In this paper, we present a novel algorithm for sampling rate conversion by an arbitrary factor. Theoretically, sampling rate conversion of a discrete-time (DT) sequence can be performed by converting the sequence to a series of continuous-time (CT) impulses. This series of impulses is filtered with a CT lowpass filter, and the output is then sampled at the desired rate. If the CT filter is chosen to have a rational transfer function, then this system can be simulated using a DT algorithm for which both computation and memory requirements are low. The DT implementation is comprised of a parallel structure, where each branch consists of a time-varying filter with one or two taps, followed by a fixed recursive filter operating at the output sampling rate. The coefficients of the time-varying filters are calculated recursively. This eliminates the need to store a large table of coefficients, as is commonly done     

A multiple sampling, single A/D conversion technique for I/Qdemodulation in CMOS

We have developed a CMOS A/D converter for I/Q demodulation with an analog mirror signal suppression filter in the sampling unit. The circuit directly converts a modulated 30 MHz IF signal to digitized I and Q values in the base band with an accuracy of more than 10 b. The output data rate is 2 MHz and the power consumption is 270 mW. By placing the I/Q split mirror suppression filter on the analog side, we can get a highly integrated system solution for a coherent receiver. The circuit uses multiple sampling, that gives the input values to the filter. The sizes of the sampling capacitors determine the coefficients for the filter multiplications. The sampled charges are then added in order to get the filter additions. This total charge is then converted to digital form in a single conversion. By requiring the filter to block DC, the filter subtraction becomes a part of the active offset reduction using correlated double sampling. Careful layout and very simple circuit solutions make the design possible     

Sample rate conversion for software radio

Software radio terminals must be able to process many various communications standards. These standards are generally based on different master clock rates and thus employ different bit/chip rates. The most obvious solution to cope with the diversity of master clock rates in one terminal is to provide a dedicated master clock for each standard of operation. Not only too costly, this kind of solution limits the applicability of a realized terminal. Hence, it is much more elegant to run the terminal on a fixed clock rate, and perform digital sample rate conversion controlled by software     

达曼类滤波器的飞秒脉冲整形技术

为了研究飞秒激光时空变换整形技术,采用理论分析与计算机模拟结合讨论的方法,分析了以达曼类滤波器为模板的4f 系统的飞秒脉冲整形技术。以梯度算法优化设计出达曼类滤波器,包括等间距、等强度和不等间距、不等强度达曼光栅,并模拟讨论了产生的超快时域多脉冲与光谱平面上调制周期的重复数、元件间距不等效应和波长效应的影响。结果表明,以达曼类滤波器为模板的飞秒脉冲整形中,模板周期重复数越多,输出脉冲的质量越高;元件间距不等和波长效应使输出脉冲的平均度和衍射效率都有所降低。     

Low distortion feedback voltage-current conversion technique

A bilateral voltage-current convertor (VCCS) using modified Wilson current mirrors in a feedback configuration is presented that produces substantially lower distortion than previous open loop arrangements.     

A ratio-independent algorithmic analog-to-digital conversion technique

An algorithmic analog-to-digital conversion technique is described which is capable of achieving high-resolution conversion without the use of matched capacitors in an MOS technology. The exact integral multiplication of the signal required by the conversion is realized through an algorithmic circuit method which involves charge summing with an MOS integrator and exchange of capacitors. A first-order cancellation of the charge injection effect from MOS transistor switches is attained with a combination of differential circuit implementation and an optimum timing scheme. An experimental prototype has been fabricated with a standard 5-/spl mu/m n-well CMOS process. It achieves 12-bit resolution at a sampling rate of 8 kHz. The analog chip area measures 2400 mils/SUP 2/.     

A 512-bit shift register using compact two-phase single fluxquantum clock generators with large margins and low power

A 512-b shift register was built and tested up to 14.5 GHz. The shift register uses a two-phase clock which is generated by coupling a master control line over many asymmetrically biased two-junction SQUIDs. Compared with other shift registers with Josephson transmission lines to deliver clock, this new clock system provides short delay, low power dissipation, and large DC bias margins. The shift register uses about 3000 Nb/AlO_x/Nb Josephson junctions and consumes about 0.1 mW     

Some properties of multidimensional sampling rate conversion

In this letter it is shown that sampling rate conversion?either interpolation or decimation?of multidimensional digital signals can be realised merely by the use of one-dimensional filter design techniques. It is then proved that multidimensional rate conversion can be performed on a dimension-by-dimension basis, leading to the establishment of its commutative and associative properties.     

Current-mode cyclic A/D conversion technique

A cyclic analogue-to-digital (A/D) conversion technique using current copiers is described. The technique requires two steps per bit conversion. The resulting digital codes are insensitive to process component mismatches. This method can be applied to both the cyclic and the pipeline structure depending on the design requirements.<>     

Analogue buffer memory for high speed rate conversion

A new sampled data technique is introduced, capable of providing real-time spectral compression of large input bandwidths, while requiring a single sampling operation to be performed at the lower output data rate. The proposed configuration, based on a tapped delay line and CMOS integrated multiplexers, exhibits dual properties for spectral expansion; unique features are the capability of accepting data directly at RF format, with power consumption and switching speed requirements independent of the maximum processed data rate. Sampling rates as high as 25 MHz are demonstrated, requiring only 2.5 MHz tap switching frequency to be performed for a time compression factor of 10.     

Design criteria for video sampling rate conversion filters

The design of video sampling rate conversion filters is discussed. It is demonstrated that for such filters to produce a satisfactory picture quality at the new sampling rate, further constraints on the frequency response of the filters are required than have previously been published.<>     

On a recursive A/D conversion technique

This letter focuses on a recursive method proposed by the author several years ago and now suitable for a system-level IC implementation. Some comments referring to the flexibility and operability of such a class of devices are also reported.     

我国不同积分时间降雨率的统一转换模式

1min积分时间降雨率概率分布是10GHz以上无线电系统雨衰减预测的基础性数据。但多数气象台站降雨率数据的积分时间大于1min,因而需要一种有效的转换方法。为此利用我国典型气候区的实测降雨率数据对几种不同积分时间降雨率转换模式进行了参数拟合与结果比较,在比较研究的基础上,提出了我国统一的转换模式。这一模式可较好地用于我国不同地区的降雨率转换。     

A monolithic 8-bit A/D converter with 120 MHz conversion rate

A monolithic 8-bit flash A/D converter is described which digitizes a 40-MHz signal at a conversion rate of over 100 MHz. To obtain full resolution and high accuracy at ultrahigh speed operation, a three-stage comparator with small talk back and other new logic circuits were designed. The process used is a self-aligned bipolar technology. Signal-to-noise ratio of 45 dB was measured at the 30-MHz input frequency.     

A technique for very-high-speed pulse generation with variable repetition rate

A simple technique is proposed for the generation of high-speed variable repetition rate pulse-trains by summing the output pulses from a series at variable delay step recovery diode circuits. The diode switching times determine the maximum repetition rate, which is several gigahertz.     

Non reciprocal single mode conversion in multilayer magnetooptical waveguides

Multilayer structures are of great interest in the fabrication of single mode devices for Integrated Optics. this work it is shown that a multilayer structure allows not only single-mode behaviour but it enhaces the non-reci procity of the quide.     

An experimental 512-bit nonvolatile memory with ferroelectricstorage cell

An experimental 512-b random-access memory based on ferroelectric-capacitor storage cells has been successfully fabricated and tested. The device was designed solely for use in process development and electrical characterization and includes onboard test circuitry for that purpose. The internal timing of the memory is controlled externally to allow experimentation with timing algorithms, hence the name 512 externally controlled device, or 512 ECD. The authors discuss the properties of the ferroelectric ceramics used in integrated circuit memories, the operation of a destructively read ferroelectric memory cell, and the organization of the 512 ECD die, including its onboard test circuitry. Finally, retention and wear-out properties of ferroelectric capacitors are discussed as they relate to design requirements     

An 8-b ADC with over-Nyquist input at 300-Ms/s conversion rate

An 8-b flash analog-digital (A/D) converter (ADC) LSI for high-speed data acquisition systems such as digital oscilloscopes and wave digitizers is described. This converter can convert analog input signals over the Nyquist frequency (up to 200 MHz) at a conversion rate of 300 megasamples per second (Ms/s) without glitch errors. In addition, it can be operated at up to 440 Ms/s when input frequency is as low as 100 kHz. This ADC is fabricated by a 2.5-μm, 10-GHz f_T , Si bipolar technology called the advanced sidewall base contact structure (advanced SICOS) technology. For high-performance glitch error suppression, an inhibitory circuit and a comparator design with an inner clock buffer are developed. Both techniques require few hardware additions