Design and Numerical Evaluation of Cascade-Type Thermoelectric Modules

Thermoelectric (TE) generation performance can be enhanced by stacking several TE modules (so-called cascade-type modules). This work presents a design method to optimize the cascade structure for maximum power output. A one-dimensional model was first analyzed to optimize the TE element dimensions by considering the heat balance including conductive heat transfer, Peltier heat, and Joule heat, assuming constant temperatures at all TE junctions. The number of p–n pairs was successively optimized to obtain maximum power. The power output increased by 1.24 times, from 12.7 W in a conventional model to 15.7 W in the optimized model. Secondly, a two-dimensional numerical calculation based on the finite-volume method was used to evaluate the temperature and electric potential distributions. Voltage–current characteristics were calculated, the maximum power output was evaluated, and the efficiencies of two possible models were compared to select the optimal design. The one-dimensional analytical approach is effective for a rough design, and multidimensional numerical calculation is effective for evaluating the dimensions and performance of cascade-type TE modules in detail.     

Fully integrated signal conditioning of an accelerometer for implantable pacemakers

This paper shows the development of a fully integrated G _m -C 0.5–7 Hz bandpass amplifier (gain G = 400), for a piezoelectric accelerometer to be employed in rate adaptive pacemakers. The circuit, fabricated in a standard 0.8 micron CMOS technology, operates with a power supply as low as 2 V, consumes 230 nA of current, and has only a 2.1 μV_rms input referred noise. Detailed circuit specifications, measurements, and a system performance comparative analysis are presented. The physical activity system includes a fully integrated G _m -C rectifier and 3-second time average. Fully integrated very low frequency circuits were implemented with the aid of series-parallel current division in symmetrical OTAs. OTAs as low as 33 pS (equivalent to a 30 GΩ resistor) were designed, fabricated, and tested.     

An Efficient Method for Evaluating Complex Polynomials

We propose an efficient hardware-oriented method for evaluating complex polynomials. The method is based on solving iteratively a system of linear equations. The solutions are obtained digit-by-digit on simple and highly regular hardware. The operations performed are defined over the reals. We describe a complex-to-real transform, a complex polynomial evaluation algorithm, the convergence conditions, and a corresponding design and implementation. The latency and the area are estimated for the radix-2 case. The main features of the method are: the latency of about m cycles for an m-bit precision; the cycle time independent of the precision; a design consisting of identical modules; and digit-serial connections between the modules. The number of modules, each roughly corresponding to serial-parallel multiplier without a carry-propagate adder, is 2(n?+?1) for evaluating an n-th degree complex polynomial. The method can also be used to compute all successive integer powers of the complex argument with the same latency and a similar implementation cost. The design allows straightforward tradeoffs between latency and cost: a factor k decrease in cost leads to a factor k increase in latency. A similar tradeoff between precision, latency and cost exists. The proposed method is attractive for programmable platforms because of its regular and repetitive structure of simple hardware operators.     

MEMS加速度计在振动环境下的可靠性分析

以电容式MEMS加速度计的悬臂梁结构为研究对象,分析了振动环境下MEMS加速度计的典型失效模式及失效机理;在Miner理论的基础上,引入了应力-寿命曲线,建立了疲劳可靠性模型;在考虑强度退化前提下,基于应力强度干涉理论建立了塑性形变可靠性模型;运用蒙特卡洛法验证了两种可靠性模型的准确性,并分析了模型关键参数对可靠度的影响。结果显示,振动应力水平和材料的屈服强度对可靠度有显著的影响,减小应力幅值,增大屈服强度,可以提高MEMS加速度计的可靠性。     

Improvement in Thermoelectric Performance of SnS Due to Electronic Structure Modification Under Biaxial Strain

Ab-initio calculations using the full potential linearized augmented plane-wave technique and the semi-classical Boltzmann theory are used to study thermoelectric properties of unstrained SnS and at 1%, 2% and 3% applied biaxial tensile (BT) strain. The studies are carried out at 800 K for p-type and n-type carriers. For an increase in BT strain, lattice constants of SnS change causing changes in the band structure and increase in the band gap which in turn modifies thermoelectric coefficients. In the case of unstrained SnS, the maximum thermopower (S) obtained is 426 μV/K at carrier concentration 5.40?×?10¹⁸ cm^?3 for p-type carriers and 435 μV/K at carrier concentration 1.68?×?10¹⁸ cm^?3 for n-type carriers. At 3% applied BT strain, S is increased to 696 μV/K at carrier concentration 4.61?×?10¹⁷ cm^?3 for p-type carriers and 624 μV/K at carrier concentration 3.21?×?10¹⁷ cm^?3 for n-type carriers. The power factor (PF) increases?～?2 times at 3% BT strain as compared to unstrained SnS, and it is 6.20 mW K^?2 m^?1 for p-type carriers. For n-type carriers, PF at 3% applied BT is slightly less than the PF for unstrained SnS, which is 6.81 mW K^?2 m^?1. For both types of carriers, the figure of merit (ZT) is found to be?～?1.5 for unstrained SnS. For p-type carriers ZT is enhanced 1.4 times at 3% applied BT strain as compared to that of unstrained SnS. However, for n-type carriers, ZT does not change drastically with increase in BT strain.     

A 90 μW continuous-time front-end with 10b SAR-ADC for capacitive MEMS accelerometers

This paper presents a low power read-out front-end for 3-axis MEMS capacitive accelerometer. The front-end includes the analog preamplifier (to sense the signal coming from the MEMS) and a Successive-Approximation 10b A/D Converter, for digitalization and off-chip digital-signal-processing. Power minimization is achieved by using a continuous-time sensing preamplifier (i.e. constant-charge capacitance-to-voltage conversion) and SAR-ADC with bridge capacitive reduction. Preamplifier programmable in-band gain allows to accommodate different MEMS sensitivities. A very high-impedance MOS transistor is used for MEMS biasing, thus providing very low frequency (<1 Hz) AC coupling. In a 0.13 μm CMOS technology, the full channel consumes 90 μW from a single 1.2 V supply voltage, and achieves an equivalent 67.9 dB_Full-Scale@SNR in [1 Hz–4 kHz] bandwidth by exploiting oversampling ratio.     

Computationally Secure Pattern Matching in the Presence of Malicious Adversaries

We propose a protocol for the problem of secure two-party pattern matching, where Alice holds a text t∈{0,1}^? of length n, while Bob has a pattern p∈{0,1}^? of length m. The goal is for Bob to (only) learn where his pattern occurs in Alice’s text, while Alice learns nothing. Private pattern matching is an important problem that has many applications in the area of DNA search, computational biology and more. Our construction guarantees full simulation in the presence of malicious, polynomial-time adversaries (assuming the hardness of DDH assumption) and exhibits computation and communication costs of O(n+m) group elements in a constant round complexity. This improves over previous work by Gennaro et al. (Public Key Cryptography, pp. 145–160, 2010) whose solution requires overhead of O(nm) group elements and exponentiations in O(m) rounds. In addition to the above, we propose a collection of protocols for important variations of the secure pattern matching problem that are significantly more efficient than the current state of art solutions: First, we deal with secure pattern matching with wildcards. In this variant the pattern may contain wildcards that match both 0 and 1. Our protocol requires O(n+m) communication and O(1) rounds using O(nm) computation. Then we treat secure approximate pattern matching. In this variant the matches may be approximated, i.e., have Hamming distance less than some threshold, τ. Our protocol requires O(nτ) communication in O(1) rounds using O(nm) computation. Third, we have secure pattern matching with hidden pattern length. Here, the length, m, of Bob’s pattern remains a secret. Our protocol requires O(n+M) communication in O(1) rounds using O(n+M) computation, where M is an upper bound on m. Finally, we have secure pattern matching with hidden text length. Finally, in this variant the length, n, of Alice’s text remains a secret. Our protocol requires O(N+m) communication in O(1) rounds using O(N+m) computation, where N is an upper bound on n.     

基于Kalman滤波和六位置法的加速度计标定补偿

加速度计的零偏、刻度因子、安装误差都会影响加速度计的精度。以微机械系统(MEMS)加速度计为实验对象,采用卡尔曼(Kalman)滤波对实验数据进行滤波,结合六位置法得到MEMS加速度计的零偏、刻度因子、安装误差与MEMS加速度计测量值的关系,最终获得基于Kalman滤波和六位置法的MEMS加速度计标定补偿数学模型。通过实验测试表明,补偿后MEMS加速度计的输出值更接近标准值,且加速度计解算俯仰角(-90°~+90°)的绝对误差由补偿前的1°经补偿后减小为0.34°。验证了该标定补偿算法的可行性,对提高MEMS加速度计测量精度有较好的理论和工程应用价值。     

FPGA-based Novel Adaptive Scheme Using PN Sequences for Self-Calibration and Self-Testing of MEMS-based Inertial Sensors

We propose a novel adaptive technique based on pseudo-random (PN) sequences for self-calibration and self-testing of MEMS-based inertial sensors (accelerometers and gyroscopes). The method relies on using a parameterized behavioral model implemented on FPGA, whose parameters values are adaptively tuned, based on the response to test pseudo-random actuation of the physical structure. Dedicated comb drives actuate the movable mass with binary maximum length pseudo-random sequences of small amplitude, to keep the device within the linear operating regime. The frequency of the stimulus is chosen within the mechanical spectral operating range of the micro-device, such that the induced response leads to the identification of the mechanical transfer function, and to the tuning of the associated digital behavioral model. In case of a micro-gyroscope, experimental results demonstrate the adaptive tracking of the damping coefficient from 5.57?×?10^?5? Kg/s to 7.12?×?10^?5? Kg/s and of the stiffness coefficient from 132?N/m to 137.7?N/m. In the case of a MEMS accelerometer, the damping and stiffness coefficients are correctly tracked from 3.4?×?10^?3? Kg/s and 49.56?N/m to 4.57?×?10^?3? Kg/s and 51.48?N/m, respectively—the former values are designer-specified target values, while the latter are experimentally measured parameters for fabricated devices operating in a real environment. Hardware resources estimation confirms the small area the proposed algorithm occupies on the targeted FPGA device.     

Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy

This paper presents simulations of three different implementations of the minority-3 function, with special focus on mismatch analysis through statistical Monte Carlo-simulations. The simulations clearly favors the minority-3 Mirrored gate, and a gate-level redundancy scheme, where identical circuits with the same input drive the same output-node, is further explored as a means of increasing fault- and defect-tolerance. Important trade-offs between supply voltage, redundancy and yield are revealed, and V _DD = 175 mV is suggested as a minimum useful operating voltage, combined with a redundancy factor of 2, in 90 nm CMOS.     

Fabrication of a Flexible Bismuth Telluride Power Generation Module Using Microporous Polyimide Films as Substrates

In this study, we investigated the effect of the structure of microporous p-type (Bi_0.4Te₃Sb_1.6) and n-type (Bi_2.0Te_2.7Se_0.3) BiTe-based thin films on their thermoelectric performance. High-aspect-ratio porous thin films with pore depth greater than 1 μm and pore diameter ranging from 300 nm to 500 nm were prepared by oxygen plasma etching of polyimide (PI) layers capped with a heat-resistant block copolymer, which acted as the template. The cross-plane thermal conductivities of the porous p- and n-type thin films were 0.4 W m^?1 K^?1 and 0.42 W m^?1 K^?1, respectively, and the dimensionless figures of merit, ZT, of the p- and n-type BiTe films were estimated as 1.0 and 1.0, respectively, at room temperature. A prototype thermoelectric module consisting of 20 pairs of p- and n-type strips over an area of 3 cm × 5 cm was fabricated on the porous PI substrate. This module produced an output power of 0.1 mW and an output voltage of 0.6 V for a temperature difference of 130°C. The output power of the submicrostructured module was 1.5 times greater than that of a module based on smooth BiTe-based thin films. Thus, the thermoelectric performance of the thin films was improved owing to their submicroscale structure.     

Design and simulation of High Q MEMS LC-tank for oscillators

This research focuses on the design of a high-performance MEMS LC-tank using a high Q MEMS inductor and capacitor. A two different gap varactor has been used to avoid pull-in voltage at 2.4 GHz. The layout has been done by CoventorWare software. The DC voltage is 2.5 v, which is applied to the plates and results of 2.04 pF could be gained. The Q factor of the varactor is computed at about 557.27, which is good enough to make a low-phase noise VCO. A hollow spiral inductor with a silicon base substrate for compatibility with CMOS technology has been designed. The Greenhouse equation has been used to obtain the dimensions of the inductor. A suspended inductor has been implemented to avoid substrate coupling. The simulation has been done by CoventorWare. The Q factor of the inductor has been calculated using Yue's model. The resultant values of inductance and the Q factor at 2.4 GHz, are 2.89 nH and 27, respectively, which are in good agreement with the results of theoretical computation. The results were verified with the well-documented literature.     

Architectured Materials to Improve the Reliability of Power Electronics Modules: Substrate and Lead-Free Solder

Power electronics modules (>100 A, >500 V) are essential components for the development of electrical and hybrid vehicles. These modules are formed from silicon chips (transistors and diodes) assembled on copper substrates by soldering. Owing to the fact that the assembly is heterogeneous, and because of thermal gradients, shear stresses are generated in the solders and cause premature damage to such electronics modules. This work focuses on architectured materials for the substrate and on lead-free solders to reduce the mechanical effects of differential expansion, improve the reliability of the assembly, and achieve a suitable operating temperature (<175°C). These materials are composites whose thermomechanical properties have been optimized by numerical simulation and validated experimentally. The substrates have good thermal conductivity (>280 W m^?1 K^?1) and a macroscopic coefficient of thermal expansion intermediate between those of Cu and Si, as well as limited structural evolution in service conditions. An approach combining design, optimization, and manufacturing of new materials has been followed in this study, leading to improved thermal cycling behavior of the component.     

Development of an Mg2Si Unileg Thermoelectric Module Using Durable Sb-Doped Mg2Si Legs

Mg₂Si unileg structure thermoelectric (TE) modules, which are composed only of n-type Mg₂Si legs, were fabricated using Sb-doped Mg₂Si. The Mg₂Si TE legs used in our module were fabricated by a plasma-activated sintering method using material produced from molten commercial doped polycrystalline Mg₂Si, and, at the same time, nickel electrodes were formed on the Mg₂Si using a monobloc plasma-activated sintering technique. The source material used for our legs has a ZT value of 0.77 at 862 K. The TE modules, which have dimensions of 21 mm × 30 mm × 16 mm, were composed of ten legs that were connected in series electrically using nickel terminals, and the dimensions of a single leg were 4.0 mm  × 4.0 mm × 10 mm. From evaluations of the measured output characteristics of the modules, it appeared that the electrical resistance of the wiring that is used to connect each leg considerably affects the power output of the unileg module. Thus, we attempted to reduce the wiring resistance of the module and fabricated a module using copper terminals. The observed values of the open-circuit voltage and output power of the Sb-doped Mg₂Si unileg module were 496 mV and 1211 mW at ΔT = 531 K (hot side: 873 K; cool side: 342 K).     

Yield enhancement techniques for 3-dimensional random access memories

As the advances of process technology keep growing, three-dimensional (3D) integration with through silicon vias is a new alternative solution to extend Moore’s law especially for random access memories (RAMs). In general, the reliability and fabrication yield of the traditional 2D memories can be improved by the incorporation of some form of redundancy. However, for 3D integration, the scenarios for the repair process are totally different. The redundancy exclusively added in a memory tier can also be reused to repair defects in the other memory tier after the bonding process. That is, the concept of inter-tier redundancy can be exploited to further increase the yield of 3D memories. Die-to-die and die-to-wafer bonding can be adopted. In this paper, we propose an efficient die-stacking flow and the corresponding built-in self-repair architectures for yield enhancement of 3D memories. The matching problem for die stacking can be converted into a bipartite graph maximal matching problem and the traditional algorithm can be used to solve this problem. Experimental results show that the proposed stacking flow, algorithm, and the corresponding BISR (built-in self-repair) architecture can improve fabrication yield significantly.     

FIR数字滤波在MEMS加速度计中的应用

简要分析了MEMS加速度计应用模型中的噪声来源,介绍了FIR数字低通滤波器的设计方法,并用FPGA实现的FIR滤波器对MEMS加速度计的输出信号进行了实时滤波处理。通过对滤波前后时、频域信号的比较,可以看出采用FIR数字低通滤波器能有效抑制加速度计输出信号中的高频噪声、提高加速度计的测量精度。实验结果表明,滤波前噪声信号标准偏差为1.53×10-5V,经FIR数字低通滤波后的噪声信号标准偏差降低为5.4×10-6V,加速度计的分辨率由126μg提高到42μg。     

Non linear response and optimization of a new z-axis resonant micro-accelerometer

Micro-Electro-Mechanical Systems (MEMS) accelerometers are micro-sized devices largely used for detecting accelerations in the consumer and automotive market. Both capacitive and resonant sensing have been successfully employed in these devices.In the present work, the focus is on a z-axis resonant accelerometer recently proposed in [1] and fabricated with the Thelma^© surface-micromachining technique developed by STMicroelectronics [2].After a full non-linear dynamic study, two possible optimized designs are studied through an optimization procedure. The goal of the work is to find a novel design for the z-axis resonant accelerometer which meets the linearity and the reliability requirements for MEMS accelerometers whitout losses in terms of sensitivity.     

Analysis and design of amplifiers and comparators in CMOS 0.35 μm technology

Design techniques and CAD tools for digital systems are advancing rapidly at decreasing cost, while CMOS analog circuit design is related mostly with the individual experience and background of the designer. Therefore, the design of an analog circuit depends on several factors such as a reliable design methodology, good modeling and technology characterization. Most of this work focuses on the analysis of several analog circuits, including their functionality, using different design methodologies. Initially the determination of two key design parameters (slope factor n and early voltage VA) and the g_m/I_D characteristics were derived from simulations. Then, the analysis and design of three diferent analog circuits are presented. A comparison is made between two design methodology applied to an analog amplifier design. The first one is a conventional approach where transistors are in saturation. The second one is based on the g_m/I_D characteristic, that allows a unified synthesis methodology in all regions of operation of the transistor. The analog modules for comparison and continuous filtering, that find vast applications today, are then analyzed and designed with the parameters and methodology proposed.     

Improvement in the Durability and Heat Conduction of uni-leg Thermoelectric Modules Using n-type Mg2Si Legs

We have fabricated several kinds of uni-leg thermoelectric (TE) modules using Sb-doped n-type Mg₂Si. In order to evaluate the influence of the structure of the modules on their durability with respect to heat-cycling, modules of two different types were evaluated. One was a conventional-structured module, in which the upper and lower surfaces of the legs were each fixed to a ceramic substrate. The other was a ‘half skeleton’ module, in which the ‘cold-side’ substrate was removed and a thermal-conductive sheet was used instead of a ceramic plate for the cold-side insulator. From the result of this evaluation, it was confirmed that, although some variation in the output power was observed for the ‘half-skeleton’ module, the power variation was markedly less than for the conventional-structured module. Additionally, to improve the output power of the module, we replaced the Al₂O₃ substrate with Si₃N₄, which has a higher thermal conductivity than the Al₂O₃ substrate. The observed output power of a module (25 mm × 24 mm × 8.3 mm) fabricated using the Si₃N₄ substrate was 1,293 mW at ΔT = 500 K. The output value of the module using the Si₃N₄ plate was improved by 29 % compared with the output value of the module using the Al₂O₃ substrate. Moreover, based on the structures of these modules, a 36 mm × 41 mm × 8.3 mm module was fabricated. The expected value of the output power of the module was 1.9 W at ΔT = 500 K.     

A high-precision spread spectrum clock generator based on a fractional-N phase locked loop

A low jitter Spread Spectrum Clock Generator (SSCG) based on a fractional-N Phase Locked Loop (PLL) capable of generating various Electromagnetic Interference (EMI) reduction levels is proposed. A digital compensation filter is fully integrated in the design to prevent various triangular modulation profiles from being distorted by the prohibitively small PLL loop bandwidth. A simple but comprehensive logic design included in the digital filter provides independently controllable modulation frequency, f _m, and modulation ratio, δ_m within all modulation modes (up, down, center). The proposed SSCG is designed in a 0.18 μm CMOS standard cell library and operates at 72 MHz with f _m ranging from 58 to 112.5 kHz and δ_m ranging from 0.75 to 2 %.