A novel nanoscaled device concept: quasi-SOI MOSFET to eliminate the potential weaknesses of UTB SOI MOSFET

For the first time, a novel device concept of a quasi-silicon-on-insulator (SOI) MOSFET is proposed to eliminate the potential weaknesses of ultrathin body (UTB) SOI MOSFET for CMOS scaling toward the 35-nm gate length, and beyond. A scheme for fabrication of a quasi-SOI MOSFET is presented. The key characteristics of quasi-SOI are investigated by an extensive simulation study comparing them with UTB SOI MOSFET. The short-channel effects can be effectively suppressed by the insulator surrounding the source/drain regions, and the suppression capability can be even better than the UTB SOI MOSFET, due to the reduction of the electric flux in the buried layer. The self-heating effect, speed performance, and electronic characteristics of quasi-SOI MOSFET with the physical channel length of 35 nm are comprehensively studied. When compared to the UTB SOI MOSFET, the proposed device structure has better scaling capability. Finally, the design guideline and the optimal regions of quasi-SOI MOSFET are discussed.     

A new symmetrical double gate nanoscale MOSFET with asymmetrical side gates for electrically induced source/drain

In this paper, we present the unique features exhibited by a novel double gate MOSFET in which the front gate consists of two side gates as an extension of the source/drain. The asymmetrical side gates are used to induce extremely shallow source/drain regions on either side of the main gate. Using two-dimensional and two-carrier device simulation, we have investigated the improvement in device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing and the hot carrier effect. Based on our simulation results, we demonstrate that the proposed symmetrical double gate SOI MOSFET with asymmetrical side gates for the induced source/drain is far superior in terms of controlling the short-channel effects when compared to the conventional symmetrical double gate SOI MOSFET. We show that when the side gate length is equal to the main gate length, the device can be operated in an optimal condition in terms of threshold voltage roll-off and hot carrier effect. We further show that in the proposed structure the threshold voltage of the device is nearly independent of the side gate bias variation.     

Scaling fully depleted SOI CMOS

Quasi-two-dimensional (2-D) device analyses, 2-D numerical device simulations, and circuit simulations of nanoscale conventional, single-gate fully depleted (FD) silicon-on-insulator (SOI) CMOS are done to examine the scalability and performance potential of the technology. The quasi-2-D analyses, which can apply to double-gate devices as well, also provide a simple expression to estimate the effective channel length (L/sub eff/) of FD/SOI MOSFETs. The insightful results show that threshold-voltage control via channel doping and polysilicon gates is not a viable option for extremely scaled FD/SOI CMOS, and hence that undoped channels and metal gate(s) with tuned work function(s) must be employed. Quantitative as well as qualitative insights gained on the short-channel effects reveal the need for ultrathin films (t/sub Si/ < 10 nm) for L/sub eff/ < 50 nm. However, the implied manufacturing burden, compounded by effects of carrier-energy quantization for ultrathin t/sub Si/, forces a pragmatic limit on t/sub Si/ of about 5 nm, which in turn limits the scalability to L/sub eff/ = 25-30 nm. Unloaded CMOS-inverter ring-oscillator simulations, done with our process/physics-based compact model (UFDG) in SPICE3, show very good performance for L/sub eff/ = 35 nm, and suggest viable technology designs for low-power as well as high-performance applications. These simulations also reveal that moderate variations in t/sub Si/ can be tolerated, and that the energy quantization significantly influences the scaled-technology performance and hence must be properly accounted for in optimal FD/SOI MOSFET design.     

Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layers

A comparison of dc characteristics of fully depleted double-gate (DG) MOSFETs with respect to low-power circuit applications and device scaling has been performed by two-dimensional device simulation. Three different DG MOSFET structures including a conventional N⁺ polysilicon gate device with highly doped Si layer, an asymmetrical P⁺/N⁺ polysilicon gate device with low doped Si layer and a mid-gap metal gate device with low doped Si layer have been analysed. It was found that DG MOSFET with mid-gap metal gates yields the best dc parameters for given off-state drain leakage current and highest immunity to the variation of technology parameters (gate length, gate oxide thickness and Si layer thickness). It is also found that an asymmetrical P⁺/N⁺ polysilicon gate DG MOSFET design offers comparable dc characteristics, but better parameter immunity to technology tolerances than a conventional DG MOSFET.     

Scaling planar silicon devices

The generation-over-generation scaling of critical CMOS technology parameters is ultimately bound by nonscalable limitations, such as the thermal voltage and the elementary electronic charge. Sustained improvement in performance and density has required the introduction of new device structures and materials. Partially depleted SOI, a most recent MOSFET innovation, has extended VLSI performance while introducing unique idiosyncrasies. Fully depleted SOI is one logical extension of this device design direction. Gate dielectric tunneling, device self-heating, and single-event upsets present developers of these next-generation devices with new challenges. Strained silicon and high-permittivity gate dielectric are examples of new materials that will enable CMOS developers to continue to deliver device performance enhancements in the sub-100 nm regime.     

Sub-50 nm P-channel FinFET

High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-aligned to each other and to the source/drain (S/D) regions; 3) raised S/D regions; and 4) a short (50 nm) Si fin to maintain quasi-planar topology for ease of fabrication. The 45-nm gate-length p-channel FinFET showed an I_dsat of 820 μA/μm at V_ds=V_gs=1.2 V and T _ox=2.5 mm. Devices showed good performance down to a gate-length of 18 nm. Excellent short-channel behavior was observed. The fin thickness (corresponding to twice the body thickness) is found to be critical for suppressing the short-channel effects. Simulations indicate that the FinFET structure can work down to 10 nm gate length. Thus, the FinFET is a very promising structure for scaling CMOS beyond 50 nm     

Characterization of double gate MOSFETs fabricated by a simple method on a recrystallized silicon film

A simple process to fabricate double gate SOI MOSFET is proposed. The new device structure utilizes the bulk diffusion layer as the bottom gate. The active silicon film is formed by recrystallized amorphous silicon film using metal-induced-lateral-crystallization (MILC). While the active silicon film is not truly single crystal, the material and device characteristics show that the film is equivalent to single crystal SOI film with high defect density, like SOI wafers produced in early days. The fabricated double gate MOSFETs are characterized, which demonstrate excellent device characteristics with higher current drive and stronger immunity to short channel effects compared to the single gate devices.     

Full-band Monte Carlo investigation of hot carrier trends in thescaling of metal-oxide-semiconductor field-effect transistors

A full-band Monte Carlo (MC) device simulator has been used to study the effects of device scaling on hot electrons in different types of n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) structures. Simulated devices include a conventional MOSFET with a single source/drain implant, a lightly-doped drain (LDD) MOSFET, a silicon-on-insulator (SOI) MOSFET, and a MOSFET built on an epitaxial layer on top of a heavily-doped ground plane. Different scaling techniques have been applied to the devices, to analyze the effects on the electric field and on the energy distributions of the electrons, as well as on drain, substrate, and gate currents. The results provide a physical basis for understanding the overall behavior of impact ionization and gate oxide injection and how they relate to scaling. The observed nonlocality of transport phenomena and the nontrivial relationship between electric fields and transport parameters indicate that simpler models cannot adequately predict hot carrier behavior at the channel lengths studied (sub-0.3-μm). In addition, our results suggest that below 0.15 μm, the established device configurations (e.g. LDD) that are successful at suppressing the hot carrier population for longer channel lengths, become less useful and their cost-effectiveness for future circuit applications needs to be reevaluated     

部分耗尽SOI MOSFETs中沟道的非对称掺杂效应

利用二维模拟软件对部分耗尽SoI器件中的非对称掺杂沟道效应进行了模拟.详细地研究了该结构器件的电学性能,如输出特性,击穿特性.通过本文模拟发现部分耗尽SOI非对称掺杂沟道相比传统的部分耗尽SOI,能抑制浮体效应,改善器件的击穿特性.同时跟已有的全耗尽SOI非对称掺杂器件相比,部分耗尽器件性能随参数变化,在工业应用上具有可预见性和可操作性.因为全耗尽器件具有非常薄的硅膜,而这将引起如前栅极跟背栅极的耦合效应和热电子退化等寄生效应.     

Full quantum simulation study of a nano tri-material double gate silicon-on-insulator MOSFET

We present 2D full quantum simulation based on the self-consistent solution of 2D Poisson–Schrödinger equations, within the nonequilibrium Green’s function formalism, for a novel multiple region silicon-on-insulator (SOI) MOSFET device architecture – tri-material double gate (TMDG) SOI MOSFET. This new structure has three materials with different work functions in the front gate, which show reduced short-channel effects such as the drain-induced barrier lowering and subthreshold swing, because of a step function of the potential in the channel region that ensures the screening of the drain potential variation by the gate near the drain. Also, the quantum simulations show the new structure significantly decreases leakage current and drain conductance and increases on–off current ratio and voltage gain as compared to conventional and dual material DG SOI MOSFET.     

Impact of Device Architecture on Performance and Reliability of Deep Submicron SOI MOSFETs (invited paper)

The main electrical properties of advanced Silicon-On-Insulator MOSFETs are addressed. The subthreshold and high field operations are analysed as a function of device architecture. The special SOI parasitic phenomena, such as the floating body potential and temperature, are critically reviewed. The main limitations of submicron MOSFET are comparatively evaluated for various SOI structures. Short channel and hot carrier effects as well as the reliability of the SOI technology are investigated for gate length down to sub-0. 1 micron.     

Impact of Device Architecture on Performance and Reliability of Deep Submicron SOI MOSFETs (invited paper)

A number of advantages,suitable for many applications,are obtained with the SOIstructure which allows to push back the technological and physical limits intrinsic to thebulk Si structure[1 ,2 ,3] :-the latch-up,a parasitic n-p-n-p str...     

High performance fully-depleted tri-gate CMOS transistors

Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5 - 2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools. Comparing tri-gate transistors to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. Furthermore, three-dimensional (3-D) simulations of tri-gate transistors with transistor gate lengths down to 30 nm show that the 30 nm tri-gate device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri-gate transistor could pose a viable alternative to bulk transistors in the near future.     

Quantum simulations of an ultrashort channel single-gated n-MOSFETon SOI

We present quantum mechanical simulations of a single-gated ultrashort channel MOSFET on silicon-on-insulator (SOI). Ballistic transport is assumed, in order to investigate ideal device performance. In particular, the electrical characteristics and the dependence on the SOI body thickness variation and doping of source and drain is elaborated. The results show that excellent performance can be achieved for devices with channel lengths down to 15 nm for a single-gated device layout. The influence of the SOI-film roughness is investigated with an SOI body thickness down to 2.5 nm. Extremely high transconductances far in excess of today's state-of-the-art devices can be expected if the doping level in source and drain is chosen appropriately. We give the relevant design rules for the fabrication of such devices     

Undoped-Body Extremely Thin SOI MOSFETs With Back Gates

We present a detailed study of gate length scalability and device performance of undoped-body extremely thin silicon-on-insulator (ETSOI) MOSFETs with back gates. We show that short channel control improves with the application of back bias via a decrease in the electrostatic scaling length as the subthreshold charges move toward the front gate. We demonstrate that, even for undoped ETSOI devices with ~8-nm SOI thickness, the improvement in short channel control with the application of a back bias translates to 10% higher drive current, 10% shorter gate lengths, and, consequently, 20% lower extrinsic gate delay at a fixed off-state current of 100 nA/mum and a back oxide electric field of 1.5 MV/cm (0.5 MV/cm SOI field).     

The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and Its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks

This paper provides evidence that, as a result of constant-field scaling, the peak$f_T$(approx. 0.3$hbox mA/muhbox m$), peak$f_ MAX$(approx. 0.2$hbox mA/muhbox m$), and optimum noise figure$ NF_ MIN$(approx. 0.15$hbox mA/muhbox m$) current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries. It is demonstrated that the characteristic current densities also remain invariant for the most common circuit topologies such as MOSFET cascodes, MOS-SiGe HBT cascodes, current-mode logic (CML) gates, and nMOS transimpedance amplifiers (TIAs) with active pMOSFET loads. As a consequence, it is proposed that constant current-density biasing schemes be applied to MOSFET analog/mixed-signal/RF and high-speed digital circuit design. This will alleviate the problem of ever-diminishing effective gate voltages as CMOS is scaled below 90 nm, and will reduce the impact of statistical process variation, temperature and bias current variation on circuit performance. The second half of the paper illustrates that constant current-density biasing allows for the porting of SiGe BiCMOS cascode operational amplifiers, low-noise CMOS TIAs, and MOS-CML and BiCMOS-CML logic gates and output drivers between technology nodes and foundries, and even from bulk CMOS to SOI processes, with little or no redesign. Examples are provided of several record-setting circuits such as: 1) SiGe BiCMOS operational amplifiers with up to 37-GHz unity gain bandwidth; 2) a 2.5-V SiGe BiCMOS high-speed logic chip set consisting of 49-GHz retimer, 40-GHz TIAs, 80-GHz output driver with pre-emphasis and output swing control; and 3) 1-V 90-nm bulk and SOI CMOS TIAs with over 26-GHz bandwidth, less than 8-dB noise figure and operating at data rates up to 38.8 Gb/s. Such building blocks are required for the next generation of low-power 40–80 Gb/s wireline transceivers.     

全耗尽异质栅单Halo SOI MOSFET二维模型

为了抑制深亚微米SOI MOSFET的短沟道效应,并提高电流驱动能力,提出了异质栅单Halo SOI MOSFET器件结构,其栅极由具有不同功函数的两种材料拼接而成,并在沟道源端一侧引入Halo技术.采用分区的抛物线电势近似法和通用边界条件求解二维Poisson方程,为新结构器件建立了全耗尽条件下的表面势及阈值电压二维解析模型.对新结构器件与常规SOI MOSFET性能进行了对比研究.结果表明,新结构器件能有效抑制阈值电压漂移、热载流子效应和漏致势垒降低效应,并显著提高载流子通过沟道的输运速度.解析模型与器件数值模拟软件MEDICI所得结果高度吻合.     

Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length

Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity,short channel effects (SCEs),leakage currents,device variability and reliability etc.Nowadays,multigate structure has become the promising candidate to overcome these problems.SOI FinFET is one of the best multigate structures that has gained importance in all electronic design automation (EDA) industries due to its improved short channel effects (SCEs),because of its more effective gate-controlling capabilities.In this paper,our aim is to explore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length.Electric field modulation is analyzed with spacer length variation and electrostatic performance is evaluated in terms of performance parameter like electron mobility,electric field,electric potential,sub-threshold slope (SS),ON current (Ion),OFF current (Ioff) and Ion/Ioff ratio.The potential benefits of SOI FinFET at drain-to-source voltage,VDS =0.05 V and VDS =0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain (Av),output conductance (gd),trans-conductance (gm),gate capacitance (Cgg),and cut-off frequency (fT =gm/2πCgg) with spacer region variations.     

Impact of the vertical SOI `DELTA' structure on planar devicetechnology

A fully depleted lean channel transistor (DELTA) with its gate incorporated into a new vertical ultrathin silicon-on-insulator (SOI) structure is presented. In the deep-submicrometer region, selective oxidation produces and isolates an ultrathin SOI MOSFET that has high crystalline quality, as good as that of conventional bulk single-crystal devices. Experiments and three-dimensional simulations have shown that this new gate structure has effective channel control and that the vertical ultrathin SOI structure provides superior device characteristics: reduction in short-channel effects, minimized subthreshold swing, and high transconductance     

Dynamic performance of graded channel DG FD SOI n-MOSFETs for minimizing the gate misalignment effect

Double gate MOSFET has been regarded as the most promising candidate for future CMOS devices, for excellent short channel effects (SCEs) immunity and high current drivability due to double gate coupling. The alignment between the top and bottom gates should be concern to fully realize the benefits of the double-gate configuration, as gate misalignment causes degradation in the device performance. Use of graded channel architectures somehow reduces the effect of gate misalignment. We scrutinize that how the misalignment affects the small signal behavior and device characteristics like conductances, capacitances and cut-off frequency, for uniformly doped and graded channel double gate architectures. Considering the fact that gate misalignment can occur on any side of the gate, extensive simulations have been carried out using high-low (H-L), low-high (L-H) and low-high-low (L-H-L) doping profiles for both source (DGS) and drain side (DGD) gate misalignment.