Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers

Various 16-bit multiplier architectures are compared in terms of dissipated energy, propagation delay, energy-delay product (EDP), and area occupation, in view of low-power low-voltage signal processing for low-frequency applications. A novel practical approach has been set up to investigate and graphically represent the mechanisms of glitch generation and propagation. It is found that spurious activity is a major cause of energy dissipation in multipliers. Measurements point out that, because of its shorter full-adder chains, the Wallace multiplier dissipates less energy than other traditional array multipliers (8.2 mu W/MHz versus 9.6 mu W/MHz for 0.18mum CMOS technology at 0.75 V). The benefits of transistor sizing are also evaluated (Wallace including minimum-size transistors dissipates 6.2 muW/MHz). By combining transmission gates with static CMOS in a Wallace architecture, a new approach is proposed to improve the energy-efficiency further (4.7 muW/MHz), beyond recently published low-power architectures. The innovation consists in suppressing glitches via resistance-capacitance low-pass filtering, while preserving unaltered driving capabilities. The reduced number of V _dd-to-ground paths also contributes to a significant decrease of static consumption.     

Low power FGMOS-based four-quadrant current multiplier circuits

In this paper, low-power, high-speed four-quadrant analog multiplier circuits have been presented, based on simple current squarer circuits. The squarer circuits consist of a floating-gate MOS transistor, operating in saturation region plus a resistor. These multipliers have a unique property of greatly reduced power as they do not have any bias currents. For performance evaluation, the designs are simulated using HSPICE software in 0.18 µm (level-49 parameters) TSMC CMOS technology. Using ± 0.5 V DC supply voltages for the first design, the simulation resulted in a maximum linearity error of 0.8%, the ? 3 dB bandwidth of 635 MHz, the Total Harmonic Distortion of 0.57% (at 1 MHz), and maximum and static power consumption of 40.4 and 5.75 µW, respectively. Corresponding values for the second design with 1 V DC supply voltage are 0.4%, 394.8 MHz, 0.72%, 44 and 11.4 µW, respectively. Furthermore, in order to verify the robustness and reliability of the proposed works, Monte Carlo analysis are performed. For the mentioned analysis, 5% variations in channel width and length, gate oxide thickness and threshold voltage of all transistors and resistance values are considered.     

Remotely powered PPM demodulator by inductive coupling for rodent applications

A low-power pulse position modulation (PPM) demodulator has been developed for remotely powered batteryless implantable devices. The required power for the implantable device is provided by the magnetic coupling with the external array of powering of coils placed under the living space of the animal. The remote powering is turned off 6 % of one bit duration during data transmission. The remote powering link is optimized to deliver power at 13.56 MHz frequency. The power is transferred from 30 mm distance with 21 % efficiency. An integrated full-wave rectifier and voltage regulator generate 1.8 V supply voltage from induced signal. The integrated PPM demodulator consumes only 27.8 µW and has 8.33 kb/s data rate. The presented entire system and basic blocks are integrated using a 0.18 µm CMOS technology. Experimental results verify the effectiveness of the PPM demodulator and the downlink communication system.     

A low-noise gain-tunable amplifier for large array biopotential recording systems

This paper presents a low-noise gain-tunable biopotential amplifier that is designed based on a folded-cascode structure. Sub-threshold and self-biasing techniques are employed to achieve a low-noise and low-power amplification. With a bias-current tuning block, the gain of the proposed biopotential amplifier can be precisely adjusted. Designed in a standard 0.13 μm CMOS process, the proposed amplifier provides a 5.9 kHz bandwidth and 30.1 dB gain with 732 nW power. The input-referred noise over the entire bandwidth is 4.3 μV _rms , equivalent to a noise-efficiency factor of 2.48.     

A 0.5-V low power analog front-end for heart-rate detector

This paper presents a low power analog front-end for heart-rate detector at a supply voltage of 0.5 V in 0.18 μm CMOS technology. A fully differential preamplifier is designed with a low power consumption of 300 nW. A 150 nW fourth order Switched-opamp switched capacitor bandpass filter is designed with passband 8–32 Hz. To digitize the analog signal, a low power second-order ΣΔ ADC is designed. The dynamic range and SNR of the converter are 46 dB and 54 dB respectively and it consumes a power of 125 nW. The overall front-end system including preamplifier, SO-SC bandpass filter, ΣΔ modulator and the biasing circuits are integrated and the total system consumes a power of 0.975 μW from 0.5 V supply.     

A low-power wide tuning-range CMOS current-controlled oscillator

This paper presents a low-power, small-size, wide tuning-range, and low supply voltage CMOS current-controlled oscillator (CCO) for current converter applications. The proposed oscillator is designed and fabricated in a standard 180-nm, single-poly, six-metal CMOS technology. Experimental results show that the oscillation frequency of the CCO is tunable from 30 Hz to 970 MHz by adjusting the control current in the range of 100 fA to 10 µA, giving an overall dynamic range of over 160 dB. The operation of the circuit is nearly independent of the power supply voltage and the circuit operates at supply voltages as low as 800 mV. Also, at this voltage, with control currents in the range of sub-nano-amperes, the power consumption is about 30 nW. These features are promising in sensory and biomedical applications. The chip area is only 8.8×11.5 µm².     

A low power sub-BGR with multi-curvature self-compensation

This paper proposes a low power sub bandgap reference (sub-BGR) with a novel multi-curvature self-compensation. The proposed circuit generates a curvature-compensation-less reference voltage (V_{REF_NC}), which is compared with the emitter–base voltage of a PNP transistor to generate a pair of complementary curvature currents. The curvature currents are used to compensate the temperature coefficient (TC) of the voltage V_{REF_NC} itself, resulting in a low-power and low-TC sub-BGR. The proposed circuit is implemented in a standard 65 nm complementary metal oxide semiconductor process. Simulation and measured results show the total power consumption is about 230 nW at the minimum supply voltage of 1.0 V. The power supply rejection ratio at low frequency is less than ?66 dB. After trimming, the average TC of 23 ppm/°C in the temperature range of ?45 to 125 °C and the accuracy of ± 0.15% (σ/µ) can be achieved.     

Novel detector implementations for 3G LTE downlink and uplink

We summarize our recent state-of-the-art programmable and reconfigurable detector and QR decomposition (QRD) implementations targeting 3G long term evolution (LTE) downlink and uplink requirements. The downlink transmission is based on the orthogonal frequency division multiplexing, whereas the uplink transmission uses a single-carrier frequency-division multiple access. The downlink implementations are based on the programmable transport triggered architecture (TTA) which provides a flexible and energy efficient architecture template. In TTA detector implementation, the LTE detection rate requirements up to 20 MHz bandwidth and 4 × 4 antenna system with 64-QAM, are achieved by using 1–6 programmable cores in parallel. Each core runs at 277 MHz clock frequency and consumes 55.5–64.0 mW depending on the detector configuration. The downlink detector is based on the selective spanning with fast enumeration algorithm. The uplink field-programmable gate array (FPGA) detector implementation is targeted for 4 × 4 antenna system and 64-QAM achieving a detection rate requirement for 20 MHz bandwidth. The used FPGA board for uplink implementation is Xilinx Virtex-6 and the implementation has been carried out using Xilinx Vivado high level synthesis tool. Two different detector architectures are implemented. The first one achieves the detection rate requirement with a single processing block running at 231 MHz and the latter one with four blocks in parallel, each running at 247 MHz. The implemented detector is based on the K-best algorithm. A multiple-input multiple-output receiver requires QRD to produce valid inputs for the detector. In addition to detector implementations, QRD is also implemented on both TTA and FPGA. Modified Gram–Schmidt algorithm is used in both QRD implementations.     

GaAs two-phase dynamic FET logic: a low-power logic family for VLSI

An extremely low-power, high-density GaAs logic family is described. Two-phase dynamic FET logic (TDFL) provides all the standard logic functions (NOT, NAND, NOR), and it operates from two nonoverlapping clocks and a single supply. TDFL gates are shown to operate above 750 MHz with an extremely low power dissipation of only 44 nW/MHz gate. TDFL is self-latching, lending itself to highly efficient pipelined architectures, and it is implemented with a standard enhancement/depletion (E/D)-mode MESFET foundry process. Finally, TDFL is directly compatible with static direct-coupled FET logic (DCFL), making its introduction into high-speed systems very straightforward     

Combination of DAC switches and SAR logics in a 720 MS/s low-bit successive approximation ADC

In this paper a 4-bit 720 MHz low-power successive approximation register ADC is simulated in a 0.18 µm digital CMOS process. By using both of the 2-bit/step and time-interleaved techniques, a high sampling frequency is obtained. To simplify the SAR ADC in low-bit applications, the analog switches are eliminated and replaced with inherent digital switches of SAR logics. The power supply, resolution, sampling frequency, SNDR, and power consumption of the proposed SAR ADC are 1.8 V, 4-bit, 720 MHz, 22.1 dB, and 10 mW.     

Design of quadruple precision multiplier architectures with SIMD single and double precision support

This paper proposes architectures for dual-mode and tri-mode dynamically configurable multiplier for quadruple precision arithmetic. The proposed dual-mode QPdDP multiplier architectures can either compute on a pair of quadruple precision (QP) operands or provide SIMD support for two-parallel (dual) sets of double precision (DP) operands. The proposed tri-mode QPdDPqSP multiplier architectures are aimed to include the four-parallel (quad) single precision (SP) along with dual-DP and a QP operand processing. For the underlying largest sub-component, the mantissa multiplier, two methods are analyzed to design the dual-mode/tri-mode architectures. One is based on the Karatsuba method, and in another a dual-mode/tri-mode Radix-4 Modified Booth (MB) multiplier is proposed. The proposed dual-mode/tri-mode MB multiplier requires few extra 2:1 MUXs as an overhead compared to a simple MB multiplier. To support dual-mode/tri-mode functioning other important sub-components of the FP multiplication are also re-designed for multi-mode support. The proposed architectures are synthesized using UMC 90 nm ASIC technology, and are compared against prior literature in terms of area, period, and a unified metric “Area (Gate Count) × Period (FO4) × Latency × Throughput (in cycles)”. The dual-mode/tri-mode FP architectures with MB mantissa multipliers shows better timings, however, those with Karatsuba mantissa multipliers acquires smaller area.     

A technique to improve the linearization of frequency–voltage characteristic of LC-VCO

This paper presents a very low-power linearization technique to improve the linearity of frequency-voltage characteristic of LC-VCO (voltage controlled oscillator) using MOS varactor. This reduces the VCO gain (K _VCO) variation and its required value over the tuning voltage range. Low K _VCO improves noise and reference spur performances at the output of phase lock loop/frequency synthesizer (FS). Low K _VCO variation reduces FS loop stability problem. Using this VCO circuit, a fully on-chip integer-N frequency synthesizer has been fabricated in 0.18 μm epi-digital CMOS technology for 2.45 GHz ZigBee application. The measured VCO phase noise is ?115.76 and ?125.23 dBc/Hz at 1 and 3 MHz offset frequencies, respectively from 2.445 GHz carrier and the reference spur of the frequency synthesizer is ?68.62 dBc. The used supply voltage is 1.5 V.     

A novel MPPT circuit with 99.1% tracking accuracy for energy harvesting

A novel maximum power point tracking (MPPT) circuit based on Buck–Boost converter is presented for micro-power energy harvesting, which efficiently improves the power efficiency and robustness of system. The proposed MPPT uses the low-power analog multiplier and multi-outputs self-powered common-gate comparator to track the input power, and simplifies data calculation and structure greatly. The fast dynamic switching circuit and digital control circuit are introduced to enhance the adaptability and flexibility of system. The performance of whole converter was validated by the simulation results in a 65-nm CMOS process. The minimum starting voltage is 0.15 V. The peak output power is 40.5 µW, with a power loss of 14.1 µW. The peak power efficiency and peak tracking efficiency are 92.1 and 99.1%, respectively. The proposed MPPT has the advantages such as low power, high efficiency, fast tracking speed, simple structure.     

Design,Modeling, Fabrication,and Evaluation of Thermoelectric Generators with Hot-Wire Chemical Vapor Deposited Polysilicon as Thermoelement Material

This paper presents the design, modeling, fabrication, and evaluation of thermoelectric generators (TEGs) with p-type polysilicon deposited by hot-wire chemical vapor deposition (HWCVD) as thermoelement material. A thermal model is developed based on energy balance and heat transfer equations using lumped thermal conductances. Several test structures were fabricated to allow characterization of the boron-doped polysilicon material deposited by HWCVD. The film was found to be electrically active without any post-deposition annealing. Based on the tests performed on the test structures, it is determined that the Seebeck coefficient, thermal conductivity, and electrical resistivity of the HWCVD polysilicon are 113 μV/K, 126 W/mK, and 3.58 × 10^?5 Ω m, respectively. Results from laser tests performed on the fabricated TEG are in good agreement with the thermal model. The temperature values derived from the thermal model are within 2.8% of the measured temperature values. For a 1-W laser input, an open-circuit voltage and output power of 247 mV and 347 nW, respectively, were generated. This translates to a temperature difference of 63°C across the thermoelements. This paper demonstrates that HWCVD, which is a cost-effective way of producing solar cells, can also be applied in the production of TEGs. By establishing that HWCVD polysilicon can be an effective thermoelectric material, further work on developing photovoltaic-thermoelectric (PV-TE) hybrid microsystems that are cost-effective and better performing can be explored.     

Low-Power Constant-Coefficient Multiplier Generator

Constant-coefficient multipliers are used in many DSP cores. A new low-power constant multiplier, with detailed design procedure, is presented. By using canonical sign-digit (CSD) number system, and introducing new simplification techniques and identities, the multiplier features a new algorithm to reduce logic depth for the Wallace-tree implementation. The method also reduces area and complexity.A generator written in C++ is used to generate technology-independent VHDL code of the constant multiplier for different input specifications. Synthesis results indicate the new design has smaller area and less power consumption while offering similar speed performance when compared with other multipliers.     

A very compact, 0.4 V DTMOS CCII employed in an audio-frequency filter

This paper presents an ultra low-voltage, ultra low-power, very compact, dynamic threshold voltage MOS transistor (DTMOS)-based CCII circuit. The proposed circuit is capable of operating under ± 0.2 V symmetric supply voltages. The circuit topology is very compact and consists of only four DTMOS transistors and four ordinary NMOS transistors. The total power consumption of the circuit is found as only 214 nW while all transistors are working in the subthreshold region. The current conveyor has 570 kHz 3 dB-bandwidth from X to Y terminal for the voltage gain and has low, 0.2 % following error between these terminals for inputs not exceeding ± 60 mV. TSMC 0.18 µm process technology parameters are used in the design of the proposed CCII block which is then employed in an audio-frequency, second-order, band-pass filter configuration where real speech signals are fed to the input of the filter to further investigate its characteristics. Close agreement is found between theoretical study and simulated responses.     

A WiSN node SoC with real-time image compressor and IEEE 802.15.4 MAC accelerator

This article presents a wireless image sensor node SoC (system-on-a-chip) for low-power wireless image sensor network (WiSN), in which camera chip interface, high-quality image compression and IEEE 802.15.4 compliant acceleration modules are integrated on chip. The proposed SoC contains a hardware-implemented real-time lossless JPEG (JPEG-LS) compression engine for Bayer Color Filter Arrays (Bayer CFA), reaching a 3.5 bits/pixel with peak signal to noise ratio (PSNR) greater than 46.3 dB and achieving a maximum 5 frames/s @16 MHz for VGA (640 × 480) colour images. The proposed hardware accelerator for IEEE 802.15.4 media access control (MAC) layer covers crucial protocol defined functions and algorithms, and reduces 45% software code in the host processor. This SoC has been fabricated in UMC 0.18 µm 1P6M CMOS process. The average power of the prototype chip is 18.2 mW at 3.0 V power supply and 16 MHz clock rate.     

A fast-settling charge-pump PLL with constant loop bandwidth

A fully integrated fast-settling Fractional-N phase-locked loop (PLL) is presented. Based on the \(\Delta \varSigma\) modulator and I/Q generator architectures, the frequency synthesizer covers a frequency range of 130 MHz-1 GHz with a 3-KHz channel step. The constant loop bandwidth over the above tuning frequency ranges is achieved without modifying low pass filter parameters. The current of charge pump \(Icp\) is programmed not only to compensate the variation of voltage-controlled oscillator gain \(Kvco\), but also for adapting to the change of divider ratio \(N_{m}\). This calibration process is carried out in an open-loop condition for a small settling time. The proposed synthesizer was fabricated in 0.18 µm CMOS process. The measurement results show that the whole synthesizer PLL draws 11.3-mA including I/Q generator from 1.8 V supply. The out-of-band phase noise is ? 123 dBc/Hz@10 MHz with a 433 MHz carrier frequency after the divider. The normalized \(\left( {Icp*Kvco} \right)/N_{m}\) which is equivalent to the variation of PLL loop bandwidth ranges from ? 6 to 6%.     

Waveguide InGaAsP/InP photodetectors for low-power autocorrelation measurements at 1.55 µm

Two-photon absorption of 1.55 μm light in quantum-well InGaAs/InP laser heterostructures has been studied. The highest achieved nonlinear response was 0.78 nA/mW². The minimum detectable peak power of 60 μW allows for the effective use of waveguides of this type as detectors in optical autocorrelators for studying temporal characteristics of low-power signals. __________ Translated from Fizika i Tekhnika Poluprovodnikov, Vol. 36, No. 6, 2002, pp. 754–756. Original Russian Text Copyright ? 2002 by Gordeev, Karachinsky, Novikov, Lyutetsky, Pikhtin, Fetisova, Tarasov, Kop’ev.     

A low power 10-bit CMOS cyclic D/A converter with an improved Johnson counter and a capacitor swapping technique

A 10-bit CMOS cyclic D/A converter based on an improved Johnson counter and a capacitor swapping technique is described. In order to reduce the capacitor mismatching errors, we propose that two capacitors are alternately swapped depending on the input data. Further, a half differential architecture to reduce offset errors and an improved Johnson counter are also discussed. With a 0.35 µm Samsung CMOS technology, the measured SFDR is about 65 dB, when the input frequency is 1 MHz at a clock frequency of 2 MHz. The power consumption is only 240 µW at 3.3 V power supply. The measured INL and DNL are within ±0.7 and ±0.7 LSB, respectively.