Dependence of Threshold Voltage of a-Si:H TFT on a-SiNx:H Film^①

The relation between threshold voltage for hydrogenated amorphous silicon thin film transistors(a-Si:HTFTs)and deposition conditions for hydrogenated amorphous silicon nitride(a-SiNx:H)films is investigated.It is observed that the threshold voltage,Vth,of a-Si:HTFT increases with the increase of the thickness of a-SiNx:H film,and the threshold voltage is reduced apparently with the increase of NH3/SiH4 gas flow rate ratio.     

Dependence of Threshold Voltage of a-Si:H TFT on a-SiN_x:H Film

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Silicon matrix disorder in amorphous hydrogenated silicon alloys

The authors report a detailed investigation of correlations between Urbach energies from photothermal deflection spectroscopy and Raman half-widths of transverse optic (TO)-like Si-Si modes as a measure of silicon matrix disorder in glow-discharge amorphous hydrogenated silicon (a-Si:H) and a-SiGe:H, as well as in glow-discharge and sputtered a-SiC:H and a-SiN:H. A corresponding decrease in TO full width at half-maximum (FWHM) and Urbach energy E₀ for soft deposition techniques yields bond angle distributions as narrow as 8.5° for the best a-Si:H films. Even at the lowest levels of nitrogen incorporation, simultaneous increases in E₀ and TO-like half-widths indicate that lattice distortions occur due to threefold coordination of nitrogen in the a-Si:H matrix. In contrast, no deviation of silicon TO-FWHM could be detected in a-SiC:H of up to 35 at.% of carbon content, whereas Urbach edges broaden in a well-known manner that is interpreted in terms of -CH₃ incorporation into the amorphous network. Diborane doping and sputter deposition, however, give rise to lattice distortions in a-SiC:H, which reflects changes in the carbon coordination     

Hydrogenated amorphous silicon thin film transistor fabricated onplasma treated silicon nitride

We have demonstrated that the performance of the inverted staggered, hydrogenated amorphous silicon thin film transistor (a-Si:H TFT) is improved by a He, H₂, NH₃ or N₂ plasma treatment for a short time on the surface of silicon nitride (SiN _x) before a-Si:H deposition. With increasing plasma exposure time, the field-effect mobility increase at first and then decrease, but the threshold voltage changes little. The a-Si:H TFT with a 6-min N₂ plasma treatment on SiN_x exhibited a field effect mobility of 1.37 cm²/Vs, a threshold voltage of 4.2 V and a subthreshold slope of 0.34 V/dec. It is found that surface roughness of SiN_x is decreased and N concentration in the SiN _x at the surface region decreases using the plasma treatment     

Hydrogen dilution effect on the properties of coplanar amorphoussilicon thin-film transistors fabricated by inductively-coupled plasmaCVD

The electrical and optical properties of the hydrogenated amorphous silicon (a-Si:H) films deposited by inductively-coupled plasma (ICP) chemical vapor deposition (CVD) with a variation of H₂ flow rate have been studied. The photosensitivity of a-Si:H is ~10⁷ when the H₂/SiH₄ ratio is between 3 and 8. With increasing H₂/SiH₄, the SiH₂ mode infrared absorption has a minimum at a H₂/SiH₄ ratio of 8. Coplanar a-Si:H thin-film transistors (TFT's) were fabricated using a triple layer of thin a-Si:H, silicon-nitride, and a-Si:H deposited by ICP-CVD using ion doping and low resistivity Ni silicide. After patterning the thin a-Si:H/silicon-nitride layers on the channel region, the gate and source/drain regions were ion-doped and then heated at 230°C to form Ni silicide layers. The low resistive Ni silicide formed on the a-Si:H reduces the offset length between gate and source/drain, leads to a coplanar a-Si:H TFT. The TFT exhibited a field effect mobility of 0.6 cm²/Vs and a threshold voltage of 2.3 V at the H₂/SiH₄ ratio of 8. The effect of H₂ dilution in SiH₄ on the coplanar a-Si:H TFT performance has been investigated. We found that the performance of the TFT is the best when the SiH₂ mode density in a-Si:H is the minimum. The coplanar TFT is very suitable for large-area, high density TFT displays because of its low parasitic capacitance between gate and source/drain contacts     

High field-effect-mobility a-Si:H TFT based on high deposition-ratePECVD materials

The hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFT's) having a field-effect mobility of 1.45 ±0.05 cm² /V·s and threshold voltage of 2.0±0.2 V have been fabricated from the high deposition-rate plasma-enhanced chemical vapor deposited (PECVD) materials. For this TFT, the deposition rates of a-Si:H and N-rich hydrogenated amorphous silicon nitride (a-SiN_1.5 :H) are about 50 and 190 nm/min, respectively. The TFT has a very high ON/OFF-current ratio (of more than 10⁷), sharp subthreshold slope (0.3±0.03 V/decade), and very low source-drain current activation energy (50±5 meV). All these parameters are consistent with a high mobility value obtained for our a-Si:H TFT structures. To our best knowledge, this is the highest field-effect mobility ever reported for an a-Si:H TFT fabricated from high deposition-rate PECVD materials     

High field effect mobility deuterated amorphous silicon thin-filmtransistors based on the substitution of hydrogen with deuterium

The characteristics of amorphous silicon hydrogen and deuterium thin-film transistors (a-Si:H/a-Si:D TFT) were studied. The deuterated and hydrogenated amorphous silicon channels were prepared by first annealing the as-deposited a-Si:H layer at 550°C in N₂ environment to expel all the hydrogen atoms out of the films, then the D ₂ or H₂ plasma were applied to treat the amorphous silicon layers. The field effect mobility of the conventional hydrogen TFT is usually smaller than 1 cm²/V-s. It was found that substitution of hydrogen with deuterium improved the field effect mobility of the TFT. The maximum field effect mobility of a-Si:D TFT obtained from the saturation region was 1.77 cm²/V-s     

铝膜沉积温度对铝诱导结晶化多晶硅薄膜性能的影响

以超白玻璃为衬底,采用热丝化学气相沉积法沉积初始非晶硅膜,经自然氧化形成二氧化硅层,最后利用磁控溅射 法在不同衬底温度下沉积铝膜,制备了glass/Si/SiO/Al叠层结构并对其进行铝诱导晶化形成多晶硅薄膜.用X射线衍射,光学显微镜和拉曼光谱对样品进行了分析.结果表明,铝诱导晶化制备的多晶硅薄膜的晶粒大小随着铝膜沉积...     

High mobility tri-layer a-Si:H thin-film transistors with ultrathinactive layer

We show that hydrogenated amorphous silicon thin-film transistors (a-Si:H TFT's) with active layer thickness of 13 nm perform better for display applications than devices with thicker 50-nm active layers. A direct comparison of a-Si:H TFT's fabricated using an i-stopper TFT structure shows that ultrathin active layers significantly improve the device characteristics. For a 5-μm channel length TFT, the linear region (V_DS=0.1 V) and saturation region mobilities increase from 0.4 cm²/V·s and 0.7 cm²/V·s for a 50-nm thick active layer a-Si:H device to 0.7 cm²/V·s and 1.2 cm²/V·s for a 13-nm thick active layer a-Si:H layer device fabricated with otherwise identical geometry and processing     

Amorphous silicon thin-film transistor with fluorinated siliconoxide ion stopper

We propose fluorinated silicon oxide (SiOF) as the ion-stopper of bottom-gate amorphous silicon thin film transistors (a-Si:H TFTs). The low dielectric constant SiOF on both the back-channel of the TFT and the crossover regions of gate/data lines can contribute to reducing the RC delay of the gate pulse signal in active-matrix liquid-crystal displays. Besides, the a-Si:H TFT with a SiOF stopper shows an improved performance compared to the widely-employed silicon nitride (SiN_x ) stopper TFT, because the fluorine incorporation reduces the interface state density between a-Si:H and SiOF     

Inverse staggered poly-Si and amorphous Si double structure TFT'sfor LCD panels with peripheral driver circuits integration

Inverse staggered polycrystalline silicon (poly-Si) and hydrogenated amorphous silicon (a-Si:H) double structure thin-film transistors (TFT's) are fabricated based on the conventional a-Si:H TFT process on a single glass substrate. After depositing a thin (20 nm) a-Si:H using the plasma CVD technique at 300°C, Ar⁺ and XeCl (300 mJ/cm²) lasers are irradiated successively, and then a thick a-Si:H (200 nm) and n⁺ Si layers are deposited again. The field effect mobilities of 10 and 0.5 cm ²/V·s are obtained for the laser annealed poly-Si and the a-Si:H (without annealing) TFT's, respectively     

Self-heating and kink effects in a-Si:H thin film transistors

We describe a new physics based, analytical DC model accounting for short channel effects for hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFT's). This model is based on the long channel device model. Two important short-channel phenomena, self-heating and kink effects, are analyzed in detail. For the self-heating effect, a thermal kinetic analysis is carried out and a physical model and an equivalent circuit are used to estimate the thermal resistance of the device. In deriving the analytical model for self-heating effect, a first order approximation and self-consistency are used to give an iteration-free model accurate for a temperature rise of up to 100°C. In the modeling of the kink effects, a semi-empirical approach is used based on the physics involved. The combined model accurately reproduces the DC characteristics of a-Si:H TFT's with a gate length of the 4 μm. Predictions for a-Si:H TFT's scaled down to 1 μm are also provided. The model is suitable for use in device and circuit simulators     

The effects of hydrogen on aluminum-induced crystallization of sputtered hydrogenated amorphous silicon

The effects of hydrogen on aluminum-induced crystallization (AIC) of sputtered hydrogenated amorphous silicon (a-Si:H) were investigated by controlling the hydrogen content of a-SiH films. Nonhydrogenated (a-Si) and hydrogenated (a-Si:H) samples were deposited by sputtering and plasma-enhanced chemical vapor deposition (PECVD). All aluminum films were deposited by sputtering. Hydrogen was introduced into the sputter-deposited a-Si films during the deposition. After deposition, the samples were annealed at temperatures from 200°C to 400°C for different periods of time. X-ray diffraction (XRD) patterns were used to confirm the presence and degree of crystallization in the a-Si:H films. For nonhydrogenated films, crystallization initiates at a temperature of 350°C. The crystallization of sputter-deposited a-Si:H initiates at 225°C when 14% hydrogen is present in the film. As the hydrogen content is decreased, the crystallization temperature increases. On the other hand, the crystallization initiation temperature for PECVD a-Si:H containing 11at.%H is 200°C. Further study revealed that the crystallization initiation temperature is a function, not only of the total atomic percent hydrogen in the film, but also a function of the way in which the hydrogen is bonded in the film. Models are developed for crystallization initiation temperature dependence on hydrogen concentration in a-Si:H thin films.     

Low-Temperature Materials and Thin Film Transistors for Flexible Electronics

This paper addresses the low-temperature deposition processes and electronic properties of silicon based thin film semiconductors and dielectrics to enable the fabrication of mechanically flexible electronic devices on plastic substrates. Device quality amorphous hydrogenated silicon (a-Si:H), nanocrystalline silicon (nc-Si), and amorphous silicon nitride (a-SiN/sub x/) films and thin film transistors (TFTs) were made using existing industrial plasma deposition equipment at the process temperatures as low as 75/spl deg/C and 120/spl deg/C. The a-Si:H TFTs fabricated at 120/spl deg/C demonstrate performance similar to their high-temperature counterparts, including the field effect mobility (/spl mu//sub FE/) of 0.8 cm/sup 2/V/sup -1/s/sup -1/, the threshold voltage (V/sub T/) of 4.5 V, and the subthreshold slope of 0.5 V/dec, and can be used in active matrix (AM) displays including organic light emitting diode (OLED) displays. The a-Si:H TFTs fabricated at 75/spl deg/C exhibit /spl mu//sub FE/ of 0.6 cm/sup 2/V/sup -1/s/sup -1/, and V/sub T/ of 4 V. It is shown that further improvement in TFT performance can be achieved by using n/sup +/ nc-Si contact layers and plasma treatments of the interface between the gate dielectric and the channel layer. The results demonstrate that with appropriate process optimization, the large area thin film Si technology suits well the fabrication of electronic devices on low-cost plastic substrates.     

Electrophotographic patterning of thin-film silicon on glass foil

We report the patterning of thin films of amorphous silicon (a-Si:H) using electrophotographically applied toner as the etch mask. Using a conventional xerographic copier, a toner pattern was applied to 0.1 μm thick a-Si:H films deposited on ~50 μm thick glass foil. The toner then served as the etch mask for a-Si:H, and as the lift-off material for the patterning of chromium. This technique opens the prospect of roll-to-roll, high-throughput patterning of large-area thin-film circuits on glass substrates     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V     

Copper gate hydrogenated amorphous silicon TFT with thin bufferlayers

We demonstrated a Cu gate hydrogenated amorphous silicon thin-film transistor (TFT) with buffer layers. We introduced an AlN/Cu/Al₂ O₃ multilayer for a gate of an a-Si:H TFT. The Al₂ O₃ improves the adhesion to glass substrate and AlN protect the Cu diffusion to the TFT and plasma damage to Cu during plasma enhanced chemical vapor deposition of silicon-nitride. An a-Si:H TFT with a Cu gate exhibited a field effect mobility of 1.18 cm² V/s, a gate voltage swing of 0.87 V/dec., and a threshold voltage of 3.5 V     

A polycrystalline silicon thin-film transistor with a thinamorphous buffer

We have developed a novel, low off-state leakage current polycrystalline silicon (poly-Si) thin-film transistor (TFT) by introducing a very thin hydrogenated amorphous silicon (a-Si:H) buffer on the poly-Si active layer. The a-Si:H buffer is formed on the whole poly-Si and thus no additional mask step is needed. With an a-Si:H buffer on poly-Si, the off-state leakage current of a coplanar TFT is remarkably reduced, while the reduction of the on-state current is relatively small. The poly-Si TFT with an a-Si:H buffer exhibited a field effect mobility of 12 cm²/Vs and an off-state leakage current of 3 fA/μm at the drain voltage of 1 V and the gate voltage of -5 V     

Understanding the Effects of Stress on the Crystallization of Amorphous Silicon

This paper presents the results of a systematic study on the effects of stress on aluminum-induced crystallization (AIC) of plasma-enhanced chemical-vapor-deposited (PECVD) amorphous silicon (a-Si:H). To decouple the impact of stress on the AIC of a-Si:H from other factors that may affect crystallization, such as a-Si:H and aluminum deposition conditions, identical thin film structures [Al (200 nm)/a-Si:H (200 nm)] were deposited on the front surface of all samples. On the back surfaces, various amorphous silicon films were deposited to adjust the curvature of the samples and, therefore, the stress in the a-Si:H film on the front surface. It was found that tensile stress in a-Si:H can retard the AIC of a-Si:H.     

Application of liquid phase deposited silicon dioxide tometal-oxide-semiconductor capacitor and amorphous silicon thin-filmtransistor

Liquid phase deposited silicon dioxide (LPD-SiO₂) is applied to crystalline Si metal-oxide-semiconductor (MOS) capacitor as the gate insulator. It is demonstrated that slow states exist at the Si/SiO₂ interface which cause hysteresis in the capacitance-voltage (C-V) characteristics. These slow states can be removed effectively by post-metallization-anneal. By means of C-V measurement and infrared absorption spectroscopy, it is concluded that the slow states are originated from the residual water or hydroxyl molecules in LPD-SiO₂. The LPD-SiO₂ is also applied to fabricate amorphous silicon (a-Si:H) thin film transistor (TFT) based on a new self-aligned process. The performance of this device is comparable to those of thin film transistors employed other kinds of SiO₂, i.e., thermal, plasma, vacuum evaporation, etc., as the gate insulator. The bias-stress measurement shows that the threshold voltage shift is dominated by charge trapping in the gate insulator