基于FPGA的AES密码协处理器的设计和实现

文章基于FPGA设计了一种能完成AES算法加密的密码协处理器，设计中利用VirtexⅡ系列FPGA的结构特点，对AES算法的实现做了优化。实验证明，这种实现方式用较少的电路资源达到了较高的数据吞吐率。该密码协处理器还提供了和ARM处理器的接口逻辑，实现了用于加／解密和数据输入输出的协处理器指令．作为ARM微处理器指令集的扩展，大大提高了嵌入式系统处理数据加／解的效率，实现数据的安全传输。     

一种适用于RFID标签芯片的AES算法结构设计

针对当前AES算法不能满足超高频RFID标签芯片小面积、高效率的要求,重新构造AES算法的轮变换,实现多个运算步骤同步完成,提高了算法执行效率;用基于有限域的逻辑运算代替S盒查找表,降低芯片面积,满足了超高频RFID系统安全性要求.     

AES/Rijndael算法协处理器设计与实现

AES／Rijndael算法是高性能的加密算法，具有极佳的抗攻击性能。文章提出了AES／Rijndael算法协处理器的半定制ASIC硬件实现方案，设计兼顾了处理速度与硬件资源耗费。其较高的加密强度，对于保护关键信息的安全具有很强的实用价值。方案在Cyclone系列FPGA芯片上实现，占用逻辑单元1400余个，综合仿真和实测的结果验证了本设计的正确性。     

一种有效缩减AES算法S盒面积的组合逻辑优化设计

 通过对AES算法S盒构造原理的研究,利用其中仿射变换的系数具有循环移位的周期性特点对电路结构进行改进,提出一种面积优化的AES算法S盒组合逻辑电路设计方法。该方法基于流水线技术,采用倍频复用的电路结构,较传统结构减少了逻辑资源的使用。经过EDA工具综合仿真和实际系统验证,该方法比Wolkerstorfer和Satoh的S盒有限域实现的硬件规模分别缩减了47.53%和41.49%,比Morioka的S盒真值表实现的硬件规模缩减了21.43%。该设计方案已成功用于一种基于FPGA实现的密码专用处理器设计中。     

基于无线传感网络的AES协处理器设计

无线传感器网络中大部分节点采用电池供电,面积、功耗成为重要的参数.在兼顾速度,功耗情况下设计了一种低成本的AES协处理器.加解密过程中采用复用和共享技术,获得了一个低成本的AES结构,在整个结构中只利用了4个S盒,并采用DSE结构实现S盒,降低了电路功耗.基于Virtex Ⅱ Pro FPGA芯片(90nm工艺技术)实现该结构,消耗面积仅约34k门;在130MHz工作频率下,128位加密的数据吞吐率达到0.67Gb/s.与同类设计相比,该处理器在可接受的吞吐率、功耗下取得了低成本优势,可应用在无线传感网络(WSN)节点芯片中.     

基于MIPS处理器的AES算法指令集扩展方法与实现

由于MIPS处理器数据总线宽度的限制,其扩展的AES(高等加密标准)指令集无法有效实现其并行性的特点.为了提高AES扩展指令集的并行处理能力,利用MIPS处理器中乘法结果寄存器.可以一次实现对64比特数据的AES处理,有效利用处理器自身资源提高指令集的并行处理能力.同时,利用MIPS处理器的空闲流水周期可以流水化AES中的关键运算,缩短其关键路径以降低扩展执行单元对流水周期的影响,对不同实现方式的性能进行比较,结果表明该方法缩短了AES算法中复杂运算的关键路径长度从而使处理器的工作频率不受增加的功能单元的影响,同时有效地减少了芯片面积,并且继承了软件编程灵活性的优点。     

低功耗AES S盒的ASIC设计与实现

S盒是高级加密标准（AES）硬件实现的关键，消耗了AES电路的大部分功耗。提出了一种基于合成域的异步流水线结构，以降低整个S盒的功耗。在电路实现中，电平敏感锁存器被插入数据通道中，以屏蔽动态竞争的传播。一种新的异步握手单元H-element组成的锁存控制器用来控制锁存器的开启和关闭。该S盒电路是一款采用0．25μm CMOS工艺的ASIC，较之合成域S盒电路，版图仿真结果表明，该电路以适宜的面积代价实现了低功耗。该电路可应用在诸如智能卡、无线传感器网络（WSN）节点芯片的嵌入式AES加密引擎中。     

基于状态映射的AES算法硬件混淆设计

代码混淆利用系统自身逻辑来保护内部重要信息和关键算法,常用于软件代码的安全防护,确保开发者和用户的利益。如何在硬件电路上实现混淆、保护硬件IP核的知识产权,也是亟待解决的问题。该文通过对硬件混淆和AES算法的研究,提出一种基于状态映射的AES算法硬件混淆方案。该方案首先利用冗余和黑洞两种状态相结合的状态映射方式,实现有限状态机的混淆;然后,采用比特翻转的方法,实现组合逻辑电路的混淆;最后,在SMIC 65 nm CMOS工艺下设计基于状态映射的AES算法硬件混淆电路,并采用Toggle、数据相关性和代码覆盖率等评价硬件混淆的效率和有效性。实验结果表明,基于状态映射的AES算法硬件混淆电路面积和功耗分别增加9%和16%,代码覆盖率达到93%以上。     

一种AES算法中S盒和逆S盒替换的表达式方法

S盒替换与逆S盒替换是AES算法性能的主要瓶颈,它直接影响AES芯片的运算速度.在优化Q-M化简法基础上,提出了一种实现AES算法中S盒替换和逆S盒替换的表达式方法,这种表达式方法相比于普遍使用的查表法,其延时减小了8.5%,面积减小了27.4%,功耗减小了17%.     

多规格S盒的硬件实现方法

本文用VHDL硬件描述语言实现了1个多规格S盒,兼容1组8×8规格的S盒和4组6×4规格的S盒。通过改变控制编码,它可以实现8×8和6×4规格的任意布尔函数变化,可以满足DES算法和AES算法中的S盒变换,也为密码算法可重组系统设计提供了一个通用IP。     

Low-power clock-less hardware implementation of the rijndael S-box for wireless sensor networks

The recent development of microelectronics techniques and advances in wireless communications have made it feasible to design low-cost, low-power, multifunctional and intelligent sensor nodes for wireless sensor networks (WSN). The design challenges for an efficient WSN mainly lie in two issues power and security. The Rijindael algorithm is a candidate algorithm for encrypting data in WSN. The SubByte (S-box) transformation is the main building block of the Rijindael algorithm. It dominates the hardware complexity and power consumption of the Rijindael cryptographic engine. This article proposes a clock-less hardware implementation of the S-box. In this S-box, 1) The composite field arithmetic in GF((24))2 was used to implement the compact datapath circuit; 2) A high-efficiency latch controller was attained by utilizing the four-phase micropipeline. The presented hardware circuit is an application specific integrated circuit (ASIC) on 0.25 μm complementary mental oxide semiconductor (CMOS) process using three metal layers. The layout simulation results show that the proposed S-box offers low-power consumption and high speed with moderate area penalty. This study also proves that the clock-less design methodology can implement high- performance cryptographic intellectual property (IP) core for the wireless sensor node chips.     

基于静态链表SCPI解析系统设计

针对传统的SCPI解释方式占用过多内存,制约了在嵌入式系统上的应用,文中设计了一种方便移植和扩展的SCPI语言解析方法。该种方法用静态链表的结构来保存SCPI命令集,通过这种方法建立的SCPI解析模块,占用内存少,且方便移植和扩展。利用文中方法设计的SCPI解析模块可方便应于各种智能程控仪器,并适用在嵌入式系统下工作。     

A new S-box construction method based on the fractional-order chaotic Chen system

Since substitution box (S-box) is the only nonlinear component related to confusion properties for many block encryption algorithms, it is a necessity for the strong block encryption algorithms. S-box is a vital component in cryptography due to having the effect on the security of entire system. Therefore, alternative S-box construction techniques have been proposed in many researches. In this study, a new S-box construction method based on fractional-order (FO) chaotic Chen system is presented. In order to achieve that goal, numerical results of the FO chaotic Chen system for \(a= 35, b=3, c=28\) and \(\alpha =0.9\) are obtained by employing the predictor–corrector scheme. Besides, a simpler algorithm is suggested for the construction of S-box via time response of the FO chaotic Chen system. The performance of suggested S-box design is compared with other S-box designs developed by chaotic systems, and it is observed that this method provides a stronger S-box design.     

纠错码方法在S-盒设计中的应用

S-盒是许多分组密码算法中唯一的非线性部件,它的密码强度决定了整个密码算法的安全强度。介绍了分组密码中S-盒的设计准则与构造方法,对S-盒设计中纠错码原理与方法进行讨论,最后给出了现代分组密码中广泛应用于S-盒设计的仿射逆函数所具有的密码特性,并证明了仿射逆函数在代数结构上存在分量函数的线性等价性。     

Subsetting Behavioral Intellectual Property for Low Power ASIP Design

Power consumption is an increasingly important consideration in the design of mixed hardware/software systems. This work defines the notion of instruction subsetting and explores its use as a means of reducing power consumption from the system level of design. Instruction subsetting is defined as creating an application specific instruction set processor from a more general processor, such as a DSP. Although not as effective as an ASIC solution, instruction subsetting provides much of the power savings while maintaining some level of programmability. Beyond energy savings, instruction subsetting also offers the opportunity to reduce the design cycle through the re-use of existing processor intellectual property including behavioral and structural designs, hardware simulators, application code, and compilers. We synthesized 9 ASIPs through place and route and found that a poorly chosen instruction set may consume more than 4 times the energy of an ASIP with a proper instruction set choice. This finding will allow designers to consider another set of trade-offs in their hardware/software design space exploration.     

基于动态策略的S盒设计研究

分组密码作为信息安全应用的主流加密方法,在无线传感器网络中也得到了广泛应用。而S盒作为分组密码算法的核心模块之一,其设计好坏直接影响着整个密码算法。为了在有限的资源下,提高分组密码算法的安全强度,对分组密码算法以及S盒构造设计进行了深入的分析研究,结合Feistel架构和S盒重构的思想,提出了动态S盒的设计方案,并对其进行了相关分析验证。结果表明,经过该设计,安全性能确实有所提高。     

A Machine State Transition Approach to Instruction Retargeting for Embedded Microprocessors

This paper presents an interesting approach to retargeting existing software at the assembly (or binary) level from one instruction set to another instruction set. The approach is based on abstracting the instruction set behaviors as symbolic transitions of the machine states. The retargeting process is modeled as a planning process, an AI technique, that finds a plan (a sequence of operations) which brings the target processor from the same initial state to the same final state as the original software does on the source processor. The approach has been successfully applied in a design project of an x86 compatible microprocessor with an embedded internal RISC core for efficient execution. The proposed approach produced optimal x86-to-RISC mapping. In addition, the approach made it easy to keep up with microarchitecture revision during the design exploration phase since the mapping table can be automatically re-generated and re-evaluated promptly, which is difficult to achieve manually.     

基于复合域通用低熵高阶掩码的设计与实现

通过对基于复合域S-box构造算法的深入研究,该文提出一种低面积复杂度的通用低熵高阶掩码算法。在有限域GF(24)上引入低熵掩码思想,并采用部分模块复用设计,有效降低了基于复合域S-box求逆运算的乘法数量。该算法能够适用于由求逆运算构成的任意分组加密算法,进一步将本方案应用于分组加密算法高级加密标准(AES),给出了详细的综合仿真结果并进行了版图面积优化,较传统的掩码方案相比有效减少了逻辑资源的使用,此外,对其安全性进行了理论验证。     

Instruction set independent program encoding

Instruction encoding techniques have been designed for reducing the program memory footprint and improving processors performance. However, many techniques are instruction-set dependent thus minimizing the adoption in different application domains and target processors. This paper presents an instruction encoding technique and a software framework tool for the design of instruction encoders independent of the instruction set. Our approach is based on (1) a methodological extension of a pattern based instruction word (PBIW) algorithm for instruction encoding; (2) the design and implementation of a software framework for minimizing the design time frame of different instruction encoding algorithms; (3) a comprehensive set of experiments showing the impacts of those techniques on memory footprint, program performance, and processor design. Our proposed framework has been used to encode a wide range of programs compiled for the \(\rho \)-VEX and SPARCv8 instruction sets. The experiments show that the framework makes it able to match the PBIW encoding technique to different ISAs and target machines. The results with SPECint00, Media, MiBench, and simple benchmarks show a compression ratio up to 0.54 (46 % of size reduction) for PBIW-SPARC programs and up to 0.59 for PBIW-VEX programs. Encoded SPARC programs have a performance speedup up to 1.7 compared to non-encoded SPARC programs.     

适用于片上并行计算阵列的超精简处理器架构

提出一种超精简处理单元架构。该处理单元基于运算-跳转式单指令处理器体系。使用指令优化和内部总线上加速器,该处理单元能够执行传统算术运算式单指令处理器难于执行的高效位运算以及执行效率较低的数据转移操作。以该处理单元构成的片上大规模并行计算阵列可用于图像处理等局部性强、实时性要求高的计算任务。包含有该处理单元架构的16 16的原型阵列已经在FPGA上实现,性能达30.7GOPS@120MHz,平均功耗39.5mW。