A 2.7-V GSM RF transceiver IC

A 2.7-V RF transceiver IC is intended for small, low-cost global system for mobile communications (GSM) handsets. This chip includes a quadrature modulator (QMOD) and an offset phase locked loop (OPLL) in the transmit path and a dual IF receiver that consists of a low noise amplifier (LNA) with an active-bias circuit, two Gilbert-cell mixers, a programmable gain linear amplifier (PGA), and a quadrature demodulator (QDEM). The IC also contains frequency dividers with a very high frequency voltage controlled oscillator (VHF-VCO) to simplify the receiver design. The system evaluation results are the phase error of 2.7° r.m.s. and the noise transmitted in the GSM receiving band of -163 dBc/Hz for transmitters and the reference sensitivity of -105 dBm for receivers. Power-control functions are provided for independent transmit and receive operation. The IC is implemented by using bipolar technology with f_T=15 GHz, r'_bb=150 Ω, and 0.6-μm features     

A 2.7-V CMOS dual-mode baseband filter for PDC and WCDMA

A fifth-order analog CMOS RC-opamp baseband filter for a dual-mode cellular phone receiver was designed with maximum component sharing in the two modes, The filter meets the bandwidth specifications of both the PDC and WCDMA standards, which represent the two extremes with respect of the channel bandwidth. The total area of 4.8 mm² was minimized by reducing the filter order from five to three in the PDC mode, Also, the operational amplifiers with adjustable GBW were used to minimize PDC-mode power consumption. The capacitance matrices were made only partially overlapping to reduce the resistance spread, The largest resistors were implemented with T networks and the smallest capacitors with series connections to extend the range of feasible passive component values. The measured integrated input referred noise is 17 μV and 47 μV in the PDC and WCDMA modes, respectively. The IIP3 is +35 dBV in the WCDMA mode, and the circuit consumes 6.8 mW and 25.4 mW in the PDC and WCDMA modes, respectively. The supply voltage is 2.7 V     

A 200-V flat-panel display IC with a novel diffused-well structure

A high-voltage diffused-well structure that allows the low-coast fabrication of a monolithic high-voltage CMOS IC without using any epitaxial layers is discussed. Offset-gate-type PMOSTs for the proposed structure were fabricated within an n-well and a breakdown voltage over 200 V was obtained. A high-performance 200-V CMOS test IC for which high-voltage NMOSTs and low-voltage CMOS peripheral circuits were built in the p-type substrate area was fabricated. Superior latchup immunity was obtained with this structure. A 2200-pF capacitance load corresponding to that of an electroluminescent display panel was successfully driven     

A 2.7-V 900-MHz/1.9-GHz dual-band transceiver IC for digitalwireless communication

A 2.7-V 900-MHz/1.9-GHz dual-band transceiver IC consisting of receive, transmit, and local oscillator (LO) sections is presented. The transmit section achieves an unwanted sideband suppression of -43 dBc, LO leakage of -59 dBc, and third-order spurious rejection of -70 dBc. The transmit output noise level is -165 dBc/Hz at a 20-MHz offset from the carrier. The on-chip very high-frequency oscillator has a phase-noise level of -106 dBc/Hz at 100-kHz offset when operating at 800 MHz. The receive section has 36 dB of gain with 36 dB of gain range in 12-dB steps. The transceiver IC has been fabricated using a 25-GHz f_t silicon bipolar process and is designed to operate over a supply-voltage range of 2.7-5.0 V     

A low-noise, GaAs/AlGaAs, microwave frequency-synthesizer IC

We have developed a GaAs/AlGaAs frequency-synthesizer IC with a 5.5-GHz feedback divider, a 2-GHz reference divider, a 500-MHz phase-frequency detector, 1-ns charge-pump pulses, and a gain-normalized charge-pump output with ±8-mA peak current and an 18-pA/√Hz noise floor. The feedback divider allows continuously selectable divide ratios from 12 to 16383, and supports dual-modulus pulse-swallowing fractional synthesis with single-bit control. The reference divider allows continuously selectable divide ratios from 1 to 4095; an optional divide-by-four/five input prescaler extends the divide ratios to 20475. The chip consumes 1 W from +5 and -5.2 V supplies     

A 2.7-V 300-MS/s track-and-hold amplifier

A fully differential bipolar track-and-hold amplifier (THA) employs an open-loop linearization technique compatible with low supply voltage. A feedthrough reduction method utilizes the junction capacitance of a replica switch to provide a close match to the junction capacitance of the main switch. The differential full-scale (FS) input range is 0.5 V. In the track mode, with f_in=10 MHz, FS sinewave input, the measured total harmonic distortion (THD) is less than -72 dB. With f_s=300 MS/s and f_in=10-50 MHz, FS sinewave input, the measured THD is less than -65 dB. This THD measurement reflects the held values as well as the tracking components of the output waveform. With f_s<10 MS/s and f_in=10-50 MHz, FS sinewave input, the measured feedthrough is less than -60 dB. The hold capacitance is 2.5 pF and the differential droop rate is 16 mV/μs. The THA consumes 32 mW from a 2.7-V power supply and is fabricated in a 0.5-μm, 18-GHz BiCMOS process     

A 2.7-V 1.8-GHz fourth-order tunable LC bandpass filter based on emulation of magnetically coupled resonators

A low-voltage fourth-order RF bandpass filter structure based on emulation of two magnetically coupled resonators is presented. A unique feature of the proposed architecture is using electric coupling to emulate the effect of the coupled inductors, thus providing bandwidth tuning with small passband ripple. Each resonator is built using on-chip spiral inductors and accumulation-mode pMOS capacitors to provide center frequency tuning. The filter has been implemented in HP 0.5-/spl mu/m CMOS process and occupies an area of 0.15 mm/sup 2/. It consumes 16 mA from a single 2.7-V supply at a center frequency of 1.84 GHz and a bandwidth of 80 MHz while providing a passband gain of 9 dB and more than 30 dB of image attenuation for an IF frequency of 100 MHz. The measured output 1-dB compression point and output noise power spectral densities are -16 dBm and -137 dBm/Hz, respectively. This results in a 1-dB compression dynamic range of 42 dB. The filter minimum power supply voltage for proper operation is 2 V. The chip experimental results are in good agreement with theoretical results.     

A 3-V, 0.35-/spl mu/m CMOS Bluetooth receiver IC

A fully integrated CMOS low-IF Bluetooth receiver is presented. The receiver consists of a radio frequency (RF) front end, a phase-locked loop (PLL), an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, and a frequency offset cancellation circuit. The highlights of the receiver include a low-power active complex filter with a nonconventional tuning scheme and a high-performance mixed-mode GFSK demodulator. The chip was fabricated on a 6.25-mm/sup 2/ die using TSMC 0.35-/spl mu/m standard CMOS process. -82 dBm sensitivity at 1e-3 bit error rate, -10 dBm IIP3, and 15 dB noise figure were achieved in the measurements. The receiver active current is about 65 mA from a 3-V power supply.     

A monolithic 200-V CMOS analog switch

A new high-voltage CMOS technology is described which can increase the operating voltage of these circuits to more than 200 V. This represents approximately an order of magnitude improvement over present-day commercially available CMOS devices. The technology is straightforward to implement and uses n-channel MOS transistors and high-voltage p-channel devices. As an example of the capability of the technology, a monolithic quad CMOS analog switch has been fabricated which can handle 200-V, 0.3-A analog signals, with a dynamic range in excess of 150 dB.     

A 2.7-V SiGe HBT variable gain amplifier for CDMA applications

A monolithic SiGe HBT variable gain amplifier with high dB-linear gain control and high linearity has been developed for CDMA applications. The VGA achieves a 30-dB dynamic gain control with a control range of 0-2.7 Vdc in 824-849 MHz band. The maximum gain and attenuation are 23 dB and 7 dB, respectively. Input/output VSWRs keep low and constant despite change in the gain-control voltage. At a low operation voltage of 2.7 V, the VGA produces a 1-dB compression output power of 13 dBm and /spl plusmn/885-kHz ACPR of -57 dBc at a 5-dBm output power.     

A 3-V continuous-time filter with on-chip tuning for IS-95

This paper describes a low-voltage channel selection analog front end with continuous-time low-pass filters and on-chip tuning for a receiver in an IS-95 cellular phone. The filters were realized as balanced seventh-order elliptical g_mC filters to achieve low current consumption. The transconductors were realized by using second-generation current conveyors (CCII) and resistors to achieve good intermodulation distortion performance. A novel CCII circuit topology was developed to fulfil the low supply-voltage requirement. The cutoff frequency tuning was implemented with capacitance matrices and a time-domain master-slave tuning circuit     

A 2-V 2.5-GHz-104-dBc/Hz at 100 kHz fully integrated VCO withwide-band low-noise automatic amplitude control loop

The automatic amplitude control (AAC) loop is an indispensable element for the practical realization of VCOs embedded in a complete transceiver. Its noise however can unacceptably degrade the single-sideband-to-carrier ratio (SSCR) performance of the oscillator, this problem being even exacerbated in low-voltage circuits. This paper addresses the design issues of a low-voltage low-noise differential LC-VCO with AAC, tunable within a 2.3-2.8-GHz frequency range, fully integrated in bipolar technology with 2-V power supply. First, the mechanisms through which the AAC noise affects the output phase are identified as the poor indirect stability and the AM-to-PM conversion due to the varactors. The effect of the AAC noise is discussed and substantially reduced with suitable design choices. We show that the achievable noise-to-signal ratio is bounded by the shot noise coming from the bias source of the differential oscillator, an intrinsic limit set by the low supply voltage which does not allow for degeneration of the tail transistor. Second, the design of the AAC is discussed. A large gain-bandwidth product (GBWP), about 100 MHz, has been implemented in order to correct for the fast oscillation amplitude variations and reduce the effect of the ground line disturbances. The expected value of the phase noise level, SSCR at 100 kHz =-104 dBc/Hz, is tightly matched by the experimental results. The core oscillator dissipates 7 mA, while less than 600 μA are drawn by the AAC circuit     

A fully integrated 24-dBm CMOS power amplifier for 802.11a WLAN applications

A fully integrated 24-dBm complementary metal oxide semiconductor (CMOS) power amplifier (PA) for 5-GHz WLAN applications is implemented using 0.18-/spl mu/m CMOS foundry process. It consists of differential three-stage amplifiers and fully integrated input/output matching circuits. The amplifier shows a P/sub 1/ of 21.8 dBm, power added efficiency of 13%, and gain of 21 dB, respectively. The saturated output power is above 24.1 dBm. This shows the highest output power among the reported 5-GHz CMOS PAs as well as completely satisfying IEEE 802.11a transmitter back off requirement.     

A flat-panel display control IC with 150-V drivers

A flat-panel display control IC with 150-V drivers is realized in high-voltage analog/digital IC technology utilizing a low-cost p-n junction isolation process. An improved semiwell isolation structure that has an epitaxial layer of two different thicknesses is used. In order to achieve high-voltage push-pull operation, totem-pole-type output circuits are formed in the structure's thick, high-resistivity epitaxial area. A compact complementary transistor logic circuit is successfully integrated in the n-wells of the structure's thin epitaxial area to meet the high-speed requirement for control logic. A stacked circuit is used to reduce the standby power needs of the logic circuits.     

A 700-V interface IC for power bridge circuits

A 700-V integrated interface circuit is presented. It provides the gate drive for the high-side and the ground-side power MOS transistor in an offline half-bridge circuit. Ground separation for good intersystem electromagnetic compatibility (EMC) and a number of new provisions to alleviate control requirements on the low-power system control section are included. An electronic ballast for gas discharge lamps is considered as an application example. Experimental results are presented     

一种13位400 kHz 11 mW Σ-Δ模拟/数字转换器

设计了应用于低中频GSM接收机的三阶单环单比特结构Σ-Δ A/D转换器。调制器采用全差分开关电容积分器实现。仿真结果显示,在工作电压为3 V、信号带宽200 kHz、0.35μm CMOS工艺的条件下,过采样率选择为64,信号/噪声失真比(SNDR)达到85 dB,功耗不超过11mW。     

A 16-bit 250-kHz delta-sigma modulator and decimation filter

This paper describes a delta-sigma analog-to-digital converter (ADC) capable of converting input frequencies up to 250 kHz. It consists of a fifth-order switched-capacitor delta-sigma modulator and a decimation filter. Various design optimizations in the modulator are presented. The decimation filter consists of a comb filter followed by a novel, highly efficient and scalable finite impulse response filter. The ADC was implemented in 0.6-μm CMOS technology. It achieves a dynamic range of 94 db     

A high speed, fully digital IC random number generator

System-on-a-chip solutions require hardware based integrated circuit random number generators for trustworthy transmission of information. This paper presents, a fully digital, high speed ASIC random number generator based on ring oscillators. Prototypes have been designed and fabricated in HHNEC's 0.25 μm eFlash process with a supply voltage of 2.5 V. The circuit occupies 0.052 mm² and dissipates 0.095 W of power. IC design level experiences, measurements, analysis of measurements and statistical test results are also demonstrated. Instead of resilient function, employed in the previous ring oscillators based design, which decreases the throughput by a factor of 16, we propose to use only a simple Von Neumann corrector which improves this result by a factor of 4. We achieved fulfilled test results from NIST 800-22 test suit after Von Neumann corrector with a sampling frequency of 74 MHz. Since, Von Neumann corrector is used as a post-processor, the throughput becomes 18.5 Mbps. Furthermore, we propose to use doubled ring oscillators structure, thus, a 125 Mbps throughput, which is the highest data rate to date with fulfilled test results, is attained without any postprocessing. The results were repeatable numerous times.     

A 0.8-V accurately tuned linear continuous-time filter

An accurately tuned low-voltage linear continuous-time filter is presented in this paper. Accurate tuning is achieved using time-constant matched master-slave tuning combined with power-up mismatch calibration. A low-pass biquad designed for a corner frequency of 115 kHz achieves better than -80-dB total harmonic distortion with a 250-mV/sub pp/ 10-kHz input signal. The prototype implemented in 0.18-/spl mu/m CMOS process occupies an area of 0.4 mm/sup 2/ and dissipates 4.6 mW (2.6 mW for the filter and 2 mW for tuning) of power.     

A low-noise widely tunable Gm-C filter with frequency calibration

A fourth-order Gm-C Chebyshev low-pass filter is presented as channel selection filter for reconfigurable multi-mode wireless receivers. Low-noise technologies are proposed in optimizing the noise characteristics of both the Gm cells and the filter topology. A frequency tuning strategy is used by tuning both the transconductance of the Gm cells and the capacitance of the capacitor banks. To achieve accurate cut-off frequencies, an on-chip calibration circuit is presented to compensate for the frequency inaccuracy introduced by process variation. The filter is fabricated in a 0.13 μm CMOS process. It exhibits a wide programmable bandwidth from 322.5 kHz to 20 MHz. Measured results show that the filter has low input referred noise of 5.9 nV/√Hz and high out-of-band ⅡP3 of 16.2 dBm. It consumes 4.2 and 9.5 mW from a 1 V power supply at its lowest and highest cut-off frequencies respectively.