OFDM超宽带3.1-4.8GHz CMOS发射机设计

本文介绍一种应用于3.1-4.8GHz 多频带正交频分复用超宽带系统的低功耗射频CMOS发射机芯片的设计和实现。发射机系统主要由电压电流跨导级、正交上变频调制器、有源双转单转换器、输出增益可控功率放大器以及产生正交差分LO信号的除2除法器等模块组成。使用上调制器,双转单及输出放大器分段谐振技术解决3.1-4.8GHz宽带增益平坦度问题;使用源级电阻负反馈镜像跨导解决系统低电压高线性度问题;使用无源电感谐振双转单电路及增益可控放大器进行低功耗设计。测试结果表明,芯片能够提供-10.7到-3.1dBm的功率输出,并且在子带增益平坦度低于3dB;输出三阶交调量最高可达12dBm;不低于30dBc的载波抑制和35dBc以上的边带抑制。芯片采用Jazz 0.18μm射频CMOS工艺流片,包括ESD防护PAD在内芯片总面积为1.74mm2。 在1.8V的电源电压下,芯片总电流为32mA。     

OFDM超宽带3.1-4.8GHz CMOS射频收发机设计

本文介绍一种应用于3.1-4.8GHz 多频带正交频分复用超宽带系统的CMOS射频收发机芯片的设计和实现。射频收发机采用零中频结构,主要模块包括：增益可控的宽带低噪声放大器、正交跨导复用下变频混频器、5阶Gm-C切比雪夫低通滤波器及可变增益放大器;采用多项滤波器进行边带杂散抑制的快速跳变频率综合器;宽带线性上变频正交调制器、片内有源双转单电路及输出可变增益放大器。芯片测试结果表明,接收机最大能够获得68dB的电压增益,其中42dB为可变增益,增益步长为6dB;在三个子带内的噪声系数为5.5~8.8dB;带内IIP3和带外IIP3不低于-4dBm和9dBm;发射机能够提供-10.7~-3dBm的输出功率,7.7dB的增益可控;输出1dB压缩点不低于-7.7dBm;发射信号边带抑制为32.4dBc,载波泄漏抑制可达31.1dBc;频率综合器的快速跳边时间低于2.05nS。芯片采用Jazz 0.18μm射频CMOS工艺流片,包括ESD防护PAD在内芯片总面积为6.1mm2;在1.8V的电源电压下,整个芯片的工作电流为221mA (RX+TX+SYN+Buffers）。     

一种用于3.1–4.8GHz MB-OFDM 超宽带系统的CMOS接收机

本文介绍一种应用于3.1-4.8GHz 多频带正交频分复用超宽带系统的全集成全差分CMOS接收机芯片。在接收机射频前端中应用了一种增益可变的低噪声放大器和合并结构的正交混频器。在I/Q中频通路中则集成了5阶Gm-C结构的有源低通滤波器以及可变增益放大器。芯片通过Jazz 0.18μm RF CMOS工艺流片,含ESD保护电路。该接收机最大电压增益为65dB,增益可调范围为45dB,步长6dB;接收机在3个频段的平均噪声系数为6.4-8.8dB,带内输入三阶交调量(IIP3)为-5.1dBm。芯片面积为2.3平方毫米,在1.8V电压下,包括测试缓冲电路和数字模块在内的总电流为110mA。     

A monolithic 3.1-4.8 GHz MB-OFDM UWB transceiver in 0.18-μm CMOS

A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is presented.The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA,a I/Q merged quadrature mixer,a fifth-order Gm-C bi-quad Chebyshev LPF/VGA,a fast-settling frequency synthesizer with a poly-phase filter,a linear broadband up-conversion quadrature modulator,an active D2S converter and a variablegain power amplifier.The ESD protected transceiver is fabricated in Jazz Semiconductor's 0.18-μm RF CMOS with an area of 6.1 mm2 and draws a total current of 221 mA from 1.8-V supply.The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/Step,noise figures of 5.5-8.8 dB for three sub-bands,and an inband/out-band IIP3 better than-4 dBm/+9 dBm.The transmitter achieves an output power ranging from-10.7 to-3dBm with gain control,an output P1dB better than-7.7 dBm,a sideband rejection about 32.4 dBc,and LO suppression of 31.1 dBc.The hopping time among sub-bands is less than 2.05 ns.     

A monolithic 3.1-4.8 GHz MB-OFDM UWB transceiver in 0.18-μm CMOS

正A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is presented.The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA,a I/Q merged quadrature mixer,a fifth-order Gm-C bi-quad Chebyshev LPF/VGA,a fast-settling frequency synthesizer with a poly-phase filter,a linear broadband up-conversion quadrature modulator,an active D2S converter and a variablegain power amplifier.The ESD protected transceiver is fabricated in Jazz Semiconductor's 0.18-μm RF CMOS with an area of 6.1 mm~2 and draws a total current of 221 mAfrom 1.8-V supply.The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/step,noise figures of 5.5-8.8 dB for three sub-bands,and an inband /out-band IIP_3 better than-4 dBm/+9 dBm.The transmitter achieves an output power ranging from-10.7 to-3 dBm with gain control,an output P_(1dB) better than-7.7 dBm,a sideband rejection about 32.4 dBc,and LO suppression of 31.1 dBc.The hopping time among sub-bands is less than 2.05 ns.     

3.7 GHz宽带CMOS LC VCO的设计

设计了一款3.7 GHz宽带CMOS电感电容压控振荡器.采用了电容开关的技术以补偿工艺、温度和电源电压的变化,并对片上电感和射频开关进行优化设计以得到最大的Q值.电路采用和舰0.18 μm CMOS混合信号制造工艺,芯片面积为0.4 mm×1 mm.测试结果显示,芯片的工作频率为3.4～4 GHz,根据输出频谱得到的相位噪声为-100 dBc/Hz@1 MHz,在1.8 V工作电压下的功耗为10 mW.测试结果表明,该VCO有较大的工作频率范围和较低的相位噪声性能,可以用于锁相环和频率合成器.     

5GHz0.18μm CMOS宽带LC VCO

采用0.18μm RF CMOS工艺,设计了一个5GHz的宽带电感电容压控振荡器。该压控振荡器的电路结构选用互补交叉耦合型,采用噪声滤波技术降低相位噪声,并采用开关电容阵列扩展其调谐范围。后仿真结果表明,实现了4.44～5.44GHz的宽调谐。振荡器的电源电压为1.8V,工作电流为2.78mA,版图面积为0.37mm2。     

A 3.16–7 GHz transformer-based dual-band CMOS VCO

A dual-band, wide tuning range voltage-controlled oscillator that uses transformer-based fourth-order(LC) resonator with a compact common-centric layout is presented. Compared with the traditional wide band(VCO), it can double frequency tuning range without degrading phase noise performance. The relationship between the coupling coefficient of the transformer, selection of frequency bands, and the quality factor at each band is investigated. The transformer used in the resonator is a circular asymmetric concentric topology. Compared with conventional octagon spirals, the proposed circular asymmetric concentric transformer results in a higher qualityfactor, and hence a lower oscillator phase noise. The VCO is designed and fabricated in a 0.18- m CMOS technology and has 75% wide tuning range of 3.16–7.01 GHz. Depending on the oscillation frequency, the VCO current consumption is adjusted from 4.9 to 6.3 m A. The measured phase noises at 1 MHz offset from carrier frequencies of 3.1, 4.5, 5.1, and 6.6 GHz are –122.5, –113.3, –110.1, and –116.8 d Bc/Hz, respectively. The chip area, including the pads, is 1.20.62 mm2 and the supply voltage is 1.8 V.     

3.1～10.6 GHz CMOS超宽带低噪声放大器设计

本文给出了一个低电压、低功耗增益连续可调CMOS超宽带低噪声放大器(Ultra-wideband Low Noise Amplifier,UWB LNA)设计。在0.85V工作电压下放大器的直流功耗约为10mW。在3.1～10.6GHz的超宽带频段内,增益S21为14±0.4dB,且随控制电压VC连续可调。输入、输出阻抗匹配S11、S22均低于-10dB,噪声系数(NF)最小值为3.3dB。设计采用TSMC 0.18μm RF CMOS工艺完成。     

A 3.1-4.8 GHz transmitter with a high frequency divider in 0.18 μm CMOS for OFDM-UWB

A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single (D2S) converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18/zm RF CMOS process with an area of 1.74 mm~2 and only consumes 32 mA current (at 1.8 V) including the test associated parts.     

2.5GHz低相位噪声CMOS LC VCO的设计

用0.35μm、一层多晶、四层金属、3.3V的标准全数字CMOS工艺设计了一个全集成的2.5GHz LC VCO,电路采用全差分互补负跨导结构以降低电路功耗和减少器件1/f噪声的影响.为了减少高频噪声的影响,采用了在片LC滤波技术.可变电容采用增强型MOS可变电容,取得了23%的频率调节范围.采用单个16边形的对称片上螺旋电感,并在电感下加接地屏蔽层,从而减少芯片面积,优化Q值.取得了在离中心频率1MHz处-118dBc/Hz的相位噪声性能.电源电压为3.3V时的功耗为4mA.     

5 GHz 0.18 μm CMOS工艺正交输出VCO

文章采用全开关状态的延时单元和双延时路径两种电路技术设计了一种高工作频率、低相位噪声的环形振荡器.环路级数采用偶数级来获得两路相位相差90 ℃的正交输出时钟.采用TSMC 0.18 μm CMOS工艺进行流片,电压控制振荡器(VCO)的频率范围为4.9～5.5 GHz,模拟的相位噪声为-119.3 dBc/Hz@5 M,采用1.8 V电源电压,核芯电路的功耗为30 mW, 振荡器核芯面积为60 μm×60 μm.     

频率覆盖3.2～6.1 GHz的CMOS LC VCO

通过提高MIM电容的调整范围,实现了一个覆盖3.2～6.1 GHz的CMOS LC VCO.该VCO使用0.18μm射频CMOS工艺制作,芯片面积约为1260μm×670μm.当输出5.5GHz时,VCO内核消耗功率为17.5mW;在100kHz频偏处的相位噪声是～101.67dBc/Hz.     

一个6GHz宽带低相位噪声CMOS LC VCO

用SMIC 0.13 μm CMOS工艺实现了一个低相位噪声的6 GHz压控振荡器(VCO).在对其相位噪声分析的基础上,通过改进和优化传统的调谐单元和噪声滤波电路以及加入源极负反馈电阻实现了一个宽带、低增益、低相位噪声VCO.测试结果显示,在中心频率频偏1 MHz处的相位噪声为-119 dBc/Hz,频率调谐范围为6...     

频率覆盖3.2～6.1 GHz的CMOS LC VCO

通过提高MIM电容的调整范围,实现了一个覆盖3.2～6.1 GHz的CMOS LC VCO.该VCO使用0.18μm射频CMOS工艺制作,芯片面积约为1260μm×670μm.当输出5.5GHz时,VCO内核消耗功率为17.5mW;在100kHz频偏处的相位噪声是～101.67dBc/Hz.     

2.5GHz低相位噪声CMOS LC VCO的设计

用0 .35μm、一层多晶、四层金属、3.3V的标准全数字CMOS工艺设计了一个全集成的2 .5 GHz L C VCO,电路采用全差分互补负跨导结构以降低电路功耗和减少器件1/ f噪声的影响.为了减少高频噪声的影响,采用了在片L C滤波技术.可变电容采用增强型MOS可变电容,取得了2 3%的频率调节范围.采用单个16边形的对称片上螺旋电感,并在电感下加接地屏蔽层,从而减少芯片面积,优化Q值.取得了在离中心频率1MHz处- 118d Bc/ Hz的相位噪声性能.电源电压为3.3V时的功耗为4 m A.     

A 3.1-4.8 GHz transmitter with a high frequency divider in 0.18μm CMOS for OFDM-UWB

A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single （D2S） converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18μm RF CMOS process with an area of 1.74 mm^2 and only consumes 32 mA current （at 1.8 V） including the test associated parts.     

0.18m CMOS工艺3.1～5.2GHz低噪声放大器

基于共源级联放大器的小信号模型,详细分析了宽带放大器的输入阻抗特性和噪声特性。利用MOS晶体管的寄生容性反馈机理,采用TSMC公司标准0.18μmCMOS工艺设计实现了单片集成宽带低噪声放大器,芯片尺寸为0.6mm×1.5mm。测试结果表明,在3.1～5.2GHz频段内,S11<-15dB,S21>12dB,S22<-12dB,噪声系数NF<3.1dB。电源电压为1.8V,功耗为14mW。     

0.18μm CMOS 3.1-10.6GHz超宽带低噪声放大器设计

介绍了一种基于0.18μm CMOS工艺、适用于超宽带无线通信系统接收前端的低噪声放大器.在3.1～10.6GHz的频带范围内对它仿真获得如下结果:最高增益12dB;增益波动小于2dB;输入端口反射系数S11小于-10dB;输出端口反射系数S22小于-15dB;噪声系数NF小于4.6dB.采用1.5V电源供电,功耗为10.5mW.与近期公开发表的超宽带低噪声放大器仿真结果相比较,本电路结构具有工作带宽大、功耗低、输入匹配电路简单的优点.     

一种1.8 V 4.8 GHz 0.9 mW 0.18 μm CMOS分频器

给出了一个电源电压为1.8 V、功耗为0.9 mW的4.8 GHz二分频器。该分频器采用基于反转触发器(TFF)的电路结构,使用动态负载,输出I、Q两路正交信号。对设计的电路采用标准UMC 0.18μm CMOS工艺进行了仿真,结果表明,该分频器工作频率可达6.5 GHz。