A single-chip CMOS PCM codec

Describes a single-chip full duplex per channel PCM codec implemented in a metal gate CMOS process. An 8-bit companding DAC, a novel autozeroed analog subsystem, and a 3.5-MHz frame interface control logic comprise the 175/spl times/195-mil integrated circuit. The DAC is implemented with matched n channel devices and utilizes redundancy and feedback to achieve the required accuracy. The analog subsystem contains two sample and hold circuits, autozeroing circuitry, CMOS amplifiers, and a fast CMOS comparator.     

Design of an MPEG-2 codec

We review the design of a single-chip MPEG-2 a/v codec, covering the design process from the MPEG specifications and system requirements to the final design. After a brief overview of MPEG-1 and MPEG-2 standards, we examine the system requirements using as an example a universal serial bus (USB)-based MPEG-2 real-time digital video recorder. Finally, we present in more detail the hardware and software architecture of a specific MPEG a/v codec     

A single-chip CMOS filter/codec

A second generation LSI codec has been implemented. In this chip, switched-capacitor filters, a charge redistribution encoder and decoder, voltage references, a signaling logic circuit, and all necessary functions for voice-PCM conversion are integrated. The authors describe the codec and summarizes its characteristics.     

A single-chip codec with switched-capacitor filters

A single-chip CMOS codec with filters has been developed using charge redistribution and switched-capacitor techniques. Its features are ~30 mm/SUP 2/ small chip area, 35 mW low power dissipation, and small 16 pin package. These are achieved with novel analog circuit techniques for A/D and D/A conversions and clock generation. Measured transmission characteristics meet the system requirements.     

A single-chip adaptive DPCM video codec

A differential pulse-code modulation (DPCM) video codec with two-dimensional intrafield prediction and adaptive quantizer is presented. An approach for the arithmetic implementation of the DPCM structure and the design of a test chip, fabricated in a 1.5 μm CMOS technology, is described. This is the first VLSI realization of a DPCM codec with adaptive quantizer. For the test chip transmitter or receiver mode, application as part of a three-dimensional interframe codec and processing of luminance or chrominance signals are optional. A line buffer and ten different quantizer characteristics are realized on-chip. Correct operation has been verified up to 26 MHz     

A single-chip I/SUP 2/L PCM codec

A single chip CPCM codec is described. This chip, which is fabricated in bipolar technology, meets all the D3 specifications. The circuit is capable of operating in a fully asynchronous transmit and receive mode, and provisions are made for zero code suppression and A/B signaling. Even with this signaling, the codec achieves a worst case idle channel noise of 13 dBrnC0.     

基于PCI总线的MPEG-2视频

对C-Cube公司最新一代的MPEG-2视频编解码芯片DVXPRESS-DVXPERT的结构特点作了详细的分析和介绍,并给出了一种基于PCI总线的单片实时实现MPEG-2视频编解码系统的硬件实现方案,该方案具有成本低、采集节目质量高、稳定性好等一系列优点.     

A single-chip CMOS PCM codec with filters

A complete PCM codec using charge redistribution and switched-capacitor techniques will be described. The device is implemented in a two-level polysilicon CMOS technology using 23.4 mm/SUP 2/ of active area. It features all the required transmission filters needed for telephony, two on-chip voltage references, TTL compatible digital interfaces, and low-power dissipation. The architecture of the chip allows asynchronous operation, a variable PCM data rate from 100 kbit/s to 4.096 Mbit/s, /spl mu//A law operation via pin selection, and gain selection at either of two levels in each direction.     

怎样选择嵌入式媒体处理器

选择一片多媒体应用处理器是一项复杂的工作.为了做出最好的选择,需要先做好以下准备. ●全面地分析每个候选处理器的内核结构以及外围设备. ●扎实地理解视频和音频数据如何流过系统. ●评估在规定功耗条件下可达到的处理水平.     

Tests on MPEG-4 audio codec proposals

During December 1995, subjective tests were carried out by members of the Moving Picture Experts Group (MPEG, ISO/JTC1/SC29/WG11) to select the proposed technology for inclusion in the audio part of the new MPEG-4 standard. The new standard addresses coding for more than just the functionality of data rate compression. Material coded at very low bit-rates is also included. Thus, different testing methodologies were applied, according to ITU-R Rec. BS 1116 for a bit-rate of 64 kbit/s per channel and according to ITU-T Rec. P.80 for lower bit-rates or functionalities other than data rate compression. Proposals were subjectively tested for coding efficiency, error resilience, scalability and speed change: a subset of the MPEG-4 ‘functionalities’. This paper describes how two different evaluation methods were used and adjusted to fit the different testing requirements. This first major effort to test coding schemes at low bit-rates proved successful. Based on the test results, decisions for MPEG-4 technology were made.

This was the first opportunity for MPEG members to carry out tests on the submitted functionalities. In the process, much was learnt. As a result, some suggestions are made to improve the way new functionalities can be subjectively evaluated.     

A single-chip programmable platform based on a multithreaded processor and configurable logic clusters

This paper presents a single-chip programmable platform that integrates most of hardware blocks required in the design of embedded system chips. The platform includes a 32-bit multithreaded RISC processor (MT-RISC), configurable logic clusters (CLCs), programmable first-in-first-out (FIFO) memories, control circuitry, and on-chip memories. For rapid thread switch, a multithreaded processor equipped with a hardware thread scheduling unit is adopted, and configurable logics are grouped into clusters for IP-based design. By integrating both the multithreaded processor and the configurable logic on a single chip, high-level language-based designs can be easily accommodated by performing the complex and concurrent functions of a target chip on the multithreaded processor and implementing the external interface functions into the configurable logic clusters. A 64-mm/sup 2/ prototype chip integrating a four-threaded MT-RISC, three CLCs, programmable FIFOs, and 8-kB on-chip memories is fabricated in a 0.35-/spl mu/m CMOS technology with four metal layers, which operates at 100-MHz clock frequency and consumes 370 mW at 3.3-V power supply.     

A single-chip 80-bit floating point processor

A single-chip 80-bit floating point VLSI processor capable of performing 5.6 million floating point operations per second has been realized using 1.2-/spl mu/m n-well CMOS technology. The processor handles 80-bit double-extended floating point data conforming to IEEE standard 754. The chip has 128 microinstructions which are stored in an on-chip ROM. By programming microinstruction sequences in an external control storage, not only basic arithmetic operation but also special arithmetic functions can be performed. A composite design method supported by a hierarchical design automation system was used to quickly lay out 50K gates including a 64-/spl times/64-bit multiplier and 15 kb of memory on a chip with a die size of 10/spl times/10 mm/SUP 2/. Only 11 man-months were required for the effort.     

Hardware/compiler codevelopment for an embedded media processor

Embedded and portable systems running multimedia applications create a new challenge for hardware architects. A microprocessor for such applications needs to be easy to program like a general-purpose processor and have the performance and power efficiency of a digital signal processor. This paper presents the codevelopment of the instruction set, the hardware, and the compiler for the Vector IRAM media processor. A vector architecture is used to exploit the data parallelism of multimedia programs, which allows the use of highly modular hardware and enables implementations that combine high performance, low power consumption, and reduced design complexity. It also leads to a compiler model that is efficient both in terms of performance and executable code size. The memory system for the vector processor is implemented using embedded DRAM technology, which provides high bandwidth in an integrated, cost-effective manner. The hardware and the compiler for this architecture make complementary contributions to the efficiency of the overall system. This paper explores the interactions and tradeoffs between them, as well as the enhancements to a vector architecture necessary for multimedia processing. We also describe how the architecture, design, and compiler features come together in a prototype system-on-a-chip, able to execute 3.2 billion operations per second per watt     

基于GPRS的ARM7嵌入式单片机视频报警系统

为解决传统视频监控系统中存在的诸多弊端,满足更高的安全需求,提出一种新型的基于GPRS的嵌入式视频报警系统．该系统具有体积小、实时性强、功耗低等特点,并实现了图像的高速采集和传输。它无需处理模拟视频信号的PC机。而是把摄像机输出的模拟视频信号通过嵌入式视频编码器直接转换成IP数字信号。结果表明：该系统对大多数低中速运动物体能有效的发现报警,通过应用GPRS协议,分辨率能达到90％,算法的效率提高8％,传输数据帧的精度提高5％．很好地克服了传统的图像采集系统的缺陷。     

基于GPRS的ARM7嵌入式单片机视频报警系统

为解决传统视频监控系统中存在的诸多弊端,满足更高的安全需求,提出一种新型的基于GPRS的嵌入式视频报警系统.该系统具有体积小、实时性强、功耗低等特点,并实现了图像的高速采集和传输.它无需处理模拟视频信号的PC机,而是把摄像机输出的模拟视频信号通过嵌入式视频编码器直接转换成IP数字信号.结果表明:该系统对大多数低中速运动物体能有效的发现报警,通过应用GPRS协议,分辨率能达到90%,算法的效率提高8%,传输数据帧的精度提高5%,很好地克服了传统的图像采集系统的缺陷.     

基于EP9315的嵌入式Linux移植

描述了将Linux移植到基于EP9315处理器的目标板上的方法和过程,包括交叉编译环境的建立,开发工具使用,内核的裁剪、编译以及文件系统的移植.最后并以一个基本程序为例调试成功,验证了应用程序移植和调试过程的正确性和可行性.     

A single-chip digital signal processor for telecommunication applications

A single-chip, software-programmable digital signal processor, intended for telecommunication applications, has been developed. The processor, fabricated with the most advanced 3 /spl mu/m n-channel E/D MOS technology, incorporates a 16/spl times/16-bit full hardware multiplier and a sophisticated bus structure to minimize bus conflicts, thus attaining the capability to implement 55 second-order filters at a sampling rate of 8 kHz with sufficient dynamic range to process PCM encoded signals. The authors describe the design concept, architecture, instructions, device design, and application techniques.     

基于Blackfin处理器的嵌入式数码相框设计

介绍了汇聚式处理器Blackfin的基本功能,给出了以Blackfin为嵌入式系统硬件平台,并采用uClinux操作系统和其中集成的大量硬件驱动程序来设计具有互联网WiFi无线连接、电子邮件发送、RSS新闻阅读、即时照片分享、全触摸操作等功能的嵌入式数码相框的设计方案。     

A 2.7-V CMOS single-chip baseband processor for CT2/CT2+ cordlesstelephones

A low-voltage, low-power CMOS single-chip baseband processor for CT2 and CT2+ cordless telephones is presented. The chip integrates a complete voiceband codec, a tone generator, a G721 adaptive differential pulse code modulation coder/decoder, a burst-mode logic controller for CT2/CT2+ framings, and an I/Q baseband signal generator. The only external components are made of two quartz crystals. The chip is interfaced with standard microcontrollers through a parallel interface. With a 2.7 V minimum supply, it consumes normal and standby powers of 35 mW and 25 μW, respectively. Maximum supply is 5.5 V, and temperature range is from -40 to 70°C. Chip area (including scribe line) is 55.5 mm² in a 0.8 μm N-well double-metal single-poly CMOS process with implanted capacitors     

基于以太网的嵌入式实时MPEG-2传输系统

介绍了一种实时MPEG-2以太网传输系统的设计方案,它由硬件MPEG-2编/解码器VW2010和基于ARM处理器的嵌入式系统卡构成,前者用于视音频的实时压缩编码和解码,后者将MPEG-2数据流进行IP封装和解封装;还分析了IP网络传输对接收端MPEG-2解码视音频的影响.