A 64 mW High Picture Quality H.264/MPEG-4 Video Codec IP for HD Mobile Applications in 90 nm CMOS

We have developed an H.264/MPEG-4 dual video codec IP for mobile applications such as digital still cameras (DSCs), digital video cameras (DVCs), and mobile phones. The codec is capable of encoding and decoding HD-sized moving pictures (1280 pixels by 720 lines at 30 fps) in real-time at an operating frequency of 144 MHz, and SD-sized pictures at 54 MHz. We have implemented our original architecture based on a macroblock-level pipeline method and encoding algorithms suitable for the architecture in the codec, which enable low power of 64 mW for HD encoding with high picture quality equivalent to that of the H.264 reference encoder “JM (Joint Model)”.      

Design of an MPEG-2 codec

We review the design of a single-chip MPEG-2 a/v codec, covering the design process from the MPEG specifications and system requirements to the final design. After a brief overview of MPEG-1 and MPEG-2 standards, we examine the system requirements using as an example a universal serial bus (USB)-based MPEG-2 real-time digital video recorder. Finally, we present in more detail the hardware and software architecture of a specific MPEG a/v codec     

数字电视系统中的时间恢复和音视频同步

音视频同步是数字电视系统中实现实时解码的难点.讨论MPEG-2传输码流中的时间信息在音视频同步中的作用,详细介绍两种MPEG-2系统时序时钟的恢复方法--锁相环同步和异步置数法,给出处理音视频同步的实际方法,采用跳帧或者重复帧的纠正措施.其算法及几个主要电路设计适用于各种MPEG-2解码器.     

Instruction Set Extensions for MPEG-4 Video

This paper describes instruction set extensions for the acceleration of MPEG-4 algorithms on programmable (RISC-) CPUs. MPEG-4 standardizes audio and video compression schemes for a variety of bit rates and scenarios. As MPEG-4 targets a much broader range of different applications than previously defined hybrid video coding standards like H.263 or MPEG-2, it employs a much higher number of different algorithms and coding modes. Therefore, MPEG-4 implementations will require a more software-oriented approach to be efficient. However, the total computational load for an optimized implementation of an MPEG-4 video codec is expected to exceed the performance levels of today's multimedia signal processors, making further hardware acceleration a necessity. For that purpose, we propose a number of instruction set extensions that add function-specific blocks to the data path of a CPU. These dedicated modules are highly adapted to the most computation-intensive processing schemes of MPEG-4, such as DCT, motion compensation, padding, shape coding, or bitstream parsing. The increased functionality of basic instructions results in a significant speed-up over standard RISC instruction sets, thus making MPEG-4 implementations feasible on programmable processor platforms. Possible target architectures include VLIW multimedia processors, MIMD-style multiprocessors, or coprocessor architectures     

A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling

A single-chip H.264 and MPEG-4 audio-visual LSI for mobile applications including terrestrial digital broadcasting system (ISDB-T / DVB-H) with a module-wise, dynamic voltage/frequency scaling architecture is presented for the first time. This LSI can keep operating even during the voltage/frequency transition, so there is no performance overhead. It is realized through a dynamic deskewing system and an on-chip voltage regulator with slew rate control. By the combination with traditional low power techniques such as embedded DRAM and clock gating, it consumes only 63 mW in decoding QVGA H.264 video at 15 frames/sec and MPEG-4 AAC LC audio simultaneously.     

适用于物联网的网络视频监控器的设计

设计了一种应用干基于光纤传感技术的物联网系统中的网络视频监控器.基干C/S模型,采用集成了高速ARM9处理核和高效MPEG-4编解码引攀的FIC8120芯片,并优化设计了嵌入式Linux驱动程序和用户程序.测试表明,该系统具备完善的控制功能和高效的编码性能,能联合光纤传感网络和中心控制服务器对各种侵入进行实时的定位、监...     

基于RF5的MPEG-4编解码器的移植与实现

简要介绍了MPEG-4视频编码器的实现原理,详细分析了基于实时操作系统DSP/BIOS的RF5框架,将MPEG-4视频编码器和解码器在VC下合成并仿真成功,提取合成编解码器中的编码模块和解码模块分两种方式移植到DM642上,一种是在一个任务中完成视频的采集、编解码处理和显示功能,另一种是分别由3个任务来完成视频的采集、编解码处理和显示功能,最终成功地实现了两种方式下的编解码器,在DM642上能完成视频的连续采集、编解码处理和显示.     

一种用于 HDTV集成解码芯片的I/O控制策略

数据的存取控制是系统集成芯片软硬件协同设计中的关键环节。许多文献都给出了对 ＭＰＥＧ—２ ＭＰ＠ＭＬ视频解码器的Ｉ／Ｏ控制策略，但是很少涉及如何有效地存取ＭＰＥＧ—２ＭＰ＠ＭＬ的数据，特别是如何控制包含系统层、视频和音频三个部分进行解码的集成解码芯片的数据输入输出。本文通过详细的分析和计算，结合不同类型数据传送的特点，提出了一种有效的用于这种集成解码芯片的Ｉ／Ｏ控制策略，在增加有限的芯片引脚的情况下，简化了数据输入输出的控制逻辑，降低了片上用于Ｉ／Ｏ控制的逻辑资源。     

A real-time digital VCR encode/decode and MPEG-2 decode LSIimplemented on a dual-issue RISC processor

A real-time system large-scale-integrated circuit (LSI) for digital video cassette recorder (DVCR) encoding/decoding and MPEG-2 decoding is implemented on a dual-issue RISC processor (DRISC) with dedicated hardware optimized for video-block processing. The DRISC achieves 972-MOPS software performance and can execute fixed-length data processing at the block level as well as processing at the macro-block level and above for the DVCR/MPEG-2. The dedicated hardware for variable-length coding/decoding can encode and decode codes for both the DVCR and the MPEG-2 by changing translation tables. The dedicated hardware for video-block loading can process video-block data transfers with half-pel operations. The LSI size is 7.7×7.2 mm² in a 0.25-μm CMOS process     

A 1.5-W single-chip MPEG-2 MP@ML video encoder with low powermotion estimation and clocking

A 1.5-W single-chip MPEG-2 MP@ML real-time video encoder large scale integrated circuit (LSI) has been developed. To form an MPEG-2 encoder system, we employ two 16-Mb synchronous DRAM's, a microprocessor unit (MPU), and an audio encoder LSI. Owing to a two-step hierarchical search scheme and a novel adaptive search window scheme, the search range of motion estimation is -48/+47 horizontal and -96/+15.5 vertical, and the pseudo search range, which is the size when the location of the search window is adaptively shifted, is -96/+95 horizontal and -32/+31.5 vertical. We have also developed low-power clocking techniques, i.e., demand-clock controller, local-clock controller, and low-power flip-flops, which can eliminate waste of power in clocking. We have successfully fabricated these new designs as a low-power single-chip MPEG-2 encoder LSI. The operating frequency except for a synchronous DRAM interface unit and a video in/out unit is 54 MHz. The supply voltage to the first and second search engines in a motion estimation unit can be successfully lowered to 2.5 V and the others are 3.3 V. Into a 12.45×12.45 mm² chip with 0.35-μm CMOS and triple-metal layer technology are integrated 3.1 M transistors     

A 99-mm2 0.7-W single-chip MPEG-2 422P@ML video, audio,and system encoder with a 64-Mb embedded DRAM for portable 422P@HLencoder system

A scalable single-chip 422P@ML MPEG-2 video, audio, and system encoder LSI for portable 422P@HL system is described. The encoder LSI is implemented using 0.13-μm embedded DRAM technology. It integrates 3-M logic gates and 64-Mb DRAM in an area of 99-mm². The power consumption is suppressed to 0.7 W by adopting a low-power DRAM core. It performs real-time 422P@ML video encoding, audio encoding, and system encoding with no external DRAM. Furthermore, the encoder LSI realizes a 422P@HL video encoder with multichip configuration, due to its scalable architecture. This results in a PC-card size 422P@HL encoder for portable HDTV codec system     

Fast Interframe mode decision algorithm based on mode mapping and MB activity for MPEG-2 to H.264/AVC transcoding

Recently the latest video coding standard H.264/AVC is widely used for the mobile and low bitrate video codec in the various multimedia terminals. On the other hand, the MPEG-2 MP@HL codec has become the center of digital video contents since it is the standard codec for the Digital TV (DTV). To provide the bridge between the contents in MPEG-2 and mobile terminals, the transcoding of MPEG-2 contents into H.264/AVC format is an inevitable technology in the digital video market. The main bottleneck in the process lies in the computational complexity. In H.264/AVC, the variable block size (VBS) mode decision (MD) is used in the Interframe for the improved performance in the motion compensated prediction. For the macroblock (MB) which cannot be accurately predicted with one motion vector (MV), it is partitioned into smaller blocks and predicted with different MVs. In addition, SKIP and Intra modes are also permitted in the Interframe MD of H.264/AVC to further ameliorate the encoding performance. With the VBS MD technology, the Inter prediction accuracy can be improved significantly. However, the incidental side-effect is the high computational complexity. In this paper, we propose a fast Interframe MD algorithm for MPEG-2 to H.264/AVC transcoding. The relationships between SKIP and Intra modes are detected at first to map these two kinds of modes directly from MPEG-2 to H.264/AVC. And then the MB activity will be scaled by the residual DCT energy obtained from the MPEG-2 decoding process to estimate the block sizes of the MB mode for H.264/AVC Interframe MD. In our proposed method, the original redundant candidate modes can be eliminated effectively, resulting in the reduction of the computational complexity. It can reduce about 85% Rate-to-Distortion Cost (RDCost) computing and 45% entire processing time compared with the well-known cascaded transcoder while maintaining the video quality.     

A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessorfor multimedia applications

We have designed a microprocessor that is based on a single instruction multiple data stream (SIMD) architecture. It features a two-way superscalar architecture for multimedia embedded systems that need to support especially MPEG2 video decoding/encoding and 3DCG image processing. This microprocessor meets all requirements of embedded systems, including (a) MPEG2 (MP@ML) decoding and graphic processing capabilities for three-dimensional images, (b) programming flexibility, and (c) low power consumption and low manufacturing cost. High performance was achieved by enhanced parallel processing capabilities while adopting a SIMD architecture and a two-way superscalar architecture. Programming flexibility was increased by providing 170 dedicated multimedia instructions. Low power consumption was achieved by utilizing advanced process technology and power-saving circuits. The processor supports a general-purpose RISC instruction set. This feature is important, as the processor will have to work as a controller of various target systems. The processor has been fabricated by 0.21-μm CMOS four-metal technology on a 9.84×10.12 mm die. It performs 2.16 GOPS/720 MFLOPS at an operating frequency of 180 MHz, with a power consumption of 1.2 W and a power supply of 1.8 V     

MPEG-4 high-efficiency AAC coding

The name MPEG-4 high-efficiency AAC (HE-AAC) refers to a family of recent audio coders that was developed by the International Organization for Standardization/International Electrotechnical Commission (ISO/IEC) Moving Picture Experts Group (MPEG) by subsequent extension of the established Advanced Audio Coding (AAC) architecture. These algorithmic extensions facilitate a significant increase in coding efficiency relative to previous standards and other known systems. Thus, they provide a representation for generic audio/music signals that offers high audio quality also to applications limited in transmission bandwidth or storage capacity, such as digital audio broadcasting and wireless music access for cellular phones. This article presents a compact overview of the evolution, technology, and performance of the MPEG-4 HE-AAC coding family.     

基于MPEG-4视频标准数字视频录像机的设计与实现

国内外许多公司都在开发有关MPEG-4视频标准的产品,最具代表意义的即是数字视频录像机(DVR)。为了缩短开发周期,这里介绍基于嵌入式Linux操作系统,应用专用音视频编解码芯片AT2042实现数字视频录像机功能,该系统实现MPEG-4视频标准高级框架的编解码器,并在此基础上添加数字硬盘的功能,例如编码存储、解码播放、快进、快退和暂停等功能。最后给出系统的实际运行的测试结果。该系统已实现对视频数据的编、解码,且实现MPEG-4/MPEG-2/MPEG-1 H.263视频标准,并已成为成型产品推向市场。     

A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI

This paper describes a block processing unit in a single-chip MPEG-2 MP@ML video encoder LSI. The block processing unit executes algorithms such as a discrete cosine transform (DCT), a quantization, an inverse quantization, and an inverse discrete cosine transform (IDCT). A double-block pipeline scheme has been introduced to execute DCT and IDCT operations on the shared circuits. Using a time-multiplexed DCT/IDCT architecture, we achieve processing performance of 2.0 clk/pel. This architecture has 21% fewer transistors and 30% less power dissipation than a conventional one. The number of transistors of the block processing unit is 240 kTr which measures 7.7% of the total of the chip. By controlling the clock signal supply, power dissipation can be reduced to 43% which is about 400 mW at 3.3 V using a 0.35 m triple-layer metal CMOS cell-base technology at 54 MHz.     

A Cost-Shared Quantization Algorithm and Its Implementation for Multi-Standard Video Codecs

Due to the growing demand of digital convergence, there is a need to have a video encoder/decoder (codec) that is capable of supporting multiple video standards on a single platform. High Efficiency Video Coding (HEVC), successor to H.264/MPEG-4 AVC, is a new standard under development that aims to substantially improve coding efficiency compared to AVC High Profile. This paper presents an efficient architecture based on a resource sharing strategy that can perform the quantization operation of the emerging HEVC encoder and six other video encoders: H.264/AVC, AVS, VC-1, MPEG-2, MPEG-4, and Motion JPEG (MJPEG). Since HEVC is still in the drafting stage, the proposed architecture is designed in such a way that any final changes can be accommodated into the design. The proposed quantizer architecture is completely division-free, as the division operation is replaced by shift and addition operations for all the codecs. The design is implemented on an FPGA and later synthesized in CMOS 0.18 μm technology. While working at 190 MHz, the design can decode a 1080p HD video at up to 61 frames per second. The multi-codec architecture is also suitable for low-cost VLSI implementation.     

Architecture and design of NX-2700: a programmable single-chip HDTVall-format-decode-and-display processor

This paper describes the architecture, functionality, and design of NX-2700, a digital television and media processor chip from Philips Semiconductors. The NX-2700 is the second generation of an architectural family of programmable multimedia processors targeted at the digital television (DTV) markets, including the United States Advanced Television Systems Committee (ATSC) DTV-standard-based applications. The chip not only supports all of the 18 ATSC formats from standard-definition to wide-angle, high-definition video, but has also the power to handle high-definition television (HDTV) video and audio source decoding (high-level MPEG-5 AC-3 and ProLogic audio, closed captioning, etc.) as well as the flexibility to process advanced interactive services. NX-2700 is a programmable processor with a very powerful, general-purpose very long instruction word (VLIW) central processing unit (CPU) core that implements many nontrivial multimedia algorithms, coordinates all on-chip activities, and runs a small real-time operating system. The CPU core, aided by an array of peripheral devices (multimedia coprocessors and input-output units) and high-performance buses, facilitates concurrent processing of audio, video, graphics, and communication-data     

基于Digital 21230芯片的数字图像监控系统

建立了一种适用保于高速信道的一代数字图像监控系统,并就涉及的关键技术和实现方法进行了讨论。采用Ｄｉｇｉｔａｌ２１２３０芯片硬件件实现视音频ＭＰＥＧ－１标准的实时压缩与解压缩,软件上基于Ｗｉｎｄｏｗｓ９ｘ／ＮＴ平台用ＶｓｕａｌＣ＋＋开发了一套完整的视音频编解码控制,同步步传输和系统多功能操作等应用程序。