Drain current model of double‐gate MOSFETs considering both electrons and holes

We present a rigorously derived current solution for undoped double‐gate (DG) MOSFETs with two carriers, which is based on surface potentials. The third‐order Newton–Raphson (NR) method is used to solve the surface‐potential equations resulting from the application of the boundary conditions to the general Poisson solution, with an initial guess very close to the true solution. The results demonstrate surface‐potential solutions for DG MOSFETs with 2–7 iterations to achieve an accuracy of 10⁻¹⁵. The drain current model for two carriers is presented as a benchmark to test the accuracy of one‐carrier current approximation. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Device circuit co‐design to reduce gate leakage current in VLSI logic circuits in nano regime

In this paper, nanoscale metal–oxide–semiconductor field‐effect transistor (MOSFET) device circuit co‐design is presented with an aim to reduce the gate leakage curren t in VLSI logic circuits. Firstly, gate leakage current is modeled through high‐k spacer underlap MOSFET (HSU MOSFET). In this HSU MOSFET, inversion layer is induced in underlap region by the gate fringing field through high‐k dielectric (high‐k) spacer, and this inversion layer in the underlap region acts as extended source/drain region. The analytical model results are compared with the two‐dimensional Sentaurus device simulation. Good agreement is obtained between the model and Sentaurus simulation. It is observed that modified HSU MOSFET had improved off current, subthreshold slope, and drain‐induced barrier lowering characteristics. Further, modified HSU MOSFET is also analyzed for gate leakage in generic logic circuits. Copyright © 2015 John Wiley & Sons, Ltd.     

A Gate‐Current Model for Advanced MOSFET Technologies Implemented into HiSIM2

A gate leakage current model for advanced MOSFETs has been developed and implemented into the Hiroshima‐university STARC IGFET Model (HiSIM), the first complete surface‐potential‐based model. The model consists of four tunneling mechanisms, the gate to channel/bulk/source/drain, and requires totally 15 model parameters covering all bias conditions. Simulation results reproduce measurement for any device size and temperature without binning. Validity of the model has been tested with circuits that are sensitive to the change of stored charge due to tunneling current. Copyright © 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A linearly adaptive gate drive technique for light‐load efficiency improvement of DC–DC converters

This paper presents a linearly adaptive gate drive technique to improve the light‐load efficiency of DC–DC converters. The optimal‐driving voltages of the power MOSFETs for reducing gate‐driving loss can be well modeled by a linear function of the load current. By scaling the gate drive voltage dynamically with respect to load current, the light‐load efficiency can be enhanced. The experimental result shows that the proposed gate drive technique can attain about 9% incremental light‐load efficiency enhancement. Copyright © 2008 John Wiley & Sons, Ltd.     

An analytical model of triple‐material double‐gate metal–oxide–semiconductor field‐effect transistor to suppress short‐channel effects

This paper presents an analytical subthreshold model for surface potential and threshold voltage of a triple‐material double‐gate (DG) metal–oxide–semiconductor field‐effect transistor. The model is developed by using a rectangular Gaussian box in the channel depletion region with the required boundary conditions at the source and drain end. The model is used to study the effect of triple‐material gate structure on the electrical performance of the device in terms of changes in potential and electric field. The device immunity against short‐channel effects is evaluated by comparing the relative performance parameters such as drain‐induced barrier lowering, threshold voltage roll‐off, and subthreshold swing with its counterparts in the single‐material DG and double‐material DG metal–oxide–semiconductor field‐effect transistors. The developed surface potential model not only provides device physics insight but is also computationally efficient because of its simple compact form that can be utilized to study and characterize the gate‐engineered devices. Furthermore, the effects of quantum confinement are analyzed with the development of a quantum‐mechanical correction term for threshold voltage. The results obtained from the model are in close agreement with the data extracted from numerical Technology Computer Aided Design device simulation. Copyright © 2015 John Wiley & Sons, Ltd.     

Potential‐based threshold voltage and subthreshold swing models for junctionless double‐gate metal‐oxide‐semiconductor field‐effect transistor with dual‐material gate

On the basis of quasi‐two‐dimensional solution of Poisson's equation, an analytical threshold voltage model for junctionless dual‐material double‐gate (JLDMDG) metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is developed for the first time. The advantages of JLDMDG MOSFET are proved by comparing the central electrostatic potential and electric field distribution with those of junctionless single‐material double‐gate (JLSMDG) MOSFET. The proposed model explicitly shows how the device parameters (such as the silicon thickness, oxide thickness, and doping concentration) affect the threshold voltage. In addition, the variations of threshold voltage roll‐off, drain‐induced barrier lowering (DIBL), and subthreshold swing with the channel length are investigated. It is proved that the device performance for JLDMDG MOSFET can be changed flexibly by adjusting the length ratios of control gate and screen gate. The model is verified by comparing its calculated results with those obtained from three‐dimensional numerical device simulator ISE. Copyright © 2015 John Wiley & Sons, Ltd.     

Monte Carlo analysis of dynamic characteristics and high‐frequency noise performances of nanoscale double‐gate MOSFETs

In this paper, a full‐band Monte Carlo simulator is employed to study the dynamic characteristics and high‐frequency noise performances of a double‐gate (DG) metal–oxide–semiconductor field‐effect transistor (MOSFET) with 30 nm gate length. Admittance parameters (Y parameters) are calculated to characterize the dynamic response of the device. The noise behaviors of the simulated structure are studied on the basis of the spectral densities of the instantaneous current fluctuations at the drain and gate terminals, together with their cross‐correlation. Then the normalized noise parameters (P, R, and C), minimum noise figure (NF_min), and so on are employed to evaluate the noise performances. To show the outstanding radio‐frequency performances of the DG MOSFET, a single‐gate silicon‐on‐insulator MOSFET with the same gate length is also studied for comparison. The results show that the DG structure provides better dynamic characteristics and superior high‐frequency noise performances, owing to its inherent short‐channel effect immunity, better gate control ability, and lower channel noise. Copyright © 2012 John Wiley & Sons, Ltd.     

Green's function approach for modeling of electrostatic effects in nanoscale fully depleted double‐gate silicon‐on‐insulator metal‐oxide‐semiconductor field‐effect transistors

Exact solution of two‐dimensional (2D) Poisson's equation for fully depleted double‐gate silicon‐on‐insulator metal‐oxide‐semiconductor field‐effect transistor is derived using three‐zone Green's function solution technique. Framework consists of consideration of source–drain junction curvature. 2D potential profile obtained forms the basis for estimation of threshold voltage. Temperature dependence of front surface potential distribution, back surface potential distribution and front‐gate threshold voltage are modeled using temperature sensitive parameters. Applying newly developed model, surface potential and threshold voltage sensitivities to gate oxide thickness have been comprehensively investigated. Device simulation is performed using ATLAS 2D (SILVACO, 4701 Patrick Henry Drive, Bldg. Santa Clara, CA 95054 USA) device simulator, and the results obtained are compared with the proposed 2D model. The model results are found to be in good agreement with the simulated data. Copyright © 2013 John Wiley & Sons, Ltd.     

Development of gate drive circuit for next‐generation ultrahigh‐speed switching devices

This paper describes a gate drive circuit which is capable of driving an ultrahigh‐speed switching device and of suppressing high‐frequency noise caused by its high dV/dt ratio of 104 V/μs order. SiC (silicon carbide)‐based power semiconductor devices are very promising as next‐generation ultrahigh‐speed switching devices. However, one of their application problems is how to drive them with less high‐frequency noise without sacrificing their ultrahigh‐speed operation capability. The paper proposes a new gate drive circuit specialized for such devices, which charges and discharges the input capacitance of the device by using an impulse voltage generated by inductors. This ultrahigh‐speed switching operation causes a high‐frequency common‐mode noise current in the gate drive circuit, which penetrates an isolated power‐supply transformer due to the parasitic capacitance between the primary and the secondary windings. In order to overcome this secondary problem, a toroidal multicore transformer is also proposed in the paper in order to reduce the parasitic capacitance drastically. By applying the former technique, the turn‐on time and turn‐off time of the power device were shortened by 50% and by 20%, compared with a conventional push‐pull gate drive circuit, respectively. In addition, the latter technique allows reduction of the peak common‐mode noise current to 25%, compared with the use of a conventional standard utility power‐supply transformer. © 2011 Wiley Periodicals, Inc. Electr Eng Jpn, 176(4): 52–60, 2011; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21124     

Analysis of the floating‐gate transistor using the charge sheet model

The multiple‐input floating‐gate transistor is a semiconductor device that has found wide application in digital and analog electronic integrated circuits. Simulating an electronic circuit is an essential step in the design flow, prior to manufacturing. Therefore, an advanced model for the multiple‐input floating‐gate transistor is needed for analog design. This paper shows a method for adapting the charge sheet model for advanced models of the device. In addition, the problem of obtaining the drain to source current numerically as a function of external voltages is addressed. Furthermore, important plots are presented in order to clarify the behavior of the concerned device. The small signal analysis of the device is included. This summary may be interesting to those seeking to model the multiple‐input floating‐gate transistor, looking for alternatives to analog electronic design, needing low operating voltage, generating new design strategies, or wishing to understand of the operation of the device or the use of alternatives to implement analog circuits. Copyright © 2015 John Wiley & Sons, Ltd.     

Measurement of the interface trap and dielectric charge density in high-/spl kappa/ gate stacks

We demonstrate an accurate measurement of the interface trap density and the stress-induced dielectric charge density in Si/high-/spl kappa/ gate dielectric stacks of metal-oxide-semiconductor field-effect transistors (MOSFETs) using the direct-current current-voltage (DCIV) technique. The capture cross section and density of the interface traps in the high-/spl kappa/ gate stack were found to be similar to those of the Si/SiO/sub 2/ interface. A constant-voltage stress of the p-channel MOSFET in inversion is shown to result in a negative dielectric charging and an increase in the interface trap density.     

Degradation of direct‐tunneling gate oxide under hot hole injection

The degradation of ultrathin SiO₂ films accompanied by the hole direct tunneling is investigated using a substrate hot hole (SHH) injection technique. Hot holes from the substrate as well as cold holes in the inversion layer are injected into the gate oxides in p‐channel MOSFETs with p⁺ poly‐Si gates, while the gate bias is kept low enough to avoid simultaneous electron injection from the gate. During the SHH stress, in contrast to the case of thicker oxide films, a strong correlation is observed between the oxide film degradation and the injected hole energy, whereas no degradation occurs due to the hole direct tunneling from the inversion layer. These experimental findings indicate the existence of threshold energy for trap creation process, which has been predicted by the theoretical study of hole‐injection‐induced structural transformation of oxygen vacancy in SiO₂. © 2002 Wiley Periodicals, Inc. Electr Eng Jpn, 140(4): 54–61, 2002; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.2008     

A 3-D Atomistic Study of Archetypal Double Gate MOSFET Structures

The double gate MOSFET architecture has been proposed as a possible solution to allow the scaling of MOSFETs to the sub-30 nm regime, particularly due to its inherent resistance to short-channel effects. The use of lightly doped, or even undoped, channels means that such devices should be inherently resistant to random dopant induced fluctuations which will be one of the major obstacles to MOSFET scaling towards the end of the Si Roadmap. Random dopants within the channel are not, however, the only source of intrinsic fluctuations within MOSFETs at this scale. In this paper we investigate the impact of discrete dopants in the source and drain, individual charges within the active region and line edge roughness on the intrinsic parameter fluctuations in double gate MOSFETs.     

A physically based,accurate compact model of direct tunneling gate current considering quantum mechanical effects in nanoscale metal‐oxide‐semiconductor field‐effect transistors

We present a physically based, accurate model of the direct tunneling gate current of nanoscale metal‐oxide‐semiconductor field‐effect transistors considering quantum mechanical effects. Effect of wave function penetration into the gate dielectric is also incorporated. When electrons tunnel from the metal oxide semiconductor inversion layer to the gate, the eigenenergies of the quasi‐bound states turn out to be complex quantities. The imaginary part of these complex eigenenergies, Γ_ij, are required to estimate the finite lifetimes of these states. We present an empirical equation of Γ_ij as a function of surface potential. Inversion layer electron concentration is determined using eigenenergies, calculated by modified Airy function approximation. Hence, a compact model of direct tunneling gate current is proposed using a novel approach. Good agreement of the proposed compact model with self‐consistent numerical simulator and published experimental data for a wide range of substrate doping densities and oxide thicknesses states the accuracy and robustness of the proposed model. The proposed model can well be extended for devices with high‐κ/stack gate dielectrics introducing necessary modifications. Copyright © 2011 John Wiley & Sons, Ltd.     

Drain current multiplication in thin pillar vertical MOSFETs due to depletion isolation and charge coupling

Drain current multiplication in vertical MOSFETs due to body isolation by the drain depletion region and gate–gate charge coupling is investigated at pillar thicknesses in the range of 200–10 nm. For pillar thickness >120 nm depletion isolation does not occur and hence the body contact is found to be completely effective with no multiplication in drain current, whereas for pillar thicknesses <60 nm depletion isolation occurs for all drain biases and hence the body contact is ineffective. For intermediate pillar thicknesses of 60–120 nm, even though depletion isolation is apparent, the body contact is still effective in improving floating body effects and breakdown. At these intermediate pillar thicknesses, a kink is also observed in the output characteristics due to partial depletion isolation. The charging kink and the breakdown behavior are characterized as a function of pillar thickness, and a transition in the transistor behavior is seen at a pillar thickness of 60 nm. For pillar thickness greater than 60 nm, the voltage at which body charging occurs decreases (and the normalized breakdown current increases) with decreasing pillar thickness, whereas for pillar thickness less than 60 nm, the opposite trend is seen. The relative contributions to the drain current of depletion isolation and the inherent gate–gate charge coupling are quantified. For pillar thickness between 120 and 80 nm, the rise in the drain current is found to be mainly due to depletion isolation, whereas for pillar thicknesses <60 nm, the increase in the drain current is found to be governed by the inherent gate–gate charge coupling.     

Threshold voltage modeling for dual‐metal quadruple‐gate (DMQG) MOSFETs

In this paper, a three‐dimensional (3D) model of threshold voltage is presented for dual‐metal quadruple‐gate metal‐oxide‐semiconductor field effect transistors. The 3D channel potential is obtained by solving 3D Laplace's equation using an isomorphic polynomial function. Threshold voltage is defined as the gate voltage, at which the integrated charge (Q_inv) at the ‘virtual‐cathode’ reaches to a critical charge Q_th. The potential distribution and the threshold voltage are studied with varying the device parameters like gate metal work functions, channel cross‐section, oxide thickness, and gate length ratio. Further, the drain‐induced barrier lowering has also been analyzed for different gate length ratios. The model results are compared with the numerical simulation results obtained from 3D ATLAS device simulation results. Copyright © 2015 John Wiley & Sons, Ltd.     

Implementation of the symmetric doped double‐gate MOSFET model in Verilog‐A for circuit simulation

Recently we developed a model for symmetric double‐gate MOSFETs (SDDGM) that, for the first time, considers the doping concentration in the Si film in the complete range from 1×10¹⁴ to 3×10¹⁸ cm⁻³. The model covers a wide range of technological parameters and includes short channel effects. It was validated for different devices using data from simulations, as well as measured in real devices. In this paper, we present the implementation in Verilog‐A code of this model, which allows its introduction in commercial simulators. The Verilog‐A implementation was optimized to achieve reduction in computational time, as well as good accuracy. Results are compared with data from 2D simulations, showing a very good agreement in all transistor operation regions. Copyright © 2009 John Wiley & Sons, Ltd.     

Investigation of multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) sub‐50 nm MOSFET: A novel design

In this paper, a two‐dimensional (2D) analytical sub‐threshold model for a novel sub‐50 nm multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) MOSFET is presented and investigated using ATLAS device simulator to counteract the large gate leakage current and increased standby power consumption that arise due to continued scaling of SiO₂‐based gate dielectrics. The model includes the evaluation of surface potential, electric field along the channel, threshold voltage, drain‐induced barrier lowering, sub‐threshold drain current and sub‐threshold swing. Results reveal that MLGEWE‐RC MOSFET design exhibits significant enhancement in terms of improved hot carrier effect immunity, carrier transport efficiency and reduced short channel effects proving its efficacy for high‐speed integration circuits and analog design. Copyright © 2008 John Wiley & Sons, Ltd.     

An ultra‐thin oxide sub‐1 V CMOS bandgap voltage reference

This paper presents a sub‐1 V CMOS bandgap voltage reference that accounts for the presence of direct tunneling‐induced gate current. This current increases exponentially with decreasing oxide thickness and is especially prevalent in traditional (non‐high‐κ/metal gate) ultra‐thin oxide CMOS technologies (t_ox < 3 nm), where it invalidates the simplifying design assumption of infinite gate resistance. The developed reference (average temperature coefficient, T_{C_AVG}, of 22.5 ppm/°C) overcomes direct tunneling by employing circuit techniques that minimize, balance, and cancel its effects. It is compared to a thick‐oxide voltage reference (T_{C_AVG} = 14.0 ppm/°C) as a means of demonstrating that ultra‐thin oxide MOSFETs can achieve performance similar to that of more expensive thick(er) oxide MOSFETs and that they can be used to design the analog component of a mixed‐signal system. The reference was investigated in a 65 nm CMOS technology with a nominal V_DD of 1 V and a physical oxide thickness of 1.25 nm. Copyright © 2013 John Wiley & Sons, Ltd.     

Electrostatic discharge effects in ultrathin gate oxide MOSFETs

The effects of destructive and nondestructive electrostatic discharge (ESD) events applied either to the gate or drain terminal of MOSFETs with ultrathin gate oxide, emulating the occurrence of an ESD event at the input or output IC pins, respectively, were investigated. The authors studied how ESD may affect MOSFET reliability in terms of time-to-breakdown (TTBD) of the gate oxide and degradation of the transistor electrical characteristics under subsequent electrical stresses. The main results of this paper demonstrate that ESD stresses may modify the MOSFET current driving capability immediately after stress and during subsequent accelerated stresses but do not affect the TTBD distributions. The damage introduced by ESD in MOSFETs increases when the gate oxide thickness is reduced.