Channel noise enhancement in small geometry MOSFET and its influence on phase noise calculation of integrated voltage‐controlled oscillator

Channel noise enhancement due to MOSFET scaling and its influence on phase noise estimation of fully integrated VCO have been studied. The channel noise of MOSFET increases due to the hot electron effect of small geometry MOSFET is obvious. The channel noise coefficient, γ, of NMOS is 3.5 for 40‐nm gate length, 2.0 for 90‐nm gate length in spite of being ⅔ for long channels MOSFET. Simultaneously, calculation of phase noise of fully integrated VCO shows large difference using γ=⅔ because the part of noise performance of VCO gain‐cell depends on channel noise of MOSFET. Calculated phase noise showed good agreement with measured data when the optimum value of channel noise of MOSFET was adopted. Copyright © 2005 John Wiley & Sons, Ltd.     

Explicit modelling of the double‐gate MOSFET with VHDL‐AMS

This paper presents a new compact model for the undoped, long‐channel double‐gate (DG) MOSFET under symmetrical operation. In particular, we propose a robust algorithm for computing the mobile charge density as an explicit function of the terminal voltages. It allows to greatly reduce the computation time without losing any accuracy. In order to validate the analytical model, we have also developed the 2D simulations of a DG MOSFET structure and performed both static and dynamic electrical simulations of the device. Comparisons with the 2D numerical simulations give evidence for the good behaviour and the accuracy of the model. Finally, we present the VHDL‐AMS code of the DG MOSFET model and related simulation results. Copyright © 2006 John Wiley & Sons, Ltd.     

Impact of channel length,gate insulator thickness,gate insulator material,and temperature on the performance of nanoscale FETs

Aggressive technology scaling as per Moore’s law has led to elevated power dissipation levels owing to an exponential increase in subthreshold leakage power. Short channel effects (SCEs) due to channel length reduction, gate insulator thickness change, application of high-k gate insulator, and temperature change in a double-gate metal–oxide–semiconductor field-effect transistor (DG MOSFET) and carbon nanotube field-effect transistor (CNTFET) were investigated in this work. Computational simulations were performed to investigate SCEs, viz. the threshold voltage (V_th) roll-off, subthreshold swing (SS), and I_on/I_off ratio, in the DG MOSFET and CNTFET while reducing the channel length. The CNTFET showed better performance than the DG MOSFET, including near-zero SCEs due to its pure ballistic transport mechanism. We also examined the threshold voltage (V_th), subthreshold swing (SS), and I_on/I_off ratio of the DG MOSFET and CNTFET with varying gate insulator thickness, gate insulator material, and temperature. Finally, we handpicked almost similar parameters for both the CNTFET and DG MOSFET and carried out performance analysis based on the simulation results. Comparative analysis of the results showed that the CNTFET provides 47.8 times more I_on/I_off ratio than the DG MOSFET. Its better control over the threshold voltage, near-zero SCEs, high on-current, low leakage power consumption, and ability to operate at high temperature make the CNTFET a viable option for use in enhanced switching applications and low-voltage digital applications in nanoelectronics.     

Potential‐based threshold voltage and subthreshold swing models for junctionless double‐gate metal‐oxide‐semiconductor field‐effect transistor with dual‐material gate

On the basis of quasi‐two‐dimensional solution of Poisson's equation, an analytical threshold voltage model for junctionless dual‐material double‐gate (JLDMDG) metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is developed for the first time. The advantages of JLDMDG MOSFET are proved by comparing the central electrostatic potential and electric field distribution with those of junctionless single‐material double‐gate (JLSMDG) MOSFET. The proposed model explicitly shows how the device parameters (such as the silicon thickness, oxide thickness, and doping concentration) affect the threshold voltage. In addition, the variations of threshold voltage roll‐off, drain‐induced barrier lowering (DIBL), and subthreshold swing with the channel length are investigated. It is proved that the device performance for JLDMDG MOSFET can be changed flexibly by adjusting the length ratios of control gate and screen gate. The model is verified by comparing its calculated results with those obtained from three‐dimensional numerical device simulator ISE. Copyright © 2015 John Wiley & Sons, Ltd.     

A simulation study of high‐order CMOS hyperbolic‐sine filters

This paper advances the field of externally linear–internally nonlinear (ELIN) filters by introducing a synthesis method that enables the design of high‐order class‐AB sinh filters by means of complementary metal–oxide semiconductor (CMOS) weak‐inversion sinh integrators comprising only one type of devices in their translinear loops. The proposed transistor‐level synthesis approach is demonstrated through the examples of (1) a biquadratic and (2) a fifth‐order filter, and their simulated performance is studied. The biquadratic filter achieves a dynamic range of 94 dB and has a tunable quality factor Q up to the value of 8, whereas its natural frequency can be tuned for four orders of magnitude. Its static power consumption amounts to 6.2 μW for Q = 1 and f_o = 2 kHz. The fifth‐order Chebyshev sinh CMOS filter with a cut‐off frequency of 100 Hz, a pass band ripple of 1 dB, and a power consumption of ~300 nW is compared head‐to‐head with its pseudo‐differential class‐AB CMOS log domain counterpart. The sinh filter achieves similar or better signal‐to‐noise ratio (SNR) and signal‐to‐noise‐plus‐distortion ratio (SNDR) performances with half the capacitor area but at the expense of higher power consumption from the same power supply level. All three presented filter topologies are novel. Cadence design framework simulations have been performed using the commercially available 0.35 µm AMS (austriamicrosystems) process parameters. Copyright © 2013 John Wiley & Sons, Ltd.     

An analytical model of triple‐material double‐gate metal–oxide–semiconductor field‐effect transistor to suppress short‐channel effects

This paper presents an analytical subthreshold model for surface potential and threshold voltage of a triple‐material double‐gate (DG) metal–oxide–semiconductor field‐effect transistor. The model is developed by using a rectangular Gaussian box in the channel depletion region with the required boundary conditions at the source and drain end. The model is used to study the effect of triple‐material gate structure on the electrical performance of the device in terms of changes in potential and electric field. The device immunity against short‐channel effects is evaluated by comparing the relative performance parameters such as drain‐induced barrier lowering, threshold voltage roll‐off, and subthreshold swing with its counterparts in the single‐material DG and double‐material DG metal–oxide–semiconductor field‐effect transistors. The developed surface potential model not only provides device physics insight but is also computationally efficient because of its simple compact form that can be utilized to study and characterize the gate‐engineered devices. Furthermore, the effects of quantum confinement are analyzed with the development of a quantum‐mechanical correction term for threshold voltage. The results obtained from the model are in close agreement with the data extracted from numerical Technology Computer Aided Design device simulation. Copyright © 2015 John Wiley & Sons, Ltd.     

Impact of high‐κ gate dielectric and other physical parameters on the electrostatics and threshold voltage of long channel gate‐all‐around nanowire transistor

High‐κ gate‐all‐around structure counters the Short Channel Effect (SCEs) mostly providing excellent off‐state performance, whereas high mobility III–V channel ensures better on‐state performance, rendering III–V nanowire GAAFET a potential candidate for replacing the current FinFETs in microchips. In this paper, a 2D simulator for the III–V GAAFET based on self‐consistent solution of Schrodinger–Poisson equation is proposed. Using this simulator, capacitance–voltage profile and threshold voltage are characterized, which reveal that gate dielectric constant (κ) and oxide thickness do not affect threshold voltage significantly at lower channel doping. Moreover, change in alloy composition of In_xGa_1‐xAs, channel doping, and cross‐sectional area has trivial effects on the inversion capacitance although threshold voltage can be shifted by the former two. Although, channel material also affects the threshold voltage, most sharp change in threshold voltage is observed with change in fin width of the channel (0.005 V/nm for above 10 nm fin width and 0.064 V/nm for sub‐10 nm fin width). Simulation suggests that for lower channel doping below 10²³ m⁻³, fin width variation affects the threshold voltage most. Whereas when the doping is higher than 10²³ m⁻³, both the thickness and dielectric constant of the oxide material have strong effects on threshold voltage (0.05 V/nm oxide thickness and 0.01 V/per unit change in κ). Copyright © 2014 John Wiley & Sons, Ltd.     

Investigation of multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) sub‐50 nm MOSFET: A novel design

In this paper, a two‐dimensional (2D) analytical sub‐threshold model for a novel sub‐50 nm multi‐layered‐gate electrode workfunction engineered recessed channel (MLGEWE‐RC) MOSFET is presented and investigated using ATLAS device simulator to counteract the large gate leakage current and increased standby power consumption that arise due to continued scaling of SiO₂‐based gate dielectrics. The model includes the evaluation of surface potential, electric field along the channel, threshold voltage, drain‐induced barrier lowering, sub‐threshold drain current and sub‐threshold swing. Results reveal that MLGEWE‐RC MOSFET design exhibits significant enhancement in terms of improved hot carrier effect immunity, carrier transport efficiency and reduced short channel effects proving its efficacy for high‐speed integration circuits and analog design. Copyright © 2008 John Wiley & Sons, Ltd.     

Asymmetric halo and symmetric Single‐Halo Dual‐Material Gate and Double‐Halo Dual‐Material Gate n‐MOSFETs characteristic parameter modeling

This paper presents an analytical subthreshold surface potential model of novel structures called asymmetric pocket‐implanted Double‐Halo Dual‐Material Gate (DHDMG) and Single‐Halo Dual‐Material Gate (SHDMG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET), which combines the advantages of both the channel engineering (halo) and the gate engineering techniques (dual‐material gate) to effectively suppress the short‐channel effects (SCEs). The model is derived using the pseudo‐2D analysis by applying the Gauss's law to an elementary rectangular box in the channel depletion region, considering the surface potential variation with the channel depletion layer depth. The asymmetric pocket‐implanted model takes into account the effective doping concentration of the two linear pocket profiles at the source and the drain ends. The inner fringing field capacitances are also considered in the model for accurate estimation of the subthreshold surface potential at the two ends of the MOSFET. The same model is used to find the characteristic parameters for dual‐material gate with single‐halo and double‐halo implantations. It is concluded that the DHDMG device structure exhibits better suppression of the SCEs and the threshold voltage roll‐off than a pocket‐implanted and SHDMG MOSFET after investigating the characteristics parameter improvement. In order to validate our model, the modeled expressions have been extensively compared with the simulated characteristics obtained from the 2D device simulator DESSIS. A nice agreement is achieved with a reasonable accuracy over a wide range of device parameter and bias condition. Copyright © 2012 John Wiley & Sons, Ltd.     

NEGF simulations of the effect of strain on scaled double gate nanoMOSFETs

The effect of biaxial strain on double gate (DG) nanoscaled Si MOSFET with channel lengths in the nanometre range is investigated using Non-Equilibrium Green’s Functions (NEGF) simulations. We have employed fully 2D NEGF simulations in order to answer the question at which body thickness the effects of strain is masked by the confinement impact. Following ITRS, we start with a 14 nm gate length DG MOSFET having a body thickness of 9 nm scaling the transistors to gate lengths of 10, 6 and 4 nm and body thicknesses of 6.1, 2.6 and 1.3 nm. The simulated I _D–V _G characteristics show a 6% improvement in the on-current for the 14 nm gate length transistor mainly due to the energy separation of the Δ valleys. The strain effect separates the 2 fold from the 4 fold valleys thus keeping mostly operational transverse electron effective mass in the transport direction. However, in the device with an extreme body thickness of 1.3 nm, the strain effect has no more impact on the DG performance because the strong confinement itself produces a large energy separation of valleys.     

An efficient neural network approach for nanoscale FinFET modelling and circuit simulation

The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano‐circuit simulation. The FinFET used in this work is designed using careful engineering of source–drain extension, which simultaneously improves maximum frequency of oscillation ƒ_max because of lower gate to drain capacitance, and intrinsic gain A_V0 = g_m/g_ds, due to lower output conductance g_ds. The framework for the ANN‐based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current I_d on drain–source V_ds and gate–source V_gs is derived by a simple two‐layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low‐noise amplifier. At low power (J_ds∼10 µA/µm) improvement was observed in both third‐order‐intercept IIP₃ (∼10 dBm) and intrinsic gain A_V0 (∼20 dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first‐order to third‐order derivative of I_d with respect to gate voltage and lower g_ds in FinFET compared to bulk MOSFET. Copyright © 2009 John Wiley & Sons, Ltd.     

Device circuit co‐design to reduce gate leakage current in VLSI logic circuits in nano regime

In this paper, nanoscale metal–oxide–semiconductor field‐effect transistor (MOSFET) device circuit co‐design is presented with an aim to reduce the gate leakage curren t in VLSI logic circuits. Firstly, gate leakage current is modeled through high‐k spacer underlap MOSFET (HSU MOSFET). In this HSU MOSFET, inversion layer is induced in underlap region by the gate fringing field through high‐k dielectric (high‐k) spacer, and this inversion layer in the underlap region acts as extended source/drain region. The analytical model results are compared with the two‐dimensional Sentaurus device simulation. Good agreement is obtained between the model and Sentaurus simulation. It is observed that modified HSU MOSFET had improved off current, subthreshold slope, and drain‐induced barrier lowering characteristics. Further, modified HSU MOSFET is also analyzed for gate leakage in generic logic circuits. Copyright © 2015 John Wiley & Sons, Ltd.     

Wide‐band aperture array using a four‐channel manifold‐type planar multiplexer and digital 2‐D IIR filterbank

Emerging wide‐band communications and spectrum‐sensing systems demand support for multiple electronically scanned beams while maintaining a frequency independent, constant far‐field beam width. Realizing existing phased‐array technology on a digital scale is computationally intensive. Moreover, digitizing wide‐band signals at Nyquist rate requires complex high‐speed analog‐to‐digital converters (ADCs), which is challenging for real developments driven by the current ADC technology. A low‐complexity alternative proposed in this paper is the use of radio‐frequency (RF) channelizers for spectrum division followed by sub‐sampling of the RF sub‐bands, which results in extensive reduction of the necessary ADC operative frequency. The RF‐channelized array signals are directionally filtered using 2‐D digital filterbanks. This mixed‐domain RF/digital aperture array allows sub‐sampling, without utilizing multi‐rate 2‐D systolic arrays, which are difficult to realize in practice. Simulated examples showing 14–19 dB of rejection of wide‐band interference and noise for a processed bandwidth of 1.6 GHz are demonstrated. The sampling rate is 400 MHz. The proposed VLSI hardware uses a single‐phase clock signal of 400 MHz. Prototype hardware realizations and measurement using 65‐nm Xilinx field‐programmable gate arrays, as well as Cadence RTL synthesis results including gate counts, area‐time complexity, and dynamic power consumption for a 45‐nm CMOS circuit operating at B _DC = 1.1 V, are presented. Copyright © 2016 John Wiley & Sons, Ltd.     

Development of gate drive circuit for next‐generation ultrahigh‐speed switching devices

This paper describes a gate drive circuit which is capable of driving an ultrahigh‐speed switching device and of suppressing high‐frequency noise caused by its high dV/dt ratio of 104 V/μs order. SiC (silicon carbide)‐based power semiconductor devices are very promising as next‐generation ultrahigh‐speed switching devices. However, one of their application problems is how to drive them with less high‐frequency noise without sacrificing their ultrahigh‐speed operation capability. The paper proposes a new gate drive circuit specialized for such devices, which charges and discharges the input capacitance of the device by using an impulse voltage generated by inductors. This ultrahigh‐speed switching operation causes a high‐frequency common‐mode noise current in the gate drive circuit, which penetrates an isolated power‐supply transformer due to the parasitic capacitance between the primary and the secondary windings. In order to overcome this secondary problem, a toroidal multicore transformer is also proposed in the paper in order to reduce the parasitic capacitance drastically. By applying the former technique, the turn‐on time and turn‐off time of the power device were shortened by 50% and by 20%, compared with a conventional push‐pull gate drive circuit, respectively. In addition, the latter technique allows reduction of the peak common‐mode noise current to 25%, compared with the use of a conventional standard utility power‐supply transformer. © 2011 Wiley Periodicals, Inc. Electr Eng Jpn, 176(4): 52–60, 2011; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21124     

67 GHz three‐spiral transformer CMOS oscillator

This paper presents a 67GHz LC oscillator exploiting a three‐spiral transformer and implemented in 65nm bulk complementary metal–oxide–semiconductor technology by STMicroelectronics. The three‐spiral transformer allows operating with a lower voltage supply, still obtaining good phase noise performance, and achieving a compact design. Measured performances when supplied with 1.2 V are: oscillation frequency of 67 GHz, phase noise (PN) equal to ?96 dBc/Hz at 1 MHz frequency offset from the carrier, power consumption (P_C) equal to 19.2 mW and figure of merit (FOM) equal to ?179.7 dB/Hz. Measured performances when supplied with 0.6 V are: oscillation frequency of 67 GHz; PN equal to ?88.7 dBc/Hz at a 1 MHz frequency offset from the carrier; P_C equal to 3.6 mW and FOM equal to ?179.7 dB/Hz. Copyright © 2016 John Wiley & Sons, Ltd.     

A low‐power delay stage ring VCO based on wrap‐gate CNTFET technology for X‐band satellite communication applications

Over the past few years, with lower power consumption, reasonable layout area, and the ease of integration with standard circuit design technologies compared to the other counterparts, delay stage ring voltage‐controlled oscillators (VCOs) have been in the limelight of microelectronics scientists. However, few efforts have focused on representing high‐performance delay stage ring VCOs in the deep nanometric regime. In this regard, by virtue of outstanding electrical properties of carbon nanotube wrap‐gate transistors, this work aims to propose a carbon nanotube field‐effect transistor (CNTFET)–based delay stage ring VCO. After performing rigorous simulations, the proposed ring VCO which has been designed by 10‐nm gate‐all‐around (GAA) CNTFET technology shows suitable electrical performance metrics. The simulation results demonstrate that the proposed GAA‐CNTFET‐based ring VCO consumes 85.176 μW at with a 6.12‐ to 10.42‐GHz frequency tuning range. At the worst‐case noise conditions, the proposed design presents ‐90.747 dBc/Hz phase noise at 1 MHz offset frequency. With occupying 1.414 μm² physical area, the proposed VCO is appropriate for the ultracompact nanoscale radio frequency apparatus. Our simulation results accentuate that with further improvements and commercializing the fabrication techniques for CNTFET transistors, the proposed GAA‐CNTFET‐based VCO can be considered as a potential candidate for X‐band satellite communication applications.     

Threshold voltage modeling for dual‐metal quadruple‐gate (DMQG) MOSFETs

In this paper, a three‐dimensional (3D) model of threshold voltage is presented for dual‐metal quadruple‐gate metal‐oxide‐semiconductor field effect transistors. The 3D channel potential is obtained by solving 3D Laplace's equation using an isomorphic polynomial function. Threshold voltage is defined as the gate voltage, at which the integrated charge (Q_inv) at the ‘virtual‐cathode’ reaches to a critical charge Q_th. The potential distribution and the threshold voltage are studied with varying the device parameters like gate metal work functions, channel cross‐section, oxide thickness, and gate length ratio. Further, the drain‐induced barrier lowering has also been analyzed for different gate length ratios. The model results are compared with the numerical simulation results obtained from 3D ATLAS device simulation results. Copyright © 2015 John Wiley & Sons, Ltd.     

Single‐Stage ZVS‐PWM AC‐AC Power Converter Using All SiC Power Module for High‐Frequency Induction Heating Applications

This paper presents a novel prototype of a single‐stage zero voltage soft‐switching pulse‐width modulation ‐controlled ac‐ac converter with a silicon carbide (SiC)‐MOSFET/SiC‐SBD power module for high‐frequency (HF) induction heating (IH) applications. The newly developed ac‐ac converter can achieve higher efficiency than a Si‐IGBT/Si‐PN diode power module‐based prototype due to a low ON‐resistance of SiC‐MOSFET and a low forward voltage of SiC‐SBD under the condition of HF switching. The performances of the new prototype converter are evaluated by experiment with a single‐phase IH utensil of ferromagnetic stainless metal, after which the high‐efficiency and low switching noise characteristics due to the all SiC power module are actually demonstrated.     

A numerical simulation tool for nanoscale ion‐sensitive field‐effect transistor

In this work, a self‐contained numerical simulation tool for nanoscale Ion‐Sensitive Field‐Effect Transistor (ISFET) is developed. The tool is based on merging nanoscale ballistic MOSFET analytical equations with the Gouy–Chapman–Stern model equations of ISFET to form a system of nonlinear equations that can be solved iteratively to yield ISFET output current. The numerical solution is accomplished using Newton–Raphson method with efficient trust‐region‐dogleg algorithm using MATLAB software coding. The tool is used to optimize the sensitivity and linearity of nanoscale ISFETs, and to study their dependence on reference voltage, drain current level, and gate‐insulator thickness. Moreover, a comparison between three types of insulators, SiO₂, Si₃N₄, and Al₂O₃, has been made. The tool is given the name: NIST (Nanoscale ISFET Simulation Tool). It can be used as a guide for design and optimization of nanoscale ISFETs and can be applied for both single‐gate and double‐gate structures. Copyright © 2016 John Wiley & Sons, Ltd.     

Uncoupled mode space approach for analysis of nanoscale strained junctionless double-gate MOSFET

In this paper, we have analyzed the electrical characteristics of Strained Junctionless Double-Gate MOSFET (Strained JL DG MOSFET). A quantum mechanical transport approach based on non-equilibrium Green’s function (NEGF) method with the use of uncoupled mode space approach has been employed for this analysis. We have investigated the effects of high-\(\kappa \) materials as gate and spacer dielectrics on the device performance. Low OFF-state current, low DIBL, and low subthreshold slope have been obtained with increase in the gate and spacer dielectric constants. The electrical characteristics of strained JL DG MOSFET have also been compared with conventional JL DG MOSFET and Inversion Mode (IM) DG MOSFET. The results indicated that the Strained JL DG MOSFET outperforms the conventional JL and IM DG MOSFETs, yielding higher values of drain current.