Nanoscale germanium MOS Dielectrics-part II: high-/spl kappa/ gate dielectrics

In this paper, atomic layer deposition (ALD) and ultraviolet ozone oxidation (UVO) of zirconium and hafnium oxides are investigated for high-/spl kappa/ dielectric preparation in Ge MOS devices from the perspectives of thermodynamic stability and electrical characteristics. Prior to performing these deposition processes, various Ge surface preparation schemes have been examined to investigate their effects on the resulting electrical performance of the Ge MOS capacitors. Interfacial layer-free ALD high-/spl kappa/ growth on Ge could be obtained; yet, insertion of a stable interfacial layer greatly enhanced the electrical characteristics but with a compromise for equivalent dielectric thickness scalability. On the other hand, interfacial layer-free UVO high-/spl kappa/ growth on Ge was demonstrated with minimal capacitance-voltage hysteresis and sub-1.0-nm capacitance equivalent thickness. Finally, the leakage conduction and scalability of these nanoscale Ge MOS dielectrics are discussed and are shown to outperform their Si counterparts.     

MOS characteristics of ultrathin NO-grown oxynitrides

In this paper, we report for the first time, the growth of high quality ultrathin oxynitrides formed by nitridation of SiO₂ in nitric oxide (NO) ambient using in-situ rapid thermal processing (RTP). This process is highly self-limited compared with N₂O oxidation of silicon. A significant improvement in the interface endurance and charge trapping properties, under constant current stress, compared to pure O₂-grown and N₂O-grown oxides is observed. The NO growth process will have a great impact on future CMOS and EEPROM technologies     

MOS characteristics of NO-grown oxynitrides on n-type 6H-SiC

The growth of high-quality thin oxynitrides in nitric oxide (NO) ambient on n-type 6H-SiC substrate is reported. The performance and reliability of NO-grown oxynitride are compared with those of NO-annealed, N₂O-grown, N₂O-annealed and N₂-annealed oxides. NO-grown device shows the best interfacial properties and oxide reliability among all the samples. X-ray photoelectron spectroscopy analysis indicates the highest nitrogen pileup at the SiO₂/SiC interface of NO-grown sample. Therefore, the best performance of NO-grown sample can be related to the fact that oxide growth in NO has the advantage of providing higher nitrogen accumulation at the SiO₂/SiC interface and in the oxide bulk than the other growth techniques.     

纳米MOS器件的设计模型

几十年来,MOS器件一直遵循摩尔定律不断发展,对于缩小到纳米尺度的MOS器件,量子效应更加突出。研究纳米尺度MOS器件的物理问题,以及适用于纳米MOS器件的设计已成为当前微电子领域重要研究内容。本文简要介绍和评述了纳米MOS器件的设计模型．并对基于非平衡态格林函数以及薛定谔方程和泊松方程自洽解的器件模型应用进行了举例说明。     

减少纳米MOS器件栅电流的研究分析

采用Schroedinger-Poisson方程自洽全量子求解法研究了MOS器件不同介质材料和栅结构栅电流,该模型对栅电流中的三维电流成分用行波统一地计算;对二维栅电流成分通过反型层势阱中准束缚态的隧穿率计算。模拟得出栅极电流与实验结果符合。研究结果表明,采用高愚栅介质材料、p-MOSFET或双栅结构对栅电流的减少有明显的作用,这一结果可望对器件性能作出预计并对其研制提供指导。     

Scalability and electrical properties of germanium oxynitride MOS dielectrics

In this letter, we present a fundamental study on the scalability and electrical properties of germanium oxynitride dielectrics for metal-oxide-semiconductor device applications. The nitrogen depth profile within the oxynitride dielectric layers was first monitored using angle-resolved x-ray photoemission spectroscopy and the dielectric permittivity variation was therefore identified. After thinning down the lower permittivity portion of these dielectrics, we successfully scaled down the capacitance-based equivalent SiO/sub 2/ thickness, in Ge MOS capacitors, to 1.9 nm without suffering from gate leakage. We have also investigated the effects of thermal annealing on various capacitor electrical properties. For instance, we measured a flat-band voltage shift of as much as -0.8 V from the ideal value on as-deposited capacitors and the recovery of the theoretical value, with acceptably small amount of oxide fixed charge, after subsequent thermal annealing. Lastly, we have benchmarked the performance of these oxynitride insulators with the advanced high-/spl kappa/ dielectrics on Ge and discussed the impacts on future scaling.     

Nanoscale electrical characterization of ultrathin high-k dielectric MOS stacks: A conducting AFM study

Extreme scaling in both silicon and alternative channel CMOS has highlighted the importance of localized characterization on the nanometer scale. We have used a conductive-contact atomic force microscopy (C-AFM) technique in ultra high vacuum (UHV) conditions to analyze and compare intrinsic stack degradation mechanisms leading to breakdown (BD) for ultrathin high-k dielectric films of (4 nm) Hf_xSiO_y/SiO₂ on Si and (2 nm) ZrO₂/GeO₂ on Ge. Simultaneous nanoscale current–voltage I–V characteristics, topography, tunneling current and relative tip–surface contact interactions as normal and lateral force maps revealed localized injected charge dependence on electrical stress. It is shown that the charge can propagate laterally. Successive voltage scanning is related to the overall post-BD conductivity for pre- to post-BD degradation propagation. In contrast with SiO₂ interface, an increased GeO₂ interlayer reactivity yielding more active interface defects is suggested.     

氮化硅扩散阻挡层在采用HfON栅介质的Ge MOS 电容中的作用

MOS capacitors with hafnium oxynitride（HfON）gate dielectrics were fabricated on Ge and Si substrates using the RF reactive magnetron sputtering method.A large amount of fixed charges and interface traps exist at the Ge/HfON interface.HRTEM and XPS analyses show that Ge oxides were grown and diffused into HfON after post metal annealing.A Si nitride interfacial layer was inserted between Ge and HfON as diffusion barrier.Using this method,well behaved capacitance–voltage and current–voltage characteristics were obtained.Finally hystereses are compared under different process conditions and possible causes are discussed.     

Effects of silicon nitride diffusion barrier on germanium MOS capacitors with HfON gate dielectrics

MOS capacitors with hafnium oxynitride (HfON) gate dielectrics were fabricated on Ge and Si substrates using the RF reactive magnetron sputtering method. A large amount of fixed charges and interface traps exist at the Ge/HfON interface. HRTEM and XPS analyses show that Ge oxides were grown and diffused into HfON after post metal annealing. A Si nitride interfacial layer was inserted between Ge and HfON as diffusion barrier. Using this method, well behaved capacitance-voltage and current-voltage characteristics were obtained. Finally hystereses are compared under different process conditions and possible causes are discussed.     

Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices

In this paper, the optimization issues of various drain-extended devices are discussed for input/output applications. The mixed-signal performance, impact of process variations, and gate oxide reliability of these devices are compared. Lightly doped drain MOS (LDDMOS) was found to have a moderate performance advantage as compared to shallow trench isolation (STI) and non-STI drain-extended MOS (DeMOS) devices. Non-STI DeMOS devices have improved circuit performance but suffer from the worst gate oxide reliability. Incorporating an STI region underneath the gate–drain overlap improves the gate oxide reliability, although it degrades the mixed-signal characteristics of the device. The single-halo nature of DeMOS devices has been shown to be effective in suppressing the short-channel effects.      

Simulation of properties of the channels of silicon MOS transistors on the deforming germanium substrate

The influence of tension deformation on the electrical parameters of semiconductor films of crystalline silicon is considered. The influence of the ratio of thicknesses of the film and deforming germanium substrate on the shift of energy bands and variation in the mobility of free charge carriers is taken into account. The dependence of resistance of the strained anisotropic n-channel of the field-effect transistor on the size of current contacts and the value of the deformation is obtained and analyzed. It is shown that resistance of the strained silicon channel of the field-effect transistor in the open state is determined not only by its sizes and electrical parameters but also by the thickness of the deforming substrate and by the sizes of current contacts.     

Atomic layer deposition of high-/spl kappa/ dielectric for germanium MOS applications - substrate

In this letter, we present the use of atomic layer deposition (ALD) for high-/spl kappa/ gate dielectric formation in Ge MOS devices. Different Ge surface cleaning methods prior to high-/spl kappa/ ALD have been evaluated together with the effects on inserting a Ge oxynitride (GeO/sub x/N/sub y/) interlayer between the high-/spl kappa/ layer and the Ge substrate. By incorporating a thin GeO/sub x/N/sub y/ interlayer, we have demonstrated excellent MOS capacitors with very small capacitance-voltage hysteresis and low gate leakage. Physical characterization has also been done to further investigate the quality of the oxynitride interlayer.     

Fundamental limitations in microelectronics—I. MOS technology

The physical phenomena which will ultimately limit MOS circuit miniaturization are considered. It is found that the minimum MOS transistor size is determined by gate oxide breakdown and drain-source punch-through. Other factors which limit device size are drain-substrate breakdown, drain ‘corner’ breakdown and substrate doping fluctuations. However these limitations are less severe than the oxide breakdown limitation mentioned above. Power dissipation and metal migration limit the frequency and/or packing density of fully dynamic and of complementary MOS circuits. In static non-complementary circuits, power dissipation is the principal limitation of the number of circuit functions per chip. The channel length of a minimum size MOS transistor is a factor of 10 smaller than that of the smallest present day devices. The tolerances required to manufacture such a transistor are compatible with electron beam masking techniques. It is thus possible to envision fully dynamic silicon chips with up to 10⁷–10⁸ MOS transistors per cm².     

Si interlayer passivation on germanium MOS capacitors with high-/spl kappa/ dielectric and metal gate

We have demonstrated the advantages of silicon interlayer passivation on germanium MOS devices, with CVD HfO/sub 2/ as the high-/spl kappa/ dielectric and PVD TaN as the gate electrode. A silicon interlayer between a germanium substrate and a high-/spl kappa/ dielectric, deposited using SiH/sub 4/ gas at 580/spl deg/C, significantly improved the electrical characteristics of germanium devices in terms of low D/sub it/ (7/spl times/10/sup 10//cm/sup 2/-eV), less C- V hysteresis and frequency dispersion. Low leakage current density of 5/spl times/10/sup -7/ A/cm/sup 2/ at 1 V bias with EOT of 12.4 /spl Aring/ was achieved. Post-metallization annealing caused continuing V/sub fb/ positive shift and J/sub g/ increase with increased annealing temperature, which was possibly attributed to Ge diffusion into the dielectric during annealing.     

Impact ionization MOS (I-MOS)-Part I: device and circuit simulations

One of the fundamental problems in the continued scaling of transistors is the 60 mV/dec room temperature limit in the subthreshold slope. In part I this work, a novel transistor based on the field-effect control of impact-ionization (I-MOS) is explored through detailed device and circuit simulations. The I-MOS uses gated-modulation of the breakdown voltage of a p-i-n diode to switch from the OFF state to the ON state and vice-versa. Device simulations using MEDICI show that the I-MOS has a subthreshold slope of 5 mV/dec or lower and I/sub ON/>1 mA//spl mu/m at 400 K. Simulations were used to further explore the characteristics of the I-MOS including the transients of the turn-on mechanism, the short-channel effect, scalability, and other important device attributes. Circuit mode simulations were also used to explore circuit design using I-MOS devices and the design of an I-MOS inverter. These simulations indicated that the I-MOS has the potential to replace CMOS in high performance and low power digital applications. Part II of this work focuses on I-MOS experimental results with emphasis on hot carrier effects, germanium p-i-n data and breakdown in recessed structure devices.     

Degradation of oxides and oxynitrides under hot hole stress

The impact of nitridation on hot hole injection and the induced degradation is quantitatively studied by comparing the behavior of a control oxide and oxynitrides. The oxynitride is prepared by either annealing the oxide in N₂O or growing directly in N₂ O. The pMOSFET's are uniformly stressed by using the substrate hot hole injection technique. The physical quantities analyzed include the hole injection current, the density of created interface states and the density of trapped holes. It is found that a 30 min annealing in N₂ O at 950°C can enhance the effective barrier for hole injection by 0.6 eV. However, the interface state generation during the injection is insensitive to nitridation. The continuing degradation post the hole injection is also investigated. This includes a poststress interface state build-up and the generation of new precursors for interface states. The nitridation reduces the poststress degradation considerably. Where it is necessary, the hole induced degradation is compared with that induced by electrons. The applicability of the models proposed for oxynitrides to the present results is examined     

Neuron MOS binary-logic integrated circuits. I. Design fundamentalsand soft-hardware-logic circuit implementation

Described are the fundamental design principles for binary-logic circuits using a highly functional device called the neuron MOS transistor (νMOS), a single MOS transistor simulating the function of biological neurons. To facilitate logic design employing this transistor, a graphical technique called the floating-gate potential diagram has been developed. It is shown that any Boolean functions can be generated using a common circuit configuration of two-stage νMOS inverters. One of the most striking features of νMOS binary-logic application is the realization of a so-called soft hardware logic circuit. The circuit can be made to represent any logic function (AND, OR, NAND, NOR, exclusive-NOR, exclusive-OR, etc.) by adjusting external control signals without any modifications in its hardware configuration. The circuit allows real-time reconfigurable systems to be built. Test circuits were fabricated by a double-polysilicon CMOS process and their operation was experimentally verified     

Comparing the ocean color measurements between MOS and SeaWiFS: avicarious intercalibration approach for MOS

The Modular Optoelectronic Scanner (MOS) was launched in the spring of 1996 on the Indian IRS-P3 satellite. With the successful launch of NASA's Sea-viewing Wide Field of-view Sensor (SeaWiFS) in the summer of 1997, there are now two ocean color missions in concurrent operation, and there is interest to compare data from these two sensors. In this paper, we describe our efforts to retrieve ocean-optical properties from both SeaWiFS and MOS using consistent methods. We first briefly review the atmospheric correction, which removes more than 90% of the observed radiances in the visible, and then we describe how the atmospheric-correction algorithm used for the SeaWiFS data can be modified for application to other ocean color sensors. Next, since the retrieved water-leaving radiances in the visible between MOS and SeaWiFS are significantly different, we developed a vicarious intercalibration method to recalibrate the MOS spectral bands based on the optical properties of the ocean and atmosphere derived from the coincident SeaWiFS measurements. Furthermore, because of the strange calibration behavior of the MOS 750 nm band, we modified the atmospheric correction such that the MOS 685 and 868 nm bands can also be used. We present and discuss the MOS-retrieved, ocean-optical properties before and after the vicarious calibration using both the MOS 685 and 750 nm coupled with 868 nm bands in comparison with results from SeaWiFS and demonstrate the efficacy of this approach. We show that it is possible and efficient to vicariously intercalibrate sensors between one and another     

Re-oxidation characteristics of oxynitrides on 3C- and 4H-SiC

N₂O annealing of oxides in both Si and SiC is known to result in a similar accumulation of nitrogen at the semiconductor-oxide interface, but the reoxidation of oxynitrides is different in these materials. With Si, the nitrogen at the interfl￡e is unaffected upon re-oxidation even under high oxidant flow conditions. With SiC, as shown in this paper, complete depletion of the nitrogen from the interface is observed with the re-oxidation of SiC oxynitrides for both 3C and 4H polytypes. The depletion of the nitrogen from the interface is strongly dependent on the re-oxidation temperature. Results are described and a possible mechanism proposed.     

Single transistor MOS RAM using a short-channel MOS transistor

The relationship between sensitivity and other factors in the sense circuit of a single transistor MOS RAM has been investigated by computer simulation. An expression for sensitivity of the sense circuit has been derived. It suggests key points to increase the sensitivity of the sense circuit. A new sense circuit that defects a signal less than /spl plusmn/30 mV and has low power capability 50 /spl mu/W/circuit is realized by following the suggestions. The high performance of the proposed sense circuit has been verified through the fabrication of a 1K MOS RAM. Fine pattern technology, such as 2-/spl mu/m minimum pattern width and spacing and 500-/spl Aring/ gate oxide thickness, has been adopted. The threshold voltage of the MOS transistor is 0.8 V and dc supplies are 7 V and /spl plusmn/2 V. This 1K RAM has characteristics of 80-ns access time, 150-ns cycle time, and 30-mW power dissipation.