IC vs VBE law in double diffused bipolar transistors

It is shown that non-unity values for m in the I_C = _co exp (V_BE/mV_t) law for double diffused transistors can be caused by the graded emitter base junction. A simple analytic expression is derived for the linearly graded case. Tabulated results are given for this case and for measured and computed results on an actual double diffused transistor.     

Extrapolated fmax of heterojunction bipolar transistors

It is shown that the extrapolated f_max of heterojunction bipolar transistors (HBT's) can be written in the form f _max=√f_T/8π(RC)_eff, where f_T is the common-emitter, unity-current-gain frequency, and where (RC)_eff is a general time constant that includes not only the effects of the base resistance and collector-base junction capacitance, but also the effects of the parasitic emitter and collector resistances, and the dynamic resistance 1/g_m, where g_m is the transconductance. Simple expressions are derived for (RC) _eff, and these are applied to two state-of-the-art devices recently reported in the literature. It is demonstrated that, in modern HBT's, (RC)_eff can differ significantly from the effective base-resistance-collector-capacitance product conventionally assumed to determine f_max     

Low frequency conductance voltage analysis of Si/GexSi1-x/Si heterojunction bipolar transistors

Low-frequency-conductance-voltage (LFGV) method for analysis of heterojunction bipolar transistors (HBTs) is presented. The method gives accurate quantitative values for the important minority-carrier transport parameters that underlie the transistor performance, such as the base diffusion length, lifetime, diffusion coefficient and transit time. The method also allows a detailed analysis of the current gain and emitter injection efficiency. The analytical model and experimental methodology are demonstrated for a Si/Ge_xSi_1-x/Si HBT with a trapeziodal and linearly graded Ge profiles in the base. The LFGV method is general and can be applied to other bipolar transistors, including those based on III-V materials     

Electrical method for measuring emitter depth of shallow bipolar transistors

A simple electrical method of measuring the emitter depth of bipolar transistors is presented, and is validated by comparison with SIMS profiles. Good agreement is obtained with the SIMS technique for emitter depths of >1000 AA, but for shallower emitters the electrical method is shown to be more accurate.<>     

Method for determining the emitter and base series resistances of bipolar transistors

A simple method for determining both the emitter and the base series resistances of bipolar transistors from the measured I - V characteristics is described. The method is based on the observation that deviation of the base current from the idealexp (qV_{BE}/kT)behavior at high currents can be attributed solely and relatively simply to series resistances. Series resistances determined by this method are given for sample high-speed digital bipolar transistors.     

High-speed frequency dividers using self-aligned AlGaAs/GaAs heterojunction bipolar transistors

A divide-by-four frequency divider and ring oscillators have been fabricated employing self-aligned AlGaAs/GaAs heterojunction bipolar transistors (HBT's). Maximum toggle frequency of 13.7 GHz and propagation delay time of 17.2 ps are achieved in ECL gate circuitry. These values are the highest and the lowest in ECL circuits and in bipolar circuits, respectively, ever reported.     

Collector-base capacitance of high frequency integrated bipolar transistors

A method of obtaining the correct emitter junction capacitance Cb'e from the measured device parameters is presented. This method is shown to apply to integrated bipolar transistors having fT ? 2.5 GHz.     

Materials characterization of WNxCy, WNx and WCx films for advanced barriers

A ternary WN_xC_y system was deposited in a thermal ALD (atomic layer deposition) reactor from ASM at 300 °C in a process sequence using tungsten hexafluoride (WF₆), triethyl borane (TEB) and ammonia (NH₃) as precursors. The WC_x layers were deposited by a novel ALD process at a process temperature of 250 °C. The WN_x layers were deposited at 375 °C using bis(tert-butylimido)-bis-(dimethylamido)tungsten (^tBuN)₂(Me₂N)₂W (imido-amido) and NH₃ as precursors. WN_x grows faster on plasma enhanced chemical vapor deposition (PECVD) oxide than WC_x does on chemical oxide. WN_xC_y grows better on PECVD oxide than on thermal oxide, which is opposite of what is seen for WN_x. In the case of the ternary WN_xC_y system, the scalability towards thinner layers and galvanic corrosion behavior are disadvantages for the incorporation of the layer into Cu interconnects. ALD WC_x based barriers have a low resistivity, but galvanic corrosion in a model slurry solution of 15% peroxide (H₂O₂) is a potential problem. Higher resistivity values are determined for the binary WN_x layers. WN_x shows a constant composition and density throughout the layer.     

A new way for measuring the apparent band gap narrowing in bipolar transistors

This paper describes a new way for measuring the apparent band gap narrowing in bipolar transistors with Si base or epitaxial Si_0.80Ge_0.20 base from the temperature dependence of the collector current J_C(T). A graph of ln J_C as a function of V_BE is plotted based on the data extracted from the linear region of the Gummel plot as the temperature is kept as a constant. We have obtained two lines of ln J_C–V_BE at temperature, 300 and 77 K, respectively. From the intersection point of the lines we can calculate the values of band gap narrowing in Si and Si_0.80Ge_0.20 bases, which are 41 and 151 meV, respectively. The results are in good agreement with the measured values in reference.     

An analytical model for determining carrier transport mechanism of polysilicon emitter bipolar transistors

An analytical model is proposed by including carrier transport mechanisms which previous unified analytical models do not consider: minority carrier combination at both sides of polysilicon-silicon interfacial oxides and thermionic emission over segregation potential barriers for determining the precise carrier transport mechanisms which govern current gain and specific emitter interfacial resistivity. This approach allows us to gain an insight into carrier transport mechanisms and provides a distinct image for polysilicon emitter bipolar devices. With the consideration of the interfacial capture cross section as a function of temperature, the dependence of current gain for devices given an HF etch prior to polysilicon deposition on temperature is first explained successfully. For improving device performance, some directive suggestions are presented.<>     

The ƒT of bipolar transistors with thin lightly doped bases

The ?_T of a bipolar transistor is normally increased by decreasing the base doping density and width. At very small widths and densities this improvement may not occur because injection modulation of the base charge at normal operating currents then increases emitter junction resistance, r_e, and so makes the emitter time constant, r_e. C_te, larger. Simple expressions are given for r_e and ?_T in this situation and the theory is compared with measurements on sets of transistors in which ?_T is found to be largely independent of impurity charge in the base.     

Analytical relations for determining the base transit times and forward-biased junction capacitances of bipolar transistors

Analytical expressions for determining the base transit times and the forward-biased junction capacitances of bipolar transistors are derived from a detailed small signal analysis of the Gummel-Poon transistor model. Results presented in this paper indicate that these expressions are significantly more accurate than commonly used expression described elsewhere.     

Model for 1/f; noise in MOS transistors biased in the linear region

1/f; Noise calculations and experiments are presented for conductance fluctuations in inversion layers. The layers are biased in the ohmic region at very low drain-source voltages. The model makes use of an experimental fact that competing scattering mechanisms other than lattice scattering lead to a reduction of 1/f; noise, but does not consider trapping of charge carriers in surface states as the source of 1/f; noise. The free charge carrier distribution and a mobility profile play an important part in the model. The model describes the measured results well. A reduction of the effective mobility with increasing gate voltage is accompanied by a strong reduction of the noise.     

InP/InGaAs double-heterojunction bipolar transistors for high-speedoptical receivers

We fabricated monolithically integrated pin/HBT photoreceivers using FPIGA (full-potential InGaAs) DHBT's with various collector thicknesses. An HBT figure-of-merit was deduced from the relationship between measured bandwidths of the preamplifiers and the f_T's and f_max's of the DHBT's. A phenomenological device model of the DHBT's is proposed to find the optimum collector thickness that gives the highest bandwidth of the photoreceivers. Finally, we discuss the feasibility of monolithically integrating a pin-PD, preamplifier, buffer amplifier, and D-type flip-flop with an operating speed of 40 Gbit/s     

Phase-noise behaviour of frequency dividers implemented with GaAs heterojunction bipolar transistors

Near carrier phase-noise performance of GaAs microwave frequency dividers (4 GHz) is investigated. The divide-by-4 circuits are fabricated using heterojunction bipolar transistor (HBT) technology. The phase-noise behaviour of the HBT divider chips is correlated with transistor 1/f noise and is insensitive to bias current variations.     

On the leverage of high-fT transistors foradvanced high-speed bipolar circuits

A detailed study on the leverage of high-f_T transistors for advanced high-speed bipolar circuit applications is presented. It is shown that for the standard ECL (emitter-coupled logic) circuit, the leverage of high f_T is limited by the passive resistors (emitter-follower resistor and collector load resistor) and wire delay, especially in the low-power regime. For the standard NTL (nonthreshold logic) circuit, the leverage is higher due to its front-end configuration and lower power supply value. As the passive resistors are decoupled from the delay path in various advanced circuits utilizing active-pull-down schemes, the leverage of high F_T becomes more significant     

80 GHz 4:1 frequency divider IC using nonself-aligned InP/InGaAsheterostructure bipolar transistors

80 GHz operation has been attained for a divide-by-four frequency divider IC fabricated with non-self-aligned InP/InGaAs heterostructure bipolar transistors. To the authors' knowledge, this is the fastest digital frequency divider IC reported to date. The measured maximum toggle frequency of 80 GHz was the upper limit of the measurement setup