Effect of low and high temperature anneal on process-induced damageof gate oxide

We have investigated the ability of high and low temperature anneals to repair the gate oxide damage due to simulated electrical stress caused by wafer charging resulting from plasma etching, etc. Even 800°C anneal cannot restore the stability in interface trap generation. Even 900°C anneal cannot repair the deteriorated charge-to-breakdown and oxide charge trapping. As a small consolation, the ineffectiveness of anneal in repairing the process-induced damage allows us to monitor the damages even at the end of the fabrication process     

Rapid thermal oxidation of silicon for thin gate dielectric

Rapid thermal oxidation of silicon has been carried out in the temperature range 1000 to 1250°C for an oxidation time of 5 to 60 s. The new kinetics data show that oxidation is carried out by a two-energy activation process. Assuming linear growth during the first 5 s of fast oxidation, the first process occurs with an activation energy Ea of 0.9 eV. The second process takes place with Ea = 1.4 eV for linear growth kinetics from 5 to 60 s.     

Ultrathin aluminum oxide gate dielectric on N-type 4H-SiC prepared by low thermal budget nitric acid oxidation

MOS capacitors with an ultrathin aluminum oxide (Al/sub 2/O/sub 3/) gate dielectric were fabricated on n-type 4H-SiC. Al/sub 2/O/sub 3/ was prepared by room-temperature nitric acid (HNO/sub 3/) oxidation of ultrathin Al film followed by furnace annealing. The effective dielectric constant of k/spl sim/9.4 and equivalent oxide thickness of 26 /spl Aring/ are produced, and the interfacial layer and carbon clusters are not observed in this paper. The electrical responses of MOS capacitor under heating and illumination are used to identify the conduction mechanisms. For the positively biased case, the conduction mechanism is shown to be dominated by Schottky emission with an effective barrier height of 1.12/spl plusmn/0.13 eV. For the negatively biased case, the gate current is shown to be due to the generation-recombination process in depletion region and limited by the minority carrier generation rate. The feasibility of integrating alternative gate dielectric on SiC by a low thermal budget process is demonstrated.     

Time-dependent degradation of thin gate oxide under post-oxidation high-temperature anneal

Charge to breakdown QBDhas been used to evaluate the quality of thin gate oxides for some time. It is well known that the QBDof a thin oxide degrades with subsequent high-temperature thermal cycles. This paper reports on the time-dependent degradation of an 80-Å gate oxide at various post-oxidation annealing temperatures. An empirical relation was obtained asQ_{BD} propto exp (-A(T)t)where t is annealing time, T is annealing temperature, and A is the "rate constant" for the QBDdegradation. An Arrhenius plot of A versus 1/T yields an activation energy in the range of 6-7 eV. Also reported is the observation of an increase in QBDduring short annealing time which may be related to the relaxation of built-in stress induced during the oxidation process.     

Rapid thermal processing of thin gate dielectrics. Oxidation of silicon

A new rapid process for the growth of thin thermal oxide films on crystalline silicon is described. This rapid thermal oxidation (RTO) is performed in a controlled oxygen ambient with the heating provided by tungsten-halogen lamps. The resulting oxides with thicknesses from 40-130 Å have a uniformity of better than 2 percent across the 75-mm wafers. Oxidation times at 1150°C vary from 5 to 30 s. Typical breakdown fields of 100-Å oxide films were 13.8 MV/cm and typical midgap interface state densities were of the order of 1 × 10¹⁰eV^-1cm^-2. The present RTO films have characteristics equal to or better than furnace grown oxides and because of the short temperature-time cycle they have potential applications for submicrometer VLSI.     

Rapid thermal chemical vapor deposited oxides on N-type 6H-siliconcarbide

The electrical characteristics of oxides deposited on nitrogen doped N-type 6H-silicon carbide using rapid thermal chemical vapor deposition are reported. The gases used in the deposition process were silane (diluted with argon), and nitrous oxide. The oxide was found to have an interface state density of 7×10¹¹ cm^-2 eV^-1 and a low effective charge density of 1.1×10 ¹¹ cm^-2. The deposited oxide is compared with oxide grown thermally on N-type 6H-silicon carbide by wet oxidation. The quality of the deposited oxide is found to be comparable to the quality of the thermal oxide. An excellent low thermal budget process to obtain good oxides on N-type 6H-silicon carbide has thus been demonstrated for the first time     

Reliable fluorinated thin gate oxides prepared by liquid phasedeposition following rapid thermal process

A reliable fluorinated thin gate oxide prepared by liquid phase deposition (LPD) following rapid thermal oxidation (RTO) in O₂ or nitridation (RTN) in N₂O ambient was reported. Fluorine (F) atoms incorporated into the oxides during LPD process are found to be helpful to the improvement of oxide quality. It is observed that these fluorinated gate oxides show good properties in radiation hardness, charge to breakdown (Q_bd), and oxide breakdown field (E_ox) endurances. Interestingly, the Q_bd 's for the fluorinated gate oxides are 10 times larger than those for the gate oxides prepared by RTO in O₂ or RTN in N₂ O directly. Some of the E_ox's are even higher than 17 MV/cm for the samples investigated in this work     

Conduction mechanisms in thermal nitride and dry gate oxides grown on 4H-SiC

The charge conduction mechanisms in Metal-Oxide-Semiconductor (MOS) capacitors formed on n-type 4H-silicon carbide (SiC) using thermally grown silicon dioxide (SiO₂) as gate dielectrics are analyzed. The possible conduction mechanisms have been identified in the whole measurement range. At high electric fields, the charge conduction is dominated by Fowler–Nordheim tunneling. In addition, trap assisted tunneling and ohmic type conduction are considered to explain the cause of leakages detected at intermediate and low oxide electric fields. Various electronic parameters are extracted. The oxide breakdown strengths are higher than 8 MV/cm. Fowler–Nordheim tunneling barrier height was found to be 2.74 eV for nitride oxides and 2.54 eV for dry oxides at high electric field regions and the trap energy level extracted using trap assisted tunneling emission model was estimated to be about 0.3 eV for both oxides. The possible contribution of the Poole–Frenkel effect to the conduction mechanism was also considered, and it was found that it does not play a dominant role.     

Low-temperature and low thermal budget fabrication ofpolycrystalline silicon thin-film transistors

A top-gate self-aligned n-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) has been fabricated with low temperature (⩽550°C) and low thermal budget process. The ultrahigh vacuum chemical vapor deposition (UHV/CVD) grown poly-Si was served as the channel film, the chemical mechanical polishing (CMP) technique was used to polish the channel surface, plasma-enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide was used as the gate dielectric, and NH₃ plasma was used to passive the device. In this process, the solid phase crystallization (SPC) step is not needed. A field effect mobility of 46 cm²/V-s, ON/OFF current ratio of over 10⁷, and threshold voltage of 0.8 V are obtained. The significant reduction in process temperature and thermal budget make this process advantageous for larger-area-display peripheral driver circuits on glass substrate     

The effect of post-deposition thermal processing on MOS gate oxides formed by remote PECVD

The effects of post-deposition thermal exposure, at temperatures typical of MOS fabrication processes, on gate oxides formed by remote plasma enhanced chemical vapor deposition (RPECVD) is discussed. SiO₂ films were prepared by (1) thermal oxidation of silicon at temperatures from 700 to 1150° C, and (2) by RPECVD at a substrate temperature of 350° C. Post deposition thermal processing was achieved by rapid thermal annealing for 100 sec from 850–1200° C. Film properties were studied by infrared spectroscopy (IR), ellipsometry, and by measurements of stress, capacitance voltage characteristics, and dielectric breakdown. Post-formation, thermal processing in the range of 850–1200° C was shown to modify both thermally grown and deposited oxides, but it has been shown that RPECVD films could be stabilized against post-deposition changes by rapid thermal annealing at temperatures of about 900° C for periods of at least 100 sec.     

Formation of silicided,ultra-shallow junctions using low thermal budget processing

The tradeoffs involved in alternative processes for the formation of ultra shallow junctions are described. Low energy implantation, preamorphization to eliminate channeling and low thermal budget processing are adequate to form junctions that are 0.1 to 0.3μm deep. For junctions less than about 100 nm, however, the enhanced diffusion resulting from the amorphization implant reduces its benefits. Athermal diffusion can result in considerable junction motion even when low thermal budget processing is used. Junctions this shallow typically require silicide or metal cladding to reduce the sheet resistance; however, the dopant redistribution associated with siliciding pre-existing junctions increases the contact resistance which diminishes the potential benefit of silicidation. In addition, high leakage can result from excessive silicon consumption. While the use of silicide as a diffusion source can overcome some of the limitations of silicided junctions, this technique can be especially hindered by slow dopant diffusion or compound formation in the silicide and by the limited thermal stability of the silicide. One outstanding issue associated with silicide diffusion sources is understanding the seemingly enhanced diffusivity of dopant in the silicon.     

Novel interface nitridation process for thin gate oxides

A thin (100-200-Å) gate dielectric film which exhibits improved properties as compared to control pure thermal oxides is discussed. The film is obtained by thermal nitridation of the silicon wafers in pure ammonia, followed by high temperature oxide (HTO) deposition, and an anneal in oxygen ambient (reoxidation). It was found that these dielectrics exhibit excellent electrical characteristics under Fowler-Nordheim tunneling stress, such as a relatively large charge-to-breakdown considerable reduction in charge trapping, reduction of interface state generation, and a significantly improved resistance to transconductance degradation. The dielectric layer is of potential use for the fabrication of reliable ultrathin gate oxide films for standard CMOS technology and particularly for nonvolatile programmable memories     

Study of aluminum thermomigration as a low thermal budget technique for innovative power devices

The main feature of the thermomigration of Al/Si liquid droplets in silicon for the realization of isolation walls in bi-directional power devices is its low thermal budget. Therefore, it is compatible with the utilization of epitaxial substrates for innovative power devices, for example, with reduced on-state resistance. This paper describes the design and realization of a medium power SCR on epitaxy. After structure presentation and voltage blocking capability simulation, the specific issue of thermomigration on (1 1 1)-orientated epitaxial substrates is considered. Limitations to migration are found due to the off-axis cut necessary for good epitaxial growth. Electrical characterization exhibits great agreement with simulation, demonstrating the great potential of thermomigration as a low thermal budget technique for isolation walls processing for both standard structures and new devices on epitaxy.     

High-field stressing of LPCVD gate oxides

We have investigated gate oxide degradation as a function of high-field constant current stress for two types of oxides, viz. standard dry and LPCVD oxides. Charge injection was done from both electrodes, the gate and the substrate. Our results indicate that compared to dry oxides, LPCVD oxides show reduced charge trapping and interface state generation for inversion stress. The degradation in LPCVD oxides with constant current stress has been explained by the hydrogen model     

Alteration of gate oxides thickness for SOC level integration

The integration of entire system on a chip (SOC) is the major challenge for the semiconductor industries. The successful implementation of SOC will require innovation in both circuit design and fabrication technology. However, from a process technology point of view, it can be seen that in order to provide design flexibility each of the sub-system may require different gate oxide thicknesses. In this work, ¹⁹F⁺ implantation of variable doses on silicon is explored to achieve this goal. It has been observed that the differential oxide thickness can be achieved by varying the implanted dose of the fluorine on silicon, due to alteration in the oxidation rate. C–V and J–E characteristics are used to demonstrate the electrical behavior of fluorine implantation-based MOS devices. The stoichiometric composition analysis of dielectric materials is reported by FTIR measurements. The control over the oxide thickness, interface states, threshold voltage and stoichiometric composition of dielectric materials could play a vital role in the SOC level integration.     

A low thermal budget self-aligned Ti silicide technology usinggermanium implantation for thin-film SOI MOSFET's

In this paper, a titanium salicide technology with a very low thermal annealing temperature using germanium implantation for thin film SOI MOSFET's is investigated in detail. Ti silicide formation on the amorphous silicon generated by germanium implantation is studied. Compared to the conventional Ti salicide process, the Ti silicidation temperature is significantly lowered and the silicide depth is well controlled through the pre-amorphized layer. Therefore, the potential problems of the salicide process for SOI MOSFET's such as lateral voids, dopant segregation, thermal agglomeration, and increase of resistance on narrow gate are suppressed by germanium implantation. With the Ge pre-amorphization salicide process, a very low silicide contact resistance is obtained and sub-0.25-μm SOI MOSFET's are fabricated with good device characteristics     

Performance study of n-MOS natural transistor fabricated by low thermal budget process

Natural n-MOS transistor and MOS capacitor test structures have been fabricated by the low temperature process design for better control on device dimensions. Si-SiO₂ interface properties and performance of LPCVD gorwn polysilicon gate natural transistor has been studied through MOS C-V analysis and physical-electrical modeling. Transistor behavior at cryogenic temperatures has also been analysed through MOS C-V characteristics and one dimensional transport equations.     

Analysis of gate shot noise in MOSFETs with ultrathin gate oxides

The impact of gate shot noise associated with gate leakage current in MOSFETs is studied by means of analytical models and numerical device simulation. The effects of shot noise on the main two-port noise parameters (minimum noise figure, equivalent noise resistance, and optimum source admittance) and their dependence on oxide thickness and on the level of tunneling leakage current are analyzed.     

Influence of gate oxides with high thermal conductivity on the failure distribution of InGaAs-based MOS stacks

In this work, the breakdown transients of metal-oxide-semiconductors (MOS) stacks with InGaAs channels and different oxide layers (Al₂O₃, HfO₂ and Si₃N₄) have been studied in terms of the time-to-breakdown and the duration of the progressive breakdown regime. It is observed that dielectric layers with higher thermal conductivity show larger transient time during the progressive breakdown regime, and this provides a significant lifetime extension across the entire failure distribution. This is attributed to a lower temperature of the percolation path which reduces local electro-migration. Moreover, the overall results show that the progressive breakdown regime is uncorrelated with the initial degradation rate, and that the bending of failure distribution at low percentiles is exclusively attributed to the progressive increase of the gate current during the breakdown event.