A 20-/spl mu/W precision operational amplifier

A precision operational amplifier is described which draws 12 /spl mu/A of quiescent current and can operate from a 1.6-V supply while requiring no external components such as the usual biasing resistor. The amplifier has DC characteristics comparable to the industry standard OP-07 and AC characteristics as good as currently available micropower devices. The circuit has an input voltage range and an output swing which include the negative supply to facilitate its use in battery-powered and other single-supply applications.     

A multiplexed switched capacitor filter bank

A technique is introduced which allows several integrator capacitors to be multiplexed onto a single operational amplifier. As a result, the op amp can be shared by several switched capacitor filter channels, drastically reducing the number of op amps required for filter banks. Twenty second-order filters have been implemented in a circuit using only two op amps and 2.5 mm/SUP 2/. The design of this system is presented and its performance is discussed. Some loss of signal energy is shown to occur during the multiplexing operations, which reduces filter Q. Causes of this charge loss are described, and its effects on performance are modeled. The design of the op amp used is presented, which incorporates a new system of input stage biasing and differential to single-ended conversion, as well as other features.     

A high-swing 2-V CMOS operational amplifier with replica-amp gainenhancement

A general gain-enhancement technique for operational amplifiers using a replica amplifier is described. Unlike conventional techniques such as cascoding, which increases the gain by increasing the output resistance, the replica-amp technique increase the gain by matching the main and the replica amps. Among the advantages of the replica-amp technique are low supply, high swing, and effectiveness with resistive loads. This technique has been demonstrated in a 1.2-μm CMOS two-stage op amp. Operating from ±1-V supplies, the op amp has an effective open-loop dc gain of greater than 10 000, while maintaining a high swing of 100 mV from either supply rails. The gain-enhancement circuit is shown to have only a small effect on the settling time experimentally, analytically, and in SPICE simulation     

Macromodeling of integrated circuit operational amplifiers

A macromodel has been developed for integrated circuit (IC) op amps which provides an excellent pin-for-pin representation. The model elements are those which are common to most circuit simulators. The macromodel is a factor of more than six times less complex than the original circuit, and provides simulated circuit responses that have run times which are an order of magnitude faster and less costly in comparison to modeling the op amp at the electronic device level. Expressions for the values of the elements of the macromodel are developed starting from values of typical response characteristics of the op amp. Examples are given for three representative op amps. In addition, the performance of the macromodel in linear and nonlinear systems is presented. For comparison, the simulated circuit performance when modeling at the device level is also demonstrated.     

A dual current feedback op amp in CMOS technology

A CMOS circuit configuration implementing a current feedback or transimpedance op amp (CFB op amp) is presented. The architecture of the circuit is derived from similar bipolar CFB op amps. The properties of the CMOS implementation are similar to those of its bipolar counterparts, i.e., a high slew rate and a bandwidth which is independent of the closed-loop gain when the op amp is used with current feedback. Further, it is shown how two CFB op amps can be connected to achieve a non-slew-rate-limited voltage-mode op amp.     

A macromodel for integrated all-MOS operational amplifiers

A macromodel for integrated all-MOS operational amplifiers is developed with reference to circuits where the settling behavior of the op amps is of particular concern. Expressions for the values of the elements of the macromodel are obtained from typical measured characteristics. It is shown that the proposed macromodel can satisfactorily predict both small-signal and large-signal behavior of the op amps.     

Simple technique for op amp continuous-time 1 V supply operation

A simple scheme for achieving continuous-time low-voltage operation of op amps is discussed. The scheme involves placing a floating battery in series with one of the op amp input terminals. Simulations and experimental results are presented that verify the proposed scheme with the example of a CMOS op amp that operates from a single 1 V supply and with 0.8 V signal swing     

Design for testability of embedded integrated operationalamplifiers

The operational amplifier (op amp) is one of the most encountered analog building blocks. In this paper, the problem of testing an integrated op amp is treated. A new low-cost vectorless test solution, known as oscillation test, is investigated to test the op amp. During the test mode, the op amps are converted to a circuit that oscillates and the oscillation frequency is evaluated to monitor faults. The tolerance band of the oscillation frequency is determined using a Monte Carlo analysis taking into account the nominal tolerance of all important technology and design parameters. Faults in the op amps under test which cause the oscillation frequency to exit the tolerance band can therefore be detected. Some Design for Testability (DfT) rules to rearrange op amps to form oscillators are presented and the related practical problems and limitations are discussed. The oscillation frequency can be easily and precisely evaluated using pure digital circuitry. The simulation and practical implementation results confirm that the presented techniques ensure a high fault coverage with a low area overhead     

High-frequency active filter design using monolithic nullors

A monolithic building block suitable for high-frequency RC active filter implementation is described. The transconductance-type device is fabricated using standard bipolar technology, and its performance is shown to be superior to corresponding voltage operational amplifiers (op amps) at frequencies above 20 kHz. It is also shown that high quality simulated inductance and frequency dependent negative resistance elements can be implemented at higher frequencies than is possible using standard bipolar op amps.     

A precision variable-supply CMOS comparator

Several new techniques are presented for the design of precision CMOS voltage comparator circuits which operate over a wide range of supply voltages. Since most monolithic A/D converter systems contain an on-chip voltage reference, techniques have been developed to replicate the reference voltage in order to provide stable supply-independent DC bias voltages, and controlled internal voltage swings for the comparator. These techniques are necessary in order to eliminate harmful bootstrapping effects which can potentially occur in all AC coupled MOS analog circuits. An actively controlled biasing scheme has been developed to allow for differentially autozeroing the comparator for applications in differential A/D converter systems. A general approach for selecting the gain in AC-coupled gain stages is also presented. The comparator circuit has been implemented in a standard metal-gate CMOS process. The measured comparator resolution is less than 1 mV, and the allowable supply voltages range from 3.5 to 10 V.     

A high bandwidth constant gm and slew-rate rail-to-railCMOS input circuit and its application to analog cells for low voltageVLSI systems

A new rail-to-rail CMOS input architecture is presented that delivers behavior nearly independent of the common-mode level in terms of both transconductance and slewing characteristics. Feedforward is used to achieve high common-mode bandwidth, and operation does not rely on analytic square law characteristics, making the technique applicable to deep submicron technologies. From the basis of a transconductor design, an asynchronous comparator and a video bandwidth op amp are also developed, providing a family of general purpose analog circuit functions which may be used in high (and low) bandwidth mixed-signal systems. Benefits for the system designer are that the need for rigorous control of common-mode levels is avoided and input signal swings right across the power supply range can be easily handled. A further benefit is that having very consistent performance, the circuits can be easily described in VHDL (or other behavioral language) to allow simulation of large mixed-signal systems. The circuits presented may be easily adapted for a range of requirements. Results are presented for representative transconductor, op amp, and comparator designs fabricated in a 0.5 μm 3.3 V digital CMOS process     

Compact High Gain CMOS Op Amp Design using Comparators

This paper discusses the design of high gain, general purpose op amps. The op amp is based on a novel cascaded design using comparators and with structural simplicity approaching that of digital circuits. Ideally, the design tool presented here can be used to optimize gain and CMRR independent of the other op amp performance parameters. The designed op amp has 140 dB open-loop gain and 43 MHz unity gain frequency (GBW) in Berkeley Spice3f Level-2 simulation. The circuit is implemented using a 2.0 m nwell CMOS process through MOSIS. The op amp is self-biased and requires only power supplies of ±2.5 V. It occupies an area of 113 m×474 m.     

Operational amplifier with 1-V rail-to-rail multipath-driven outputstage

A bipolar operational amplifier (op amp) with a rail-to-rail multipath-driven output stage that operates at supply voltages down to 1 V is presented. The bandwidth of this output stage is as high as possible, viz, equal to that of one of the output transistors, loaded by the output capacitance. The output voltage can reach both supply rails within 100 mV and the output current is ±15 mA. The op amp is designed to be loaded by a 100-pF capacitor and the unity-gain bandwidth is 3.4 MHz at a 60° phase margin. The voltage gain is 117 dB and the CMRR is 100 dB. The frequency behavior of the multipath-driven (MPD) topology has an improved performance when compared to that of previously presented low-voltage output stages. A figure of merit F_M for low-voltage op amps has been defined as the bandwidth-power ratio     

Highly linear micropower class AB current mirrors using Quasi-Floating Gate transistors

A design approach to achieve low-voltage micropower class AB CMOS cascode current mirrors is presented. Both class AB operation and dynamic cascode biasing are based on the use of Quasi-Floating Gate transistors. They allow high linearity for large signal currents and accurately set quiescent currents without requiring extra power consumption or supply voltage requirements. Measurement results show that dynamic cascode biasing allows a wider input range and a linearity improvement of more than 23 dB with respect to the use of conventional biasing. A THD value better than −35 dB is measured for input amplitudes up to 100 times the bias currents. Two class AB current mirror topologies are proposed, with slightly different ways to achieve class AB operation and dynamic biasing. The proposed current mirrors, fabricated in a 0.5 µm CMOS technology, are able to operate with a supply voltage of 1.2 V and a quiescent power consumption of only 36 µW, using a silicon area <0.025 mm².     

红外成像技术在自动测试设备中的应用

“印制电路板故障红外诊断仪”是集光、机、电和计算机一体化的非接触式故障诊断系统。文中详细介绍了该系统的组成、功能及特点,描述了在系统研制过程中解决的主要关键技术问题和难点。该系统硬件由热像仪、计算机、图像采集处理卡、信号源、交直流电源、测试平台等部分组成,软件由故障诊断、信息处理、开发服务等模块组成。该系统具有自动、手动两种诊断方式,其故障诊断速度快、准确率高,通用性强、适用面广。     

A Novel Method for Bandwidth and Phase Margin Enhancement of Folded-Cascode Amplifier

This article describes a method to enhance bandwidth and phase margin of conventional folded-cascode op amps. It achieves a larger bandwidth and/or phase margin in folded-cascode CMOS op amps than those of a conventional one in a given CMOS process. For the same bandwidth the new method allows a larger phase margin, and for a given phase margin a larger bandwidth can be obtained. Also, for equal bandwidth, power consumption of the new folded-cascode is lower than the traditional one with similar load.     

不同结构CMOS运算放大器电路的电离辐射效应

介绍了在相同工艺条件下 ,N沟和 P沟输入两种不同结构 CMOS运算放大器电路的电离辐照响应规律及各子电路对电特性的影响情况 .结果表明 :由辐照感生的氧化物电荷引起的N沟镜像负载的不对称是导致 P沟输入运放电特性衰降的主要机制 ;而由氧化物电荷和界面态引起的 N沟差分对的漏电增大则是造成 N沟输入运放电路性能变差的主要原因     

Effect of substrate biasing on Si/SiGe heterostructure MOSFETs for low-power circuit applications

We have investigated the effect of substrate biasing on the subthreshold characteristics and noise levels of Si/Si/sub 1-x/Ge/sub x/ (x=0,0.15,0.3) heterostructure MOSFETs. A detailed analysis of the dependence of threshold voltage, off-state current, and low-frequency noise level on the substrate-source (V/sub bs/) biasing showed that SiGe heterostructure MOSFETs offer a significant speed advantage, an extended subthreshold operation region, a reduced noise level, and reduced bulk potential sensitivity compared to Si bulk devices. These experimental results demonstrate that SiGe heterostructure MOSFETs render a promising extension to the CMOS technologies at the low-power limit of operation, eventually making the micropower implementation of radio frequency (RF) functions feasible.     

一种折叠共源共栅运算放大器的设计

折叠共源共栅运放结构的运算放大器可以使设计者优化二阶性能指标,这一点在传统的两级运算放大器中是不可能的。特别是共源共栅技术对提高增益、增加PSRR值和在输出端允许自补偿是有很用的。这种灵活性允许在CMOS工艺中发展高性能无缓冲运算放大器。目前,这样的放大器已被广泛用于无线电通信的集成电路中。介绍了一种折叠共源共栅的运算放大器,采用TSMC 0.18混合信号双阱CMOS工艺库,用HSpice W 2005.03进行设计仿真,最后与设计指标进行比较。     

A 1.2-V 19.2-mW 10-bit 30-MS/s pipelined ADC in 0.13-icm CMOS

A 10-bit 30-MS/s pipelined analog-to-digital converter (ADC) is presented.For the sake of lower power and area,the pipelined stages are scaled in current and area,and op amps are shared between the successive stages.The ADC is realized in the 0.13-tt,m 1-poly 8-copper mixed signal CMOS process operating at 1.2-V supply voltage.Design approaches are discussed to overcome the challenges associated with this choice of process and supply voltage,such as limited dynamic range,poor analog characteristic devices,the limited linearity of analog switches and the embedded sub-1-V bandgap voltage reference.Measured results show that the ADC achieves 55.1-dB signal-to-noise and distortion ratio,67.5-dB spurious free dynamic range and 19.2-mW power under conditions of 30 MSPS and 10.7-MHz input signal.The FoM is 0.33 pJ/step.The peak integral and differential nonlinearities are 1.13 LSB and 0.77 LSB,respectively.The ADC core area is 0.94 mm2.