The impact of semiconductor technology scaling on CMOS RF and digital circuits for wireless application

The impact of CMOS technology scaling on the various radio frequency (RF) circuit components such as active, passive and digital circuits is presented. Firstly, the impact of technology scaling on the noise and linearity of the low-noise amplifier (LNA) is thoroughly analyzed. Then two new circuits, i.e., CMOS complementary parallel push-pull (CCPP) circuit and vertical-NPN (V-NPN) circuit for direct-conversion receiver (DCR), are introduced. In CCPP, the high RF performance of pMOS comparable to nMOS provides single ended differential RF signal processing capability without the use of a bulky balun. The use of parasitic V-NPN bipolar transistor, available in triple well CMOS technology, has shown to provide more than an order of magnitude improvement in 1/f noise and dc offset related problems, which have been the bottleneck for CMOS single chip integration. Then CMOS technology scaling for various passive device performances such as the inductor, varactor, MIM capacitor, and switched capacitor, is discussed. Both the forward scaling of the active devices and the inverse scaling of interconnection layer, i.e., more interconnection layers with effectively thicker total dielectric and metal layers, provide very favorable scenario for all passive devices. Finally, the impact of CMOS scaling on the various digital circuits is introduced, taking the digital modem blocks, the various digital calibration circuits, the switching RF power amplifier, and eventually the software defined radio, as examples.     

Investigation of a multigigahertz MOSFET amplifier with an on-chipinductor fabricated on a SIMOX wafer

This paper describes a technology that can be used to integrate multigigahertz RF circuits into large-scale digital circuits. Spiral inductors and a MOSFET amplifier with an inductive load were fabricated on a SIMOX wafer in order to demonstrate the feasibility of SOI technology. With a 1-V supply voltage, peaking of the amplifier gain was observed, as expected from circuit simulations, at 1-4 GHz. These results show that RF circuits with inductors can be implemented on a SIMOX wafer by using the conventional digital CMOS LSI process     

SOI在射频电路中的应用

随着射频电路(RF)工作频率和集成度的提高,衬底材料对电路性能的影响越来越大.SOI(Silicon-on-Insulator)结构以其良好的电学性能,为系统设计提供了灵活性.与CMOS工艺的兼容使它能将数字电路与模拟电路混合,在射频电路应用方面显示巨大优势.文章分析了RF电路发展中遇到的挑战和SOI在RF电路中的应用优势,综述了SOI RF电路的最新进展.     

Verification of Complex Analog and RF IC Designs

Meeting performance specifications in the design of analog and RF (A/RF) blocks and integrated circuits (IC) continues to require a high degree of skill, creativity, and expertise. However, today's A/RF designers are increasingly faced with a new challenge. Functional complexity in terms modes of operation, extensive digital calibration, and architectural algorithms is now overwhelming traditional A/RF design methodologies. Functionally verifying A/RF designs is a daunting task requiring a rigorous methodology. As occurred in digital design, analog verification is becoming a separate and critical task. This paper describes the verification issues faced by the A/RF designer and presents a verification methodology to address these challenges. It presents a systematic approach to A/RF verification, the concept of an analog verification engineer, how to establish the methodology, and concludes with an example     

IIP2 Calibration by Injecting DC Offset at the Mixer in a Wireless Receiver

A major contributor to degraded input-referred second-order intercept point (IIP2) in integrated RF systems-on-chips is local oscillator (LO) leakage to the input of RF circuits. In this brief, we present a digital calibration technique for improving IIP2 by injecting controlled dc offset at the mixer output through a three-port network of switched-capacitor filters. The dc offset at mixer output gets up-converted to LO frequency at the input of RF circuits due to poor reverse isolation of the receiver front-end. By controlling the amplitude of the injected dc, IIP2 degradation due to LO leakage at the input of RF amplifiers can be compensated. Mathematical analysis is presented and supported by measurement data from a quad-band GSM/GPRS receiver implemented in 90-nm digital CMOS process. Calibrated IIP2 of 50 dBm is reported for the receiver at low-noise amplifier input.     

Estimation and compensation of process-induced variations in capacitors for improved reliability in integrated circuits

This paper describes a method for the estimation of capacitor process variations in integrated circuits and for the subsequent compensation of such variations through a calibration scheme that exploits a variable capacitor bank. An architecture for the calibration circuit is proposed, and various problems that arise during implementation are discussed. The design consists of an oscillator whose output frequency is inversely proportional to the capacitor value and simple state machine for measurement of capacitor process variations. The design of optimum capacitor bank is described together with the adequate tuning plan. The circuit is fabricated and verified in 130 nm RF CMOS process and can be easily scaled to sub-100-nm technologies.     

The impact of plasma-charging damage on the RF performance ofdeep-submicron MOSFET

Integration of RF analog functions with CMOS digital circuits offers great advantages in terms of cost and performance. Plasma-charging damage is known to degrade MOSFET characteristics and can be expected to impact the RF performance as well. In this work, we present for the first time a thorough investigation of the impact of plasma-charging damage on the RF characteristics of deep-submicron MOSFET. Our result shows that, with ultra-thin gate oxide, a 400°C forming gas annealing can completely recover the RF performance degradation due to plasma-charging damage     

A Wideband ΔΣ Digital-RF Modulator for High Data Rate Transmitters

A wideband software-defined digital-RF modulator targeting Gb/s data rates is presented. The modulator consists of a 2.625-GS/s digital DeltaSigma modulator, a 5.25-GHz direct digital-RF converter, and a fourth-order auto-tuned passive LC RF bandpass filter. The architecture removes high dynamic range analog circuits from the baseband signal path, replacing them with high-speed digital circuits to take advantage of digital CMOS scaling. The integration of the digital-RF converter with an RF bandpass reconstruction filter eliminates spurious signals and noise associated with direct digital-RF conversion. An efficient passgate adder circuit lowers the power consumption of the high-speed digital processing and a quadrature digital-IF approach is employed to reduce LO feedthrough and image spurs. The digital-RF modulator is software programmable to support variable bandwidths, adaptive modulation schemes, and multi-channel operation within a frequency band. A prototype IC built in 0.13-mum CMOS demonstrates a data rate of 1.2 Gb/s using OFDM modulation in a bandwidth of 200 MHz centered at 5.25 GHz. In-band LO and image spurs are less than -59 dBc without requiring calibration. The modulator consumes 187 mW and occupies a die area of 0.72 mm².     

A programmable intraocular CMOS pressure sensor system implant

We present a programmable intraocular pressure sensor system implant integrated on a single CMOS chip. It contains an on-chip micromechanical pressure sensor array, a temperature sensor, readout and calibration electronics, a μC-based digital control unit, and an RF transponder. The transponder enables wireless data transmission and wireless power reception, thus making batteryless operation feasible. The chip has been fabricated in a 1.2-μm n-well CMOS process complemented by additional processing steps     

Survey of Robustness Enhancement Techniques for Wireless Systems-on-a-Chip and Study of Temperature as Observable for Process Variations

Built-in test and on-chip calibration features are becoming essential for reliable wireless connectivity of next generation devices suffering from increasing process variations in CMOS technologies. This paper contains an overview of contemporary self-test and performance enhancement strategies for single-chip transceivers. In general, a trend has emerged to combine several techniques involving process variability monitoring, digital calibration, and tuning of analog circuits. Special attention is directed towards the investigation of temperature as an observable for process variations, given that thermal coupling through the silicon substrate has recently been demonstrated as mechanism to monitor the performances of analog circuits. Both Monte Carlo simulations and experimental results are presented in this paper to show that circuit-level specifications exhibit correlations with silicon surface temperature changes. Since temperature changes can be measured with efficient on-chip differential temperature sensors, a conceptual outline is given for the use of temperature sensors as alternative process variation monitors.     

Self-calibration of input-match in RF front-end circuitry

The input match of RF front-end circuitry can degrade significantly due to process faults and parasitic package inductances at its input pad. The proposed technique ascertains the input match frequency of the circuit by using a built-in self-test (BiST) structure, determines the frequency interval by which it needs to be shifted to restore it to the desired value, and then feeds back a digital word to the low-noise amplifier (LNA), which adaptively corrects its input-match in real-time. The circuitry presented in the paper offers the advantages of low power overheads (the circuits can be powered off when not in use), robustness, no requirements of digital signal processing cores or processors, and fast calibration times (less than 30 /spl mu/s). This proof of concept is demonstrated by designing a cascode LNA and the complete self-calibration circuit in IBM 0.25-/spl mu/m CMOS RF process.     

CMOS wireless transceivers: the new wave

A new generation of wireless transceivers is being intergrated into CMOS IC technology, which so far has been used mainly to realize digital and mixed analog-digital baseband circuits. This article reviews some of the RF CMOS circuit design techniques, and shows how an understanding of the strengths and weaknesses of these circuits influences choice of radio architecture. The CMOS approach to radio design calls for the elimination of discrete components in favor of high levels of on-chip integration which freely use translators and mix analog and digital functionality; in these respects, it departs from traditional RF circuit practices. Successful wireless devices of the future will require that radio system design evolve around these new trends in RF integration     

A 2.45-GHz Near-Field RFID System With Passive On-Chip Antenna Tags

The design of a 2.45-GHz near-field RF identification (RFID) system with passive on-chip antenna (OCA) tags is very challenging as the efficiency of RF power conversion is very low. It poses multidisciplinary research challenges such as ultra-low-power circuits design, semiconductor process technology, and integrated antenna design. This paper describes the designs of such an RFID system, the reader, and OCAs, as well as the passive tag integrated circuits in detail. The passive tag chip with 128-bit nonvolatile memory has been realized using CMOS 0.13- technology. The OCA is fabricated on top of the chip using post-processing technology. The complete RFID tag with an integrated OCA is smaller than 0.5- with a thickness of 0.1 mm. With the reader generating an output power of 0.5 W, the RFID system is able to perform with RF read/write functions at a distance of .     

RF calibration of on-chip DfT chain by DC stimuli and statistical multivariate regression technique

The problem of parameter variability in RF and analog circuits is escalating with CMOS scaling. Consequently every RF chip produced in nano-meter CMOS technologies needs to be tested. On-chip Design for Testability (DfT) features, which are meant to reduce test time and cost also suffer from parameter variability. Therefore, RF calibration of all on-chip test structures is mandatory. In this paper, Artificial Neural Networks (ANN) are employed as a multivariate regression technique to architect a RF calibration scheme for DfT chain using DC- instead of RF (GHz) stimuli. The use of DC stimuli relaxes the package design and on-chip routing that results in test cost reduction. A DfT circuit (RF detector, Test-ADC, Test-DAC and multiplexers) designed in 65 nm CMOS is used to demonstrate the proposed calibration scheme. The simulation results show that the cumulative variation in a DfT circuit due to process and mismatch can be estimated and successfully calibrated, i.e. 25% error due to process variation in DfT circuit can be reduced to 2.5% provided the input test stimuli is large in magnitude. This reduction in error makes parametric tests feasible to classify the bad and good dies especially before expensive RF packaging.     

Modeling and Design of CMOS UHF Voltage Multiplier for RFID in an EEPROM Compatible Process

Modeling and design of CMOS ultra-high-frequency (UHF) voltage multipliers are presented. These circuits recover power from incident radio frequency (RF) signal and supply battery less UHF RF identification (RFID) transponders. An analytical model of CMOS UHF voltage multipliers is developed. It permits to determine the main design parameters in order to improve multiplier performance. The design of this kind of circuits is then greatly simplified and simulation time is reduced. Thanks to this model, a voltage multiplier is designed and implemented in a low-cost electrically erasable programmable read-only memory compatible CMOS process without Schottky diodes layers. Measurements results show communication ranges up to 5 m in the U.S. standard.     

Towards Fault-Tolerant RF Front Ends

The continuing trends of scaling have brought with them an ever-increasing array of process faults and fabrication complexities. The relentless march towards miniaturization and massive integration, in addition to increasing operating frequencies has resulted in increasing concerns about the reliability of integrated RF front-ends. Coupled with rising cost per chip, the fault-tolerant paradigm has become pertinent in the RFIC domain. Due to the high frequencies involved, traditional fault-tolerance methods used in digital and lower frequency analog circuits cannot be applied. We propose a unique methodology to achieve fault-tolerance in RF circuits through dynamic sensing and on-chip self-correction, along with the development of robust algorithms. This technique, which poses minimal overheads and is transparent during ‘normal’ use of the circuit, is demonstrated on a cascode LNA, since the LNA is critical for the performance of the entire front-end. We present simulation and fabricated results of the system designed in IBM 0.25 μm CMOS 6RF process.     

Efficient algorithms for multilevel power estimation of VLSI circuits

This paper presents a methodology for calculating highly accurate mean power estimates for integrated digital CMOS circuits. A complementary calibration scheme for ASIC library cells to extract the power relevant parameters is proposed. The circuit models presented allows the prediction of mean power dissipation of gate-level designs in CMOS technologies with an accuracy that is comparable to a SPICE simulation but up to 10 000 times faster. The outlined approach is capable of handling complex circuits consisting of more than 20 000 cells and thousands of memory elements. Very large sets of input data with several millions of patterns can, thus, be simulated in an efficient way. This allows the prediction of mean power dissipation of VLSI circuits in a realistic functional context which provides new assessment possibilities for digital CMOS low-power design methods. Experimental results for some benchmark circuits are detailed in order to demonstrate the significant improvements in terms of performance, accuracy, and flexibility of this approach compared to state-of-the-art power estimation methods     

Thick Metal CMOS Technology on High Resistivity Substrate and Its Application to Monolithic L-Band CMOS LNAs

Thick metal 0.8 µm CMOS technology on high resistivity substrate (RF CMOS technology) is demonstrated for the L-band RF IC applications, and we successfully implemented it to the monolithic 900 MHz and 1.9 GHz CMOS LNAs for the first time. To enhance the performance of the RF circuits, MOSFET layout was optimized for high frequency operation and inductor quality was improved by modifying the technology. The fabricated 1.9 GHz LNA shows a gain of 15.2 dB and a NF of 2.8 dB at DC consumption current of 15 mA that is an excellent noise performance compared with the off-chip matched 1.9 GHz CMOS LNAs. The 900 MHz LNA shows a high gain of 19 dB and NF of 3.2 dB despite of the performance degradation due to the integration of a 26 nH inductor for input match. The proposed RF CMOS technology is a compatible process for analog CMOS ICs, and the monolithic LNAs employing the technology show a good and uniform RF performance in a five inch wafer.     

All-Digital PLL With Ultra Fast Settling

A fully digital frequency synthesizer for RF wireless applications has recently been proposed. At its foundation lies a digitally controlled oscillator with sufficiently fine frequency resolution to avoid analog tuning. The conventional phase/frequency detector, charge pump and RC loop filter are replaced by a time-to-digital converter and a simple digital loop filter. When implemented in highly scaled digital CMOS processes, the proposed architecture is more advantageous over conventional charge-pump-based phase-locked loops (PLLs) since it exploits signal processing capabilities of digital circuits and avoids relying on the fine voltage resolution of analog circuits. In this brief, we present novel techniques used in the all-digital PLL to achieve an ultra-fast frequency acquisition of <50 mus while maintaining excellent phase noise and spurious performance during transmission and reception. This approach has been validated and incorporated in commercial single-chip Bluetooth and Global System for Mobile Communications radios realized in deep-submicrometer CMOS     

A Wideband CMOS RF Front-End Using AC-Coupled Current Mirrored Technique for Multiband Multistandard Mobile TV Tuners

In this paper, a wideband CMOS radio frequency (RF) front-end for various terrestrial mobile digital TV applications such as digital video broadcasting-handheld, terrestrial digital multimedia broadcasting, and integrated services digital broadcasting-terrestrial is proposed. To cover VHF III, UHF, and L bands and reduce the silicon area simultaneously, it employs three low-noise amplifiers and single-to-differential transconductors and shares the rest of the RF front-end. By applying ac-coupled current mirrored technique, the proposed RF front-end has good wideband performance, high linearity, and precise gain control. It is fabricated in 0.18 mum CMOS process and draws 15 mA~20 mA from a 1.8 V supply voltage for each band. It shows a gain of more than 29 dB, noise figure of lower than 2.5 dB, IIP2 of more than 30 dBm, IIP3 of more than -10 dBm for entire bands.