低电压Charge-RecOVery逻辑电路的设计

提出了一种新的适用于低电压工作的semi-adiabatic逻辑电路--Dual-Swing Charge-Recovery Logic(DSCRL).该电路由CMOS-latch-type电路及负载驱动电路构成,对负载的驱动为full-adiabatic过程.DSCRL的电源为六相双峰值脉冲电源,低摆幅脉冲用于驱动负载,高摆幅脉冲用于驱动CMOS-latch-type电路.降低负载上摆幅时驱动负载的NMOS管的栅压可以保持不变,有效地解决了传统的adiabatic电路在低电压工作时charge-re-covery效率降低的问题.文中比较了DSCRL电路与部分文献中的semi-adiabatic电路的功耗,DSCRL在低电压工作方面有较为明显的优势.     

一种利用自举效应的Charge-Recovery逻辑电路

提出了一种新的 semi- adiabatic逻辑电路—— Bootstrap Charge- Recovery Logic( BCRL) .该电路由 semi- adiabatic电路完成逻辑运算 ,而由自举的 NMOS管驱动负载 ,对负载的操作为 full- adiabatic过程 .BCRL电路由两相无交叠脉冲时钟电源供电 ,输出为全摆幅脉冲信号 .比较了 BCRL反相器驱动电容负载时与静态 CMOS电路及部分文献中的 semi- adiabatic电路的功耗差别 .应用 0 .65μm CMOS工艺器件参数的模拟结果表明 ,BCRL电路可以在1 0 0 MHz脉冲电源频率下正常工作 ,并且有较好的降低功耗的效果     

一种利用自举效应的Charge-Recovery逻辑电路

提出了一种新的semi-adiabatic逻辑电路--BootstrapCharge-RecoveryLogic(BCRL).该电路由semi-adiabatic电路完成逻辑运算,而由自举的NMOS管驱动负载,对负载的操作为full-adiabatic过程.BCRL电路由两相无交叠脉冲时钟电源供电,输出为全摆幅脉冲信号.比较了BCRL反相器驱动电容负载时与静态CMOS电路及部分文献中的semi-adiabatic电路的功耗差别.应用0.65μmCMOS工艺器件参数的模拟结果表明,BCRL电路可以在100MHz脉冲电源频率下正常工作,并且有较好的降低功耗的效果.     

一种用于DSCRL绝热电路的新型功率时钟

提出了一种用于DSCRL(双摆幅电荷恢复逻辑)绝热电路的新型四相功率时钟,该功率时钟采用了非对称的方法来优化其时序,比已提出的采用对称技术来优化时序的六相功率时钟更简洁.这种新型的功率时钟用于DSCRL绝热电路后,该电路仍然保持了其能量恢复的高效性,同时还降低了电路设计的复杂性,这一结论已被文中的HSPICE 模拟结果证明.     

一种用于DSCRL绝热电路的新型功率时钟

提出了一种用于DSCRL(双摆幅电荷恢复逻辑)绝热电路的新型四相功率时钟,该功率时钟采用了非对称的方法来优化其时序,比已提出的采用对称技术来优化时序的六相功率时钟更简洁.这种新型的功率时钟用于DSCRL绝热电路后,该电路仍然保持了其能量恢复的高效性,同时还降低了电路设计的复杂性,这一结论已被文中的HSPICE 模拟结果证明.     

低压高驱动能力的CMOS电流反馈运算放大器

基于0.18μm CMOS工艺,设计了一种具有低电压高驱动能力的电流反馈运算放大器。电路工作在1.8 V电源电压下,Spectre仿真的功耗为316μW,转换速率为112 V/μs,电流驱动能力达±1.5 mA。输入采用轨对轨结构,以提高输入电压摆幅;输出采用互补输出结构,使输出工作在甲乙类状态,以降低电路功耗。     

低电压低功耗密勒OTA仿真设计

设计了一种电源电压低于阈值电压的低电压、低功耗、输入/输出全摆幅的密勒运算跨导放大器(OTA),采用衬底驱动差分对和直流电平偏移技术,使MOS器件工作在亚闲值区,降低了对电源电压VDD的要求,且输入/输出摆幅也能实现轨对轨.采用台积电(TSMC)0.35 μm标准n阱CMOS工艺BSIM3V3模型对此OTA进行了HSPICE仿真实验.结果表明,当VDD为600mV时开环增益A0为70.4 dB,不但此OTA输入/输出摆幅轨对轨,而且其功耗PD只有420 nW,从而实现了低压低耗的设计目标,可用于便携式产品的电子电路设计中.     

德州仪器推出采用微型电源封装的轨至轨2A运算放大器

德州仪器(T I)推出一款大电流、低成本功率运算放大器(运放),能够以低电压电源驱动各种负载。O P A567来自TIBurr-Brown产品线,其工作电源可为单电源或双电源,能够实现设计的灵活性,并且适用于几乎所有的运算放大器配置(更多详情,敬请访问w w w.t i.com/sc05213)。该款单位增益稳定器件具有输入与输出轨至轨摆动。当输出电流为2A时,电源轨的输出摆幅在300m V以内。电流负载越低,输出摆幅与轨就越接近,从而能够实现更高的性能。该款运算放大器理想适用于驱动阀门、传动装置、激光二极管泵以及伺服马达等。其它应用包括热电冷却器、同步…     

大输出摆幅的多级功率放大器及其频率补偿

本文对平衡传输(BTL)功率驱动电路中功率放大器的输出级进行了改进设计,输出摆幅明显改善,在5V的电源电压下,功率放大器的输出摆幅提高了2 3%.因该功率放大器是多级的,通常驱动的是电感负载,频率补偿时本文采用网巢密勒补偿(NMC)和简单密勒补偿相结合的方式.在总补偿电容为7pF及0.6 μm的BCD工艺条件下,得到了大于95dB的增益值,大于70度的相位裕度,大于2MHZ的增益带宽和0.43V输出摆幅下限.     

微功耗＋3．3V．双SCART方案

MAX9598的音频和视频电路工作在＋3．3V电源,仅在处理低速切换信号时需要＋12V电源。内部的电荷泵将＋3．3V电源反相,从而产生-3．3V电源,可为2．0VRMS音频信号提供足够的电压摆幅。其静态功耗仅为70mW。MAX9598还集成了输入视频信号和视频负载检测电路,可以根据负载和输入信号的情况智能地降低整个系统的功耗。     

An improved current mode logic latch for high‐speed applications

In this paper, an improved current mode logic (CML) latch design is proposed for high‐speed on‐chip applications. Transceivers use various methods in fast data transmission in wireless/wire‐line application. For an asynchronous transceiver, the improved CML latch is designed using additional NMOS transistors in conventional CML latch which helps to boost the output voltage swing. The proposed low‐power CML latch‐based frequency divider is compatible for higher operating frequency (16 GHz). Next, the delay model is also developed based on small signal equivalent circuit for the analysis of the proposed latch. The output voltage behavior of the proposed latch is analyzed using 180‐nm standard CMOS technology.     

Pass transistor with dual threshold voltage domino logic design using standby switch for reduced subthreshold leakage current

Dual threshold voltages domino design methodology utilizes low threshold voltages for all transistors that can switch during the evaluate mode and utilizes high threshold voltages for all transistors that can switch during the precharge modes. We employed standby switch can strongly turn off all of the high threshold voltage transistors which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current. Subthreshold leakage currents are especially important in burst mode type integrated circuits where the majority of the time for system is in an idle mode. The standby switch allowed a domino system enters and leaves a low leakage standby mode within a single clock cycle. In addition, we combined domino dynamic circuits style with pass transistor XNOR and CMOS NAND gates to realize logic 1 output during its precharge phase, but not affects circuits operation in its evaluation and standby phase. The first stage NAND gates output logic 1 can guarantee the second stage computation its correct logic function when system is in a cascaded operation mode. The processing required for dual threshold voltage circuit configuration is to provide an extra threshold voltage involves only an additional implant processing step, but performs lower dynamic power consumption, lower delay and high fan-out, high switching frequencies circuits characteristics. SPICE simulation for our proposed circuits were made using a 0.18 µm CMOS process from TSMC, with 10 fF capacitive loads in all output nodes, using the parameters for typical process corner at 25 °C, the simulation results demonstrated that our designed 8-bit carry look-ahead adders reduced chip area, power consumption and propagation delay time more than 40%, 45% and around 20%, respectively. Wafer based our design were fabricated and measured, the measured data were listed and compared with simulation data and prior works. SPICE simulation also manifested lower sensitivity of our design to power supply, temperature, capacitive load and process variations than the dynamic CMOS technologies.     

一种单锁存器CMOS三值D型边沿触发器设计

提出了一种只使用单个锁存器的CMOS三值D型边沿触发器设计.该电路是通过时钟信号的上升沿后产生的窄脉冲使锁存器瞬时导通完成取样求值.所提出的电路较之以往设计具有更为简单的结构,三值双轨输出时仅需24个MOS管.计算机模拟结果验证了所提出的触发器具有正确的逻辑功能、良好的瞬态特性和更低的功耗.此外,该设计结构极易推广至基值更高的多值边沿触发器的设计.     

一种高速低耗全摆幅BiCMOS集成施密特触发器

通过分析国外流行的一种 Bi CMOS集成施密特触发门 ,提出了一种高速、低功耗、全摆幅输出的Bi CMOS施密特触发器。该器件中单、双极型电路优势互补 ,电源电压为 1 .5 V,实现了优于同类产品的全摆幅输出 ,且其开关速度高于同类 CMOS产品的 1 3倍以上 ,因此特别适用于高速数字通信系统中     

采用三相电源的互补传输管绝热逻辑电路

提出了一种由三相电源驱动的新绝热逻辑电路--complementary pass-transistor adiabatic logic(CPAL).电路由CPL电路完成相应的逻辑运算,由互补传输门对输出负载进行绝热驱动,电路的整体功耗较小.指出选取合适的输出驱动管的器件尺寸可进一步减小CPAL电路的总能耗.设计了仅由一个电感和简单控制电路组成的三相功率时钟产生电路.为了验证提出的CPAL电路和时钟产生电路,设计了8bit全加器进行模拟试验.采用MOSIS的0.25μm CMOS工艺,在50～200MHz频率范围内,CPAL全加器的功耗仅为PFAL电路和2N-2N2P电路的50%和35%.     

A compact rail-to-rail output stage for CMOS operational amplifiers

This paper presents a CMOS output stage devised for driving heavy resistive loads. An operational amplifier of this type has been fabricated in a 3 μm double-polysilicon CMOS technology. With a supply voltage of ∓5 V and load of 470 Ω, the amplifier has a ∓4.6-V output swing and features a 60 mA short-circuit output current. Although simple, the proposed configuration enables the output transistors to be driven efficiently     

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS-only sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by 88 to 97% as compared to the standard dual threshold voltage domino logic circuits. Similarly, a 22 to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45 nm CMOS technology.