An automated meniscus coating system for polymer deposition onlarge-area MCM-D and MCM-L substrates

Material deposition techniques can be a significant contributor to the overall electronics manufacturing costs. The present study evaluates meniscus coating as a low-cost tool for large-area polymer deposition. Meniscus coating has the following advantages over conventional spin coating: (1) minimal material waste; (2) higher throughput; (3) higher planarity; (4) minimal defect density; (5) thickness uniformity over a large area. Each of these factors help reduce the overall manufacturing costs. The objective of this effort is to develop, install, and qualify an automated, low-cost, high-throughput polymer deposition method for large area MCM-D and MCM-L substrates. A variety of polymer photoresists, dielectrics, and composites are used for thick film coating on 12 in PWB and glass substrates. For each material, the deposition process is optimized to the desired film thickness. In this paper, we report materials and process optimization for 12 in×12 in substrates that is scalable to 24 in×24 in substrates. For higher throughput and lower manufacturing cost, an automated coating workcell is designed. The proposed workcell includes a robotic material handling and convection drying of coated films with automated loading/unloading capability. Design and fabrication of the integrated workcell are also addressed     

High rate magnetron RIE of thick polyimide films for advanced computer packaging applications

High performance (high speed and high wiring density) computer packaging can be obtained by applying thin film technology to the multichip interconnection structure. The thickness of the layers, as determined by the electrical requirements, necessitates the use of a via-fill process in conjunction with straight-wall openings in the dielectric layers. The packaging performance and wiring density is improved through reduced via areal dimensions (increased number of lines per layer), through elimination of stepcoverage limitations, and through better planarity thus increasing the number of signal and power layers. The MCNC split cathode magnetron was found to be the best RIE system for obtaining high rate low pressure oxygen RIE of polyimide films. The polyimide etch process was studied, characterized and optimized for the anisotropic residue free etch of 4 μm to 12 μm thick polyimide films. The etched wafers were then processed through the subsequent via filling step and reproducible planar via-filling was achieved with an electroless Ni plating process.     

The effect of electroplating parameters and substrate material on tin whisker formation

Electroplated tin finishes are widely used in the electronics industry due to their excellent solderability, electrical conductivity and corrosion resistance. However, the spontaneous growth of tin whiskers during service can result in localised electrical shorting or other harmful effects. Until recently, the growth of tin whiskers was successfully mitigated by alloying the tin with lead. However, restriction in the use of lead in electronics as a result of EU legislation (RoHS) has led to renewed interest in finding a successful alternative mitigation strategy.Whisker formation has been investigated for a bright tin electrodeposit to determine whether whisker growth can, at least partially, be mitigated by control of electroplating parameters such as deposition current density and deposit thickness. The influence of substrate material and storage at 55 °C/85% humidity on whisker growth have also been investigated.Whisker growth studies indicate that deposition parameters have a significant effect on both whisker density and whisker morphology. As deposition current density is increased there is a reduction in whisker density and a transition towards the formation of large eruptions rather than potentially more harmful filament whiskers. Increasing the tin coating thickness also results in a reduction in whisker density. Results demonstrate that whisker growth is most prolific from tin deposits on brass, whilst that from tin deposits on rolled silver is greater than that observed for tin deposits on copper.     

Facile and Rapid Method for Fabricating Liquid Metal Electrodes with Highly Precise Patterns via One‐Step Coating

Gallium‐based alloys, which are virtually non‐toxic liquid metals at room temperature, are considered highly promising electrode materials for state‐of‐the‐art electronics with new form factors. Herein, a facile and rapid method to fabricate liquid metal electrodes with highly precise patterns via a one‐step coating is presented. For this work, polymeric stencil masks with dual structures, comprising upper and lower structures for injecting and molding the liquid metal, respectively, are used for direct patterning of the liquid metal via spray deposition for few seconds, enabling the formation of complex and minute patterns including long thin lines and hollow forms. This method can be adapted to 3D substrates of various materials without any surface treatment, owing to the intrinsic adhesive and flexible properties of the polymeric masks ensuring conformal contact with non‐flat surfaces, and is also expected to be applicable to sub‐micron patterns. In addition, a number of highly flexible/stretchable electronic applications, exhibiting no change in electrical conductivity upon consecutive structural deformations, are demonstrated on various substrates including human skin. It is anticipated that these results will not only spur the further development of flexible/stretchable electronics, but also significantly contribute to the innovative on‐site fabrication of wearable electronics with high durability.     

Evolution of a unique flip-chip MCM-L package

Flip-chip (FC) packaging is gaining acceptance in the electronics packaging arena. More sources of bumped die and high density printed wiring boards (PWBs) laminates become available every day. Also, known good die (KGD) issues are being resolved by several companies, and design tools to perform FC packaging designs are becoming more available. This is the infrastructure FC packaging requires to become the packaging method of choice, particularly for >200 I/O applications. FC packages come in a variety of styles: FC plastic ball grid arrays (FC/PBGAs), FC plastic quad flat packs (PC/PQFPs), etc. Presently, the industry's drive is toward single chip packages on low cost laminates; i.e., organic substrates. Work is starting to occur in the area of multichip FC packages, due to the need to increase memory to microprocessor speed communication. In this article, a unique FC/MCM-L package is discussed. Part I will concentrate on the development and reliability testing of a one to four chip leadless FC/MCM-L package. Unlike traditional surface mount (SM) components that are attached to printed wiring boards (PWBs) with leads, the SM pads within the body of the package are used for attachment to a PWB. Collapsible eutectic solder domes are deposited on the SM pads by traditional screen printing. After reflow, these domes are used to connect the FC/MCM-L to the PWB. Challenges encountered during package design, PWB fabrication and first and second level assembly will be discussed. Part II of this article will focus on the extension of this FC/MCM-L package to a BGA second level interconnect. Change of FC attachment method, design enhancements, assembly, and reliability testing results will be presented     

Methodology for Modeling Substrate Warpage Using Copper Trace Pattern Implementation

The current trend in the electronics industry is to decrease the size of electronic components while attempting to increase processing power and performance. This is leading to increased interest in thinner printed wiring boards and finer line width and pitch. However, these goals can be hindered by the occurrence of warpage in the manufacturing and assembly process of electronic packages from mismatches in thermomechanical properties of the materials used. Warpage can be problematic as it leads to misalignments during package assembly, reduced tolerances, and a variety of operational failures. Current warpage prediction techniques typically utilize volume averaging to estimate material properties in layers of copper mixed with interlayer dielectric material. These techniques use copper percentages for an entire layer and do not account for trace orientation. This paper describes the development of a new methodology to predict the warpage of a particular substrate. The developed methodology accounts for both the trace pattern planar density and planar orientation in material property calculations for each layer of a multilayer substrate. This process has been used to calculate the warpage of actual substrates and the results of using the developed methodology are shown to agree well with experimental data.      

Laser sintering of thick-film PTC thermistor paste deposited by micro-pen direct-write technology

In this paper, laser sintering has been used to process thermal sensitive material deposited by micro-pen direct-write technology. Lines of thick-film PTC thermistor paste were deposited by micro-pen direct-write technology and irradiated by a continuous-wave laser with varied power density and scanning speed. Line widths, sheet resistivities and temperature coefficients of resistivity were measured as a function of laser power density, scanning speed, coating thickness and overlapped value. The mechanism of laser sintering thermistor paste was discussed. Laser sintering enabled finer thermistor lines to overcome the resolution limitation of micro-pen deposition without the use of any high temperature post processing. The thermistors exhibited excellent electrical performance and resistance tolerance equivalent to traditional oven-fired electronic paste.     

Effects of fluid properties on dispensing processes for electronics packaging

The fluid dispensing process has been widely employed in electronics packaging manufacturing to deliver fluid materials (such as epoxy, encapsulant, adhesive) on substrates or printed circuit boards (PCBs) for the purpose of die attachment, encapsulation, coating, or surface mounting. In this process, the fluid properties such as How behavior, surface tension, and contact angle can have a significant influence on the How rate of the fluid dispensed and the profile of fluid formed on the substrate or PCB, thereby affecting the quality of electronics packaging. At present, massive measurements are always required to characterize the fluid properties by using specific instruments, and the procedure of measuring is time-consuming. This paper presents a method upon which the fluid properties and their influence on the dispensing process can be readily identified from a few measurements of the process. By experiments, this method was proven to be not only cost and time effective but also promising for the investigation into the effects of fluid properties on the dispensing process.     

Escape routing design to reduce the number of layers in area array packaging

High density multilayer substrate technologies are indispensable to accommodate high input/outputs (I/Os) fine pitch area array integrated circuits (ICs), chip scale packages/ball grid arrays (CSP/BGAs) in the coming packaging generation. They must provide not only a high wiring density, but also an acceptable low cost, short turn around time (TAT) and reliability. Reduction of the number of layers is expected to be a reasonable solution for the conflicting demands. General approaches to reduce the layer count have been to decrease the size of the routing line width and spacing. However, they need changes in the manufacturing processes and materials, causing an increased cost. From escape routing design viewpoint, effects of routing manner on the layer count have been studied. A preferential routing creates specific pad geometry resulting in a high wiring efficiency. This effect can be estimated with an increase in the number of lines per layer routable as a contribution of "the hybrid channel," depending on capture pad pitch-pad diameter-line width-interline space relationship. It is one of the remarkable cases recognized that, within one line per channel rule, the preferential routing can be almost equivalent to that by two lines per channel with regard to the wireability. Its better effect on cost and TAT can also be expected compared with the two thinner sized lines per channel rule, since nothing changes in both manufacturing processes and materials is needed. This method is applicable immediately to packages and boards for assembly of the high I/O flip chips, CSPs, and BGAs.     

Vacuum Web Coating - State of the Art and Potential for Electronics

Going flexible seems to be a major trend for a variety of electronic applications such as displays, printed circuit boards, solar cells, and solid-state lighting. Driving forces, which may often include the function of "flexibility," are the potential to build units with less thickness and with less weight or the ability for very-large-area applications. Last but not least, there is the need for a remarkable reduction of production costs, which can be fulfilled by changing the production process from sheet processing to roll to roll. The first vacuum web coater was built 70 years ago, and vacuum web coating is currently used for a wide variety of applications. In the packaging industry, aluminum coating is primarily used for barrier improvement of plastic substrates. Such coatings are deposited with an evaporation process in machines of up to 4-m coating widths on rolls up to 60 000-m length and at coating speeds of more than 16 m/s. For capacitor production, thin webs with thicknesses down to the submicrometer range are vacuum-coated with aluminum, silver, or zinc layers, and uncoated stripes or patterns are also needed. Vacuum-coated web-shaped substrates can also be used for antireflective, antistatic function in the front of monitors, as window films for cars and architectural applications or as front electrodes for touch panels as a few examples. Different coating tools such as evaporation, sputtering, plasma-enhanced chemical-vapor deposition (PECVD), as well as pretreatment tools and inline layer measurement systems are available. Many of the currently available tools and processes existing in the web coating industry may become useful for upcoming electronic applications, but special demands for these new applications, such as exact area tracking, zero defects, roll-to-roll masking, and reduced substrate temperature during coating, require further development of machine design and process technology. This paper will summarize the state of the art of vacuum w     

Optimization of via formation in photosensitive dielectric layersusing neural networks and genetic algorithms

Via formation using photosensitive polymer technology can reduce process cost by reducing process complexity and is hence of great interest in electronics packaging substrate fabrication. However, to overcome technical difficulties and to facilitate low-cost manufacturing, process modeling, optimization and control are required. In this paper, a process optimization approach for via formation in dielectric layers composed of photosensitive benzocyclobutene (BCB) for high density interconnect (HDI) in MCM-L/D substrates is presented. A series of designed experiments are used to characterize the via formation workcell (which consists of the spin coat, soft bake, expose, develop, cure, and plasma de-scum unit process steps). Neural network process models are then constructed to characterize via yield and geometry, as well as film thickness, retention, and uniformity. These models are used for process optimization using genetic algorithms (GA's) and hybrid combinations of GA's with the Powell algorithm and with the simplex algorithm. The optimized process recipes are verified experimentally. Comparison of the three approaches reveals that the hybrid GA/simplex method yields superior recipes     

Run-by-run estimation-based control of meniscus coating

This paper describes the application of process control techniques to the meniscus coating process. Meniscus coating may be used to deposit polymers used in integrated circuits and electronics packages. Three control schemes are presented and each employs Kalman filtering to identify process coefficients. The three schemes differ according to the process model and amount of process information that is available. The dominating process parameters are applicator speed and material viscosity which affect the output of film thickness. The first scheme addresses the case where the least amount of information is known; viscosity is not measured. Identification and control is applied to a meniscus coater that does not have hardware to sense viscosity. In the second control scheme, viscosity sensors are used. However, limitations of the process model and the nature of the process produce controller lag in the presence of a shift in the process. This lag is undesirable in a manufacturing setting, therefore the third scheme is introduced which improves upon the second by reducing lag. The third scheme employs curves fitted to a history of process data to reinitialize the coefficient estimates when there is a shift in the process     

Ultra-thin high-density LSI packaging substrate for advanced CSPs and SiPs

An ultra-thin high-density LSI packaging substrate, called multi-layer thin substrate (MLTS), is described. It meets the demand for chip scale packages (CSPs) and systems in a package (SiPs) for use in recently developed small portable applications with multiple functions. A high-density build-up structure is fabricated on a Cu plate, which is then removed, leaving only an ultra-thin, high-density multi-layer substrate. MLTS has (1) excellent registration accuracy, which enables higher density and finer pitch patterning due to the use of a rigid, excellent-flatness Cu base plate; (2) a thinner multi-layer structure due to the use of a core-less multi-layer structure; (3) excellent reliability, supported by the use of an aramid-reinforced epoxy resin dielectric layer; and (4) a cost-effective design due to the use of fewer layers fabricated using a conventional build-up process. A prototype high-density CSP (0.4-mm pitch/288 pins/4 rows/10 mm²) was fabricated using a 90-μm-thick MLTS (with a solder resist layer). Testing demonstrated that it had excellent long-term reliability. A prototype ultra-thin, high-density SiP (0.5-mm pitch/225 pins/11 mm²/0.93 mm thick) was also fabricated based on MLTS. MLTS consists of only two conductor layers (total thickness: 90 μm) while an identical-function build-up printed wiring board needs four conductor layers (total thickness: 300 μm). With its thinner core-less multi-layer structure, MLTS enables the fabrication of ultra-thin, high-density SiPs.     

Printing Nanostructures with a Propelled Anti‐Pinning Ink Droplet

Striving for cheap and robust manufacturing processes has prompted efforts to adapt and extend methods for printed electronics and biotechnology. A new “direct‐write” printing method for patterning nanometeric species in addressable locations has been developed, by means of evaporative deposition from a propelled anti‐pinning ink droplet (PAPID) in a manner analogous to a snail‐trail. Three velocity‐controlled deposition regimes have been identified; each spontaneously produces distinct and well‐defined self‐assembled deposition patterns. Unlike other technologies that rely on overlapping droplets, PAPIDs produce continuous patterns that can be formed on rigid or flexible substrates, even within 3D concave closed shapes, and have the ability to control the thickness gradient along the pattern. This versatile low cost printing method can produce a wide range of unusual electronic systems not attainable by other methods.     

Initial investigations into low-cost ultra-fine pitch solderprinting process based on innovative laser printing technology

Advances in electronics packaging and assembly technology are driving increased demand for ultra-fine pitch solder deposition. In this work, innovative solder deposition techniques based on laser printing are investigated for low-cost ultra-fine pitch printing applications. This paper investigates the feasibility of using solder particles in off-the-shelf xerographic technology. The physics of two development systems (dual component and monocomponent) is discussed. This inquisition leads to a discussion of triboelectric charging of the solder toners, coating the solder with thin dielectrics, and charge induction by an applied electric field. This initial investigation explores the basic feasibility of xerographic printing techniques using solder and defines future work     

8英寸Si衬底上高质量AlGaN/GaN HEMT结构的生长

在8英寸(1英寸=2.54 cm)的Si衬底上采用金属有机化学气相沉积(MOCVD)生长了高质量、无龟裂的GaN薄膜和AlGaN/GaN高电子迁移率晶体管(HEMT)结构.通过调节应力调控层的结构,厚度为5 μm的GaN膜层翘曲度低于50 μm.采用X射线衍射(XRD)对GaN薄膜的(002)和(102)衍射峰进行扫描,其半峰全宽(FWHM)分别为182和291 arcsec.透射电子显微镜(TEM)截面图显示GaN外延层的位错密度达到了3.5×107/cm2,证实了在大尺寸Si衬底上可以制作高质量的GaN薄膜.AlGaN/GaN HEMT结构的二维电子气浓度和载流子迁移率分别为9.29×1012/cm2和2 230 cm2/(V·s).基于这些半绝缘AlGaN/GaNHEMT结构所制作的功率电子器件的输出电流可达20 A,横向击穿电压可达1 200 V.     

Efficient Bump-Pad Geometries to Relax Design Rules Required for High Density I/O Area Array Packaging

Continuous increase in density of interconnection is demanded as a result of advances in the performance of electronic devices. Because a finer design rule is necessary in the conventional routing design to achieve the higher density, especially in the chip-to-package connection, this trend will bring various problems in both its manufacturing process and reliability. To avoid such a risk, approaches from an escape routing design standpoint might be expected to give an effective solution. This paper presents a design method efficient to relax the severe demands for an ultra-fine wiring rule that leads to a costly manufacturing process and a poor interconnection reliability. This method has been developed focusing on a bump-pad geometry that provides an efficient hybrid channel allowing a higher routability. A specific pad geometry “microvilli” type hybrid channel has been revealed to be applicable in both square grid and hexagonal arrays and to achieve a notable relaxing in trace width and spacing. With this hybrid channel, traces with twice the width become allowable for escape routing compared with the conventional geometry. The effects of this relaxation, not only on manufacturing cost but also on the performance and reliability of packaging, are discussed.      

Flexible Induction Heater Based on the Polymeric Thin Film for Local Thermotherapy

Local delivery of physical energy, such as heat, is promising for the treatment of target lesions without the unintended distribution of heat to other normal tissue. However, the heating device must be equipped with an external power source or strong magnetic field to operate the device, and many of them are too large to be placed inside the body. In this regard, wireless, lightweight, flexible electronics can be used for the miniaturization of implantable devices. In this study, a flexible induction heating (IH) device is reported that integrates inkjet-printed wirings and flexible polymeric thin films, specifically Au nanoink-based wirings (thickness: 1.5 µm) and a biodegradable poly(D, L-lactic acid) (PDLLA) thin film (thickness: 5 µm). A unique method of transferring the inkjet-printed Au nanoink wiring onto the PDLLA thin film realizes the integration of the following technical features in one device: biocompatible packaging, a printed IH system, and body conformability. The resulting thin-film IH device is successfully placed on a hepatic lobe of a beagle dog, which allows for a local increase in temperature of 7 °C after 1-min power feeding without tissue inflammation. The thin-film IH device is expected to provide minimally invasive thermotherapy when combined with endoscopic surgery.     

Trade-off analysis on cost and manufacturing technology of an electronic product: Case study

A trade-off analysis on the cost and system packaging metrics of an electronic product aimed at the commercial/retail industry has been carried out. By comparing the system cost and packaging metrics with those of comparable consumer products, we have determined that there is opportunity for significant cost, size, and weight reduction of the overall electronics packaging system. These include the use of fine pitch IC packages, smaller discrete components, denser PCB wiring technology, double sided IC package surface mount, surface mount connectors, and improved plastics for the product housing. The analysis concluded that PCB area reduction of 40%, using a single PCB instead of three boards, reduction in board cost of over 50% and product weight reduction of over 28% are possible using available technologies.