Channel noise modeling of deep submicron MOSFETs

This brief presents a new channel noise model using the channel length modulation (CLM) effect to calculate the channel noise of deep submicron MOSFETs. Based on the new channel noise model, the simulated noise spectral densities of the devices fabricated in a 0.18 /spl mu/m CMOS process as a function of channel length and bias condition are compared to the channel noise directly extracted from RF noise measurements. In addition, the hot electron effect and the noise contributed from the velocity saturation region are discussed.     

Analytical modeling of thermal noise in deep submicron MOSFETs

An analytical modeling of MOSFETs channel noise is proposed by considering short-channel effects of deep submicron MOSFETs, such as mobility degradation, hot carrier, bulk charge, and channel length modulation effect. The model is only dependent on bias, size, and technology of MOSFETs, and hence is suitable for low-noise RF IC design. Noise parameters of MOSFETs are achieved and good agreement between calculated and measured results is demonstrated.     

Analytical drain thermal noise current model valid for deep submicron MOSFETs

In this paper, a physics-based MOSFET drain thermal noise current model valid for deep submicron channel lengths was derived and verified with experiments. It is found that the well-known /spl mu/Q/sub inv//L/sup 2/ formula, previously derived for long channels, remains valid for short channels. Carrier heating in the gradual channel region was taken into account implicitly with the form of diffusion noise source and then impedance field method taking velocity saturation effect was used to calculate the external drain thermal noise current. The derived model was verified by experimental noise for devices with channel lengths down to 0.18 /spl mu/m. Excellent agreement between measured and modeled drain thermal noise was obtained for the entire V/sub GS/ and V/sub DS/ bias regions.     

Characterization of interface degradation in deep submicron MOSFETs by gate-controlled-diode measurement

The gate-controlled-diode (GCD) characteristic of a deep submicron MOSFET is changed dramatically following a Fowler-Nordheim (FN) injection. The changes can be explained by the trap generation on the Si surface close to the channel/drain edge and the interface trap generation in the channel region. By examining the change in the reverse drain current under accumulation and inversion in the GCD measurements, the information of trap generation in the surface region close to the channel/drain edge is obtained (note that the trap generation in this region could be different from that in other interface regions); and by measuring the reverse drain current under depletion, the interface trap generation in the channel region is obtained.     

Drain current thermal noise modeling for deep submicron n- and p-channel MOSFETs

The drain current thermal noise has been measured and modeled for the short-channel devices fabricated with a standard 0.18 μm CMOS technology. We have derived a physics-based drain current thermal noise model for short-channel MOSFETs, which takes into account the velocity saturation effect and the carrier heating effect in gradual channel region. As a result, it is found that the well-known Q_inv/L²––formula, previously derived for long-channel, remains valid for even short-channel. The model excellently explained the carefully measured drain thermal noise for the entire V_GS and V_DS bias regions, not only in the n-channel, but also in the p-channel MOSFETs. Large excess noise, which was reported earlier in some other groups, was not observed in both the n-channel and the p-channel devices.     

Static and low-frequency noise characterization in submicron MOSFETs for memories cells applications

In this paper, we present the extraction of oxide traps properties of n-metal-oxide-semiconductor (N-MOS) field effect transistors with W×L=0.5×0.1 μm² using low-frequency (LF and random telegraph signal) noise and static I(V) characterizations. The impact of oxide thickness, on static and noise parameters is analyzed. Static measurements on N-MOS devices with different tunnel oxide thickness show anomalies (a significant increase in V_t values for low temperature and kink effect) attributed to traps located in the oxide. From LF noise analysis we find that 1/f noise stems from carrier number fluctuations. The slow oxide trap concentration deduced from the noise data is about 10¹⁵ eV/cm³ in agreement with the state-of-the-art gate oxides. Finally, drain current RTS amplitude as large as 10% have been observed.     

Projecting lifetime of deep submicron MOSFETs

A detailed examination of hot-carrier-induced degradation in MOSFETs from a 0.25-μm and a 0.1-μm technology is performed. Although the worst case stress condition depends on the stress voltage, channel length, and oxide thickness, I_b,peak is projected to be the worst case stress condition at the operating voltage for both nMOSFETs and pMOSFETs. Post-metallization anneal (PMA) in deuterium can significantly improve the device lifetime if the primary degradation mechanism at the stress condition is interface trap generation due to interface depassivation by energetic electrons     

A new field dependent mobility model for high frequency channel thermal noise of deep submicron RFCMOS

In this paper, a new field dependent effective mobility model including the drain-induced vertical field effect (DIVF) is presented to calculate the channel thermal noise of short channel MOSFETs operating at high frequencies. Based on the new channel thermal noise model, the simulated channel thermal noise spectral densities have been compared to the channel thermal noise directly extracted from noise measurements on devices fabricated using GLOBALFOUNDRIES’ 0.13 μm RFCMOS technology. The comparison has been done across different channel length, finger width and number of finger for different frequencies, gate biases and drain biases. Excellent agreement between simulated and extracted noise data has shown that the proposed model is scalable over different dimensions and operating conditions. The proposed model is simple and can be easily implemented in a circuit simulation environment.     

Excess high frequency noise and flicker noise in MOSFETs

The noise parameter α=R_ng_m, where R_n is the noise resistance and g_m the transconductance, was measured for n- and p-channel MOSFETs as a function of frequency with the temperature T as a parameter. At lower frequencies α varies as 1/f, as expected for flicker noise, whereas at higher frequencies α attains a limiting value α_∞ that is larger than expected for thermal noise. Arguments are presented whether this high-frequency noise can be hot electron noise. The flicker noise resistance R_mf has a much stronger temperature dependence for n-channel than for p-channel devices; this is related to the energy dependence of the surface state distribution in the forbidden gap.     

High frequency characterization of gate resistance in RF MOSFETs

The gate resistances (R_g) of MOSEETs with various geometries have been characterized at various bias conditions at high frequency (HF). The results show that R_g decreases when either channel length (L_f) or per-finger-width (W_f) increases before reaching a critical L_f or W _f, and then starts to increase as L_f or W_f continues to increase. The irregular geometry dependence of R_g is caused by the combined distributed effects in both the gate and channel at HF. Stronger contribution from the distributed channel to the effective R_g is observed in the saturation region of devices with longer channel length (L_f) at lower gate bias (V_gs). The results show that an optimized design of the per-finger-width is necessary for an rf MOSFET to achieve the lowest effective R_g, which is desirable in rf applications     

Induced gate noise in MOSFETs revisited: The submicron case

At high frequencies the gate admittance of the MOSFET contains a conductive component because of the capacitive coupling of the gate electrode to the channel. The thermal noise fluctuations, originating in the channel, induce a gate current outwards from the gate electrode. Based on a proved two-region model for the drain current noise of a sub-micron MOSFET, it is shown that the calculated gate-noise current increases significantly, compared to that predicted by a classical model, valid for long channel devices.     

Analytical modeling of MOSFETs channel noise and noise parameters

Simple analytical expressions for MOSFETs noise parameters are developed and experimentally verified. The expressions are based on analytical modeling of MOSFETs channel noise, are explicit functions of MOSFETs geometry and biasing conditions, and hence are useful for circuit design purposes. Good agreement between calculated and measured data is demonstrated. Moreover, it is shown that including induced gate noise in the modeling of MOSFETs noise parameters causes /spl sim/5% improvement in the accuracy of the simple expressions presented here, but at the expense of complicating the expressions.     

深亚微米部分耗尽SOI MOSFETs STI应力效应研究

The STI stress effect is investigated based on the 0.13 m SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences（IMECAS）. It shows that the threshold voltage and mobility are all affected by the STI stress. The absolute value of the threshold voltage of NMOS and PMOS increased by about 10%, the saturation current of NMOS decreases by about 20%, while the saturation current of PMOS increases by about 20%. It is also found that the lower temperature enhances the STI stress and then influences the device performance further. Then a macro model for this effect is proposed and is well verified.     

Interconnect noise analysis and optimization in deep submicron technology

The migration to using ultra deep submicron (UDSM) process, 0.25 /spl mu/m or below, necessitates new design methodologies and EDA tools to address the new design challenges. One of the main challenges is noise. All different types of deep submicron such as cross talk, leakage, supply noise and process variations are obstacles in the way of achieving the desired level of noise immunity without giving up the improvement achieved in performance and energy efficiency. This article describes research directions and various levels of design abstraction to handle the interconnect challenges. These directions include approaches to adopt new analytical methods for interconnects, physical design levels and finally ways to face these challenges early in a higher level of the design process.     

New method for extraction of effective channel length in submicron MOSFETs

A new method for effective channel length extraction in submicron MOSFETS is presented. It is based on measurements of the saturation voltage V/sub DSAT/ in devices with different channel lengths. The method has been tested using submicron double diffused drain (DDD) MOS devices.<>     

Short channel effect in deep submicron PDSOI nMOSFETs

Deep submicron partially depleted silicon on insulator (PDSOI) nMOSFETs were fabricated based on the 0.35μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS). Mechanisms determining short-channel effects (SCE) in PDSOI nMOSFETs are clarified based on experimental results of threshold voltage dependence upon gate length. The effects of body bias, drain bias, temperature and body contact on the SCE have been investigated. The SCE in SOl devices is found to be dependent on body bias, drain bias and body contact. Floating body devices show a more severe reverse short channel effect (RSCE) than devices with body contact structure. Devices with low body bias and high drain bias show a more obvious SCE.     

深亚微米PDSOI nMOSFETs的短沟道效应

基于中国科学院微电子所开发的0.35µmSOI工艺制备了深亚微米PDSOI nMOSFET。根据阈值电压依赖沟道长度的测试结果阐述了决定PDSOI nMOSFET 短沟道效应的机理。研究了体偏置、漏偏置以及温度和体接触对PDSOI nMOSFET 短沟道效应的影响,发现短沟道效应依赖于体偏置、漏偏置以及体接触。浮体器件比有体接触结构的器件的反短沟道效应更严重,器件在低体偏和高漏偏下会表现出更明显的短沟道效应。     

Hot electron noise effects in buried channel MOSFETs

Measurements are reported on a 2.0 μmeter buried channel MOSFET. Because of the short channel length, the device showed large hot electron effects. The noise reaches a limiting value above a few MHz; this is attributed to hot electron thermal noise. The parameter $\text{α = (}\text{q}\text{2kT}\text{)(}\text{I}{}_{\mathrm{eq}}\text{g}{}_{\mathrm{m}}\text{)}$ is plotted as a function of the absolute temperature T; it increases with decreasing temperature, as expected for hot electron effects.     

On the determination of the time-dependent degradation laws and device lifetime in deep submicron n- and p- channel SOI MOSFETs

Two-stage device degradation induced by hot-carrier injection is thoroughly investigated in deep submicron n- and p-channel silicon-on-insulator (SOI) MOSFETs. A logarithmic saturation phenomenon relative to the initial power time-dependent law can describe the degradation for long stress time. In this paper, various lifetime prediction methods based on the logarithmic time-dependent law are proposed and compared. The gate length dependence of the maximal drain biases in order to obtain a 10 year lifetime is also addressed with these various extrapolation techniques.     

Low frequency noise in thin gate oxide MOSFETs

Low frequency, 1/f, noise of the drain current, I_D, fluctuations was measured on a series of Si MOSFETs with the gate oxide thickness, t_ox, varied from 25 to 40 Å by steps of 5 Å. The salient point of this work is a demonstration that, at sufficiently low I_D intensities, a mean low noise level in the MOSFETs is reduced as the gate oxide becomes thinner. This is explained assuming that the noise originates from the electron capture/release on Si/SiO₂ interface/border traps. The flat band voltage fluctuations, observable as noise, are linked then to the oxide charge fluctuations by a factor, that is inversely proportional to the gate capacitance, C_ox, and thus proportional to t_ox. At higher I_D, the results are more complicated, as the access resistance noise is also involved. We provide an interpretation of the ensemble of the data and show that the noise analysis can furnish quantitative estimates of several device characteristics. Device degradation and its consequences for the low frequency noise at higher current levels are also discussed.