基于相控阵天线的RFID系统设计

设计了一种可扩展阅读范围的相控阵天线RFID系统。采用Intel R1000阅读器开发平台、MASWSS0204开关芯片,研制了功率分配器、移相器、天线阵,搭建了符合ISO 18000-6C和EPC globalGen 2标准、中心频率为915 MHz RFID阅读器系统。系统引入相控阵原理,并对阅读器进行了简单改动,设计了相控阵RFID系统的硬件组成结构和软件工作流程。设计的相控天线阵列由2×2个微带天线单元、3个功率分配器和1个移相器组成,使用FR4介质板材料制作。实验结果表明,该系统增大了RFID信号的覆盖范围。     

Ka‐band phased patch array antenna integrated with a PET‐controlled phase shifter

In this article, a 4 × 4 linear‐phased patch array antenna, consisting of four 1 × 4 patch subarrays and a true time‐delay multiline phase shifter, is proposed on a thin film liquid crystal polymer substrate at Ka‐band. The patch antenna is designed with a gain of 6 dBi at 35 GHz and a bandwidth of 23% centered at 35 GHz. To enhance the gain and symmetrize the beam patterns of the 4 × 4 array, a 1 × 4 patch subarray in the E‐plane was designed and characterized. The subarray produces an enhanced gain of 11 dBi and a wide beamwidth of ±38° in the H‐plane for beam steering. The proposed phase shifter comprises a 1 × 4 microstrip line power splitter and a piezoelectric transducer‐controlled phase perturber. A large phase variation of up to 370° and a low insertion loss of less than 2 dB were demonstrated for the phase shifter at Ka‐band. The integrated phased array attains a gain of 15.6 dBi, and a continuous true‐time delay beam steering of up to 33 ± 1° from 31 to 39 GHz. © 2015 Wiley Periodicals, Inc. Int J RF and Microwave CAE 26:199–208, 2016.     

A low‐profile circularly polarized dielectric patch antenna and array

A square dielectric patch (DP) resonator fusing with the bottom substrate is studied for designing low‐profile circularly polarized (CP) antenna. Based on the theoretical investigation using the constructed analysis model, it can be found that the proposed DP resonator possesses a pair of degenerate dominate modes (TM₁₀₁ and TM₀₁₁), which can be split by introducing perturbations on the DP resonator and then used to design CP antenna fed by a microstrip line directly. To verify the proposed idea, a 2 × 2 array fed by a dual Marchand balun network is designed and implemented. Reasonable agreement between the measured and simulated results is observed. Experimental results show that a measured impedance bandwidth is 380 MHz (5.18‐5.56 GHz) for |S₁₁| < ?10 dB and the 3‐dB axial ratio bandwidth is 90 MHz (5.32‐5.41 GHz). The measured gain is up to 11.77 dBic with a cross polarization of about ?20 dB in the boresight direction.     

Application of principal component analysis based effective digital predistortion technique for low‐cost FPGA implementation

This article investigates the issue of low‐cost digital predistortion (DPD) implementation in fixed‐point field programmable gate array (FPGA) by considering the bit‐resolution along with lower number of coefficients. The impact of principle component analysis (PCA) on bit‐resolution of DPD solution is proposed within the context of established DPD models. Unlike previously proposed PCA based solutions, it is established by simulation and measurement that the numerical stability problem associated with popular models such as memory polynomial (MP) can be alleviated when PCA is applied to the observation data matrix. It is reported with measurement results that PCA based model provides better linearization performance with the least memory size requirement and number of LUTs in 16‐bit fixed‐point FPGA operation than MP, orthogonal memory polynomial (OMP), and generalized memory polynomial (GMP) models. The performance of the proposed model, is evaluated in terms of normalized mean square error, adjacent channel error power ratio, matrix condition number, and dispersion coefficient for continuous Class‐AB and ZX60‐V63+ power amplifiers using wide code‐division multiple access signal (WCDMA) and long term evolution (LTE) signal with peak‐to‐average‐power ratio (PAPR) around 9.895 and 11.92 dB, respectively.