Effects of hot-carrier trapping in n- and p-channel MOSFET's

Detailed measurements of hot-carrier gate current and its trapping effects were studied on both n- and p-channel MOSFET's down to submicrometer channel lengths. Comparison of the measurements for these two types of devices is made. No hot-hole gate current or hot-hole trapping was detected in p-channel MOSFET's. A hot-electron gate current is present not only in n-channel MOSFET's, but also in p-channel MOSFET's where the current is increased by hot-electron trapping. By trapping hot electrons uniformly over the channel in n-MOSFET's, it was shown that hot-electron trapping produces only negative oxide charge without generating interface traps.     

Observation of hot-hole injection in NMOS transistors using a modified floating-gate technique

A modified floating-gate technique for measuring small gate currents in MOSFET's with very high resolution (0.01 fA) is described. Using this technique, gate oxide currents due to hot-carrier injection are measured in n-channel MOSFET's. The conventional negative channel hot-electron gate oxide current is observed nearV_{g} = V_{d}and a small positive gate current occurs at low Vg. We argue that the dependencies of this small positive current on Vgand gate length, together with results from a separate floating-source experiment, are consistent only with hot-hole injection.     

Relationship between hot-electrons/Holes and degradation of p- and n-channel MOSFET's

The relationship between hot electrons and holes and the degradation of p- and n-channel MOSFET's is clarified by experimentally determining where along the channel the SiO2is most affected by each type of carrier. Transconductance degradation is found to be caused by hot-hole injection in pMOSFET's, and by hot-electron injection in nMOSFET's.     

Relationship between MOSFET degradation and hot-electron-induced interface-state generation

Device degradation due to hot-electron injection in n-channel MOSFET's is mainly caused by mobility degradation and reduced mobile charges in the channel introduced by interface-state generation. With the use of simple gradual-channel approximation (GCA), a linear relationship is derived between the threshold shift, relative transconductance reduction, and the number of interface states generated. This model provides a link between the electrical characteristics of a degraded device and its physical damages and, therefore, is a vital tool in the study of hot-electron-induced device degradation mechanisms.     

Correlation between substrate and gate currents in MOSFET's

A correlation between substrate and gate currents in MOSFET's is described and analyzed. Both of these currents are the result of hot-electron mechanisms. Theory for these mechanisms has been applied to derive an expression for gate current in terms of substrate current and parameters that can be calculated from processing data and bias conditions. The theory is successfully applied to a series of n-channel MOSFET's with a range of geometries and bias values.     

A model for the relation between substrate and gate currents in n-channel MOSFET's

The gate current in n-channel MOSFET's normalized to the source current is expressed as a function of the substrate current normalized to the source current by means of an impact ionization model. The ratio of the electron mean free path for impact ionization to that for optical phonon scattering, which is the most important among the various related device parameters, is determined by indirect measurement of the gate current using stacked-gate MOSFET's. The present model has been applied to interpret the experimental results obtained from samples with a variety of device dimensions. Limitation by the hot-electron emission, which is an important design constraint for submicrometer-gate MOS devices, is studied for single-gate and stacked-gate MOSFET's in comparison with other limiting factors.     

Comparison of characteristics of n-channel and p-channel MOSFET's for VLSI's

A comparison of device characteristics of n-channel and p-channel MOSFET's is made from the overall viewpoint of VLSI construction. Hot-carrier-related device degradation of device reliability, as well as effective mobility, is elaborately measured for devices having effective channel lengths of 0.5-5 µm. From these experiments, it is found that hot-electron injection due to impact ionization at the drain, rather than "lucky hot holes," imposes a new constraint on submicrometer p-channel device design, though p-channel devices have been reported to have much less trouble with hot-carrier effects than n-channel devices do. Additionally, p-channel devices are found to surpass n-channel devices in device reliability in that they have a highest applicable voltage BVDCthat is more than two times as high as for n-channel devices. It is also experimentally confirmed that the effective hole mobility approaches the effective electron mobility when effective channel lengthL_{eff} < 0.5µm. These significant characteristics of p-channel devices imply that p-channel devices have important advantages over n-channel devices for realization of sophisitcated VLSI's with submicrometer dimensions. It is also shown that hot holes, which may create surface states or trap centers, play an important role in such hot-carrier-induced device degradation as transconductance degradation.     

Hot-electron-induced interface state generation in n-channel MOSFET's at 77 K

Hot-electron-induced degradation in n-channel Si MOSFET's as a result of stress voltages applied at 77 K was studied. The devices were stressed at 77 K for 48 h with a drain voltage of 5 V and a gate voltage corresponding to that at which maximum substrate current was measured. Comparison of pre-stress and post-stress electrical characteristics for forward and for inverse mode operation at room temperature and at 77 K indicate that the observed degradation was due to the generation of hot-electron-induced acceptor interface states at the drain end of the device approximately 0.09 eV below the Si conduction band edge. No trapped charge resulting from hot-electron injection into the gate oxide was observed. The charge associated with the filled interface states had no observable effect on effective channel electron mobility at room temperature, and reduced that at 77 K by no more than 25 percent of the pre-stress value. Operation of CMOS inverters in either logic state (OFF, ON) resulted in no degradation of either device. Operation in a switching mode at 77 K did result in degradation of the n-channel device but not the p-channel FET. The observed degradation is thought to be correlated with the substrate current generated during the switching transient.     

Substrate current at cryogenic temperatures: Measurements and a two-dimensional model for CMOS technology

This work characterizes the temperature, channel length, and voltage dependences of substrate current, and presents a local model describing this behavior using Shockley's lucky electron (LE) model as a basis. For n-channel (p-channel) devices, the model is extended using a Maxwell-Boltzmann (MB) distribution of hot-electron (hole) energies above (below) the conduction (valence) band minimum (maximum). The model has been implemented in CADDET, a 2-D device simulator, and is able to explain all of the important features of substrate current which have been reported to date. The model is discussed in the context of works which look at both the local and physical nature of the impact ionization phenomenon. Based on this discussion, the model's parameters are shown to have a solid physical basis, requiring no reliance on curve fitting. The agreement between data and simulations thus enhances physical understanding of substrate current in MOSFET's, and warrants confident design of CMOS technologies for cryogenic operation.     

1 µm MOSFET VLSI technology: Part IV—Hot-electron design constraints

An approach is described for determining the hot-electron-limited voltages for silicon MOSFET's of small dimensions. The approach was followed in determining the room-temperature and the 77 K hot-electron-limited voltages for a device designed to have a minimum channel length of 1 µm. The substrate hot-electron limits were determined empirically from measurements of the emission probabilities as a function of voltage using devices of reentrant geometry. The channel hot-electron limits were determined empirically from measurements of the injection current as a function of voltage and from long-term stress experiments. For the 1 µm design considered, the channel hot-electron limits are lower than the substrate hot-electron limits. The maximum voltage,V_{DS} = V_{GS}, is 4.75 V at room temperature (25°C) and 3.5 V at 77 K. More details of the voltage limits as well as the approach for determining them are discussed. Examples of circuits designed with these devices to operate within these hot-electron voltage limits are also discussed.     

Role of hot-hole injection in hot-carrier effects and the small degraded channel region in MOSFET's

Drain avalanche hot-carrier (DAHC) injection, which imposes the most severe limitations on n-channel MOS device design, is investigated from the viewpoint of surface-state generation and its localized area in the channel. It is shown, using the charge pumping technique, that the surface states are mainly created by hot-hole injection, and its small degraded area stretches toward the source region with increased stress time. A remarkable correlation between the increase of surface-state density, transconductance degradation, and substrate current is also described. In addition, to clarify the role of hot-hole injection, p-channel devices, as well as n-channel devices, are used, and hot-hole injection is shown to create more surface states than hot-electron injection.     

Observation of double-hump substrate current in funnel-shape transistors

n-channel transistors with a funnel-shape (FS) channel region were fabricated with thin gate oxide (21 nm) and short-channel length (1 µm) to study the effects of channel shapes on hot-electron effects. Two interesting phenomena are observed. First, the double-hump substrate current phenomenon is found when operating with wider channel close to drain side (wide-drain mode), while the narrow-drain mode shows the usual single-peak substrate current characteristics. Second, an enhanced gate current injection is found in the wide-drain mode, which is surprising as substrate current is actually lower in this mode. The finding is interesting as it suggests that floating-gate FS-tranistors with short-channel length and thin gate oxide are more efficient in programming when operating in wide-drain mode. This contradicts the previous SIMOS EPROM device that utilizes funnel-shape channel region operating in narrow-drain mode. The discrepancy is ascribed to the occurrence of double-hump effect in substrate current and associated enhanced gate current injection in FS-transistors when channel length and gate oxide are scaled down.     

Analytical model and characterization of small geometry MOSFET's

Electrical characteristics of small geometry p-channel and n-channel MOSFET's are characterized based on an analytical model that includes short-channel, narrow-channel, and carrier-velocity-saturation effects. Theoretical results on threshold voltage, threshold-voltage shift by a substrate bias voltage, and drain current are in good agreement with the experimental results over wide ranges of channel lengths from 1 to 9 µm and channel widths from 2 to 14 µm. A comparison of the electrical characteristics of MOSFET's with and without field implantation leads to the conclusion that the field implantation is the main cause of the narrow-channel-width effect on threshold-voltage increase and drain-current degradation. The carrier-velocity-saturation effect starts to appear at the 3-µm channel length for the n-channel device and at 1 µm for the p-channel device under 5-V operation. According to the theoretical analysis of a 1-µm-channel inverter circuit, a CMOS inverter has superior noise immunity with 1.4 to 2.0 times larger driving-current capability in a load MOS device and requires 9 percent less area than a 1-µm n-channel enhancement/depletion inverter.     

Hot-electron currents in very short channel MOSFET's

The behaviors of the hot-electron gate and substrate currents in very short channel devices were studied. For a test device with electrical channel length of 0.14 µm, the hot-electron substrate current can be detected at 0.9-V drain voltage which is lower than the silicon band gap. The gate current can be measured at 2.35-V drain voltage, which is lower than the oxide-silicon energy barrier for electrons. These measurements support the quasi-thermal-equilibrium approximation and suggest that the hot-electron-induced problems cannot be eliminated in future VLSI MOSFET's of arbitrarily short channels by reducing the drain bias below some constant critical energies. An empirical relationship between the effective electron temperature and the field is found to be Te= 9.05 × 10^-3E.     

A comprehensive study of hot-carrier instability in p- and n-typepoly-Si gated MOSFET's

A comprehensive comparison of hot-carrier instability between p- and n-type poly Si-gated MOSFET's is presented in this paper. The electron trapping and interface state generation in the 7 nm gate oxide of MOSFET's are investigated using uniform hot-electron injection from a buried junction injector (BJI) and channel-hot-carrier stress. From BJI experiments, electron trapping (instead of oxide trap generation) and interface state generation are shown to be the major effects of hot-electron injection. Electron trapping and interface state generation are found to be similar in both p- and n-type poly-Si gated MOSFET's. The dependences of interface state generation by hot electrons on oxide voltages and temperatures are observed to be similar between n- and p-type poly-Si gated MOSFET's. From the results of channel-hot-carrier stress on surface-channel n- and p-channel MOSFET's, it was also found that the channel-hot-carrier instabilities of p- and n-type poly-Si gated MOSFET's are comparable     

Generation of interface states by hot hole injection in MOSFET's

The emission of hot electrons and hot holes from n-channel MOSFET's into the gate oxide is investigated as a function of the gate bias for a given lateral electric field. The resulting electron gate current as well as the substrate current are analyzed for both the saturation and the linear regime of the transistor. In the saturation regime, a remarkable increase of interface states occurs which can be correlated with the hole generation due to avalanche multiplication in the high-field region. In this case, the electric field normal to the Si-SiO2interface near the drain aids in the injection of hot holes along the channel which initiates acceptor-type interface states. In the linear operation regime, however, no pronounced generation of interface states can be detected.     

Novel hot-electron effects in the channel of MOSFET's observed by capacitance measurements

Capacitance-voltage measurements were performed on small-size MOSFET's with applied drain voltage to obtain information about hot-electron effects. The theoretical analysis shows that hot carriers cause remarkable changes 1) in the vertical and horizontal distribution of the electrons in the inversion layer, 2) in the surface potential drop, 3) in the depletion charge, and 4) in the effective threshold voltage. The influence of these hot-electron effects on the channel current is discussed.     

Thermal stability and secondary breakdown in planar power MOSFET's

The destructive secondary-breakdown mechanism of high-voltage n-channel power MOSFET's is discussed. A model is proposed in which the secondary breakdown is caused primarily by the negative-resistance effects of a parasitic bipolar transistor structure. The model suggests that destructive breakdown can be suppressed by a new no-surface-breakdown structure fabricated on a p^-on p⁺epitaxial wafer. Power MOSFET's having this structure have been realized and are completely free from secondary breakdowns, as suggested by the model. In addition, experimental evidence for excellent thermal stability of the power MOSFET is given by infrared scanner measurements of the temperature rise in the chip compared with bipolar transistors. An n-channel planar power MOSFET with a 400-W power limitation at 220-V breakdown voltage and a maximum current of 12 A has been successfully fabricated.     

Reliability of MOSFETs as affected by the interface traptransformation process

An investigation of the long-term time-dependent degradation of the subthreshold characteristics in n-channel and p-channel MOSFETs resulting from Fowler-Nordheim electron injection is discussed. Immediately after the hot-electron injection, degradation in both n- and p-channel transistors due to the hot-electron-induced interface traps is observed. When measured after the hot-electron injection was terminated, however, the subthreshold slope in n-channel transistors exhibits a gradual recovery toward its preinjection level, while that in p-channel transistors continues to degrade with time. This phenomenon can be explained by the interface trap transformation process, which is characterized by a gradual reduction of the hot-electron-induced interface traps above midgap and a gradual increase of the interface traps below midgap     

Low 1/f noise design of Hi-CMOS devices

Low-frequency noise characteristics of High-Performance CMOS(Hi-CMOS) devices were measured. It was found that the equivalent input noise power SVg,eqfor n-channel MOSFET's has a 1/fα spectrum (0.8 < α < 0.95) above 10 µA, even for sealed-down devices with channel lengths LGof 2 µm. The SVg,eqis clearly proportional to 1/Leffdown to 0.8 µm. The noise characteristics of p-channel and n-channel MOSFET's were compared. It was found that in Hi-CMOS devices, noise reduction in normally-off-type p-channel devices was obtained by light boron-ion implantations at doses below 10¹²cm^-2. The 1/f noise level of p-channel devices was reduced to 1/10- 1/20 that of n-channel devices. In n-channel devices, the low-frequency noise power is a slow increasing function of the drain current. In p-channel devices, on the other hand, a threshold current was observed at which the noise begins to increase rapidly. The results are discussed in this paper in relation to the theoretical model of 1/f noise. The device design for reducing 1/f noise in CMOS differential amplifiers is also examined.