采用交流电源供电的低功耗开关电容电路

提出一种新的低功耗开关电容电路设计方法.新的电路结构充分利用开关电容电路的工作特点,同时采用ACP交流电源对电路进行供电.当电路工作在采样相位阶段时,关闭OTA放大器电源以达到降低电路功耗的目的.电路仿真基于CSMC 5V 0.6μm CMOS工艺,与传统的采用DCP直流电源供电的开关电容电路相比,新的ACPSC低功耗开关电容电路可以取得降低40%电路功耗的效果.ACPSC电路技术经过流片测试,验证了电路功能的有效性.     

一种应用于开关电容电路的0.9 V自适应偏置OTA

设计了一种应用于开关电容电路的自适应偏置的低电压、低功耗开关运算跨导放大器。采用负阻负载技术和自适应偏置技术,分别提高了放大器的增益和转换速率;采用电流镜型OTA技术降低功耗,并通过控制开关关断非工作状态下的运放电源,进一步降低了功耗。新型开关电容共模反馈电路的共模电压可在一个时钟周期内快速稳定,不增加额外功耗,不限制输出摆幅。在SMIC 0.18 μm工艺下的仿真结果表明,OTA在0.9 V供电下,直流增益达60 dB,增益带宽积为1.81 MHz,转换速率为0.94 V/μs,功耗为4.16 μW。     

基于并联开关的低电压低功耗电流型CMOS电路设计

该文提出了一种电流型CMOS电路的并联开关结构,使得电流型CMOS电路能在较低的电源电压下工作,因而可以实现电路的低功耗设计,同时在相同的电源电压下,采用并联开关结构的电路比相应的串联开关电路具有更快的速度,PSPICE模拟证明了采用并联开关结构设计的电路能在较低的电源电压下工作,并具有较小的电路延时。     

超高速低功耗ECL予置分频器研究

本文介绍一个÷5/6低功耗ECL予置分频器的设计,从降低电源电压,减小内部逻辑摆幅和寄生电容等几方面讨论了提高电路高速低功耗特性的途径。该电路采用串联电源电压结构,内部电路在-2.5V～-2.7V电源电压下工作。电路功耗仅为具有相同功能的普通ECL电路的1/6。采用3μm设计规则的氧化物隔离等平面S型双极工艺。发射极条实际尺寸2μm×9μm,晶体管f_i为3.2GHz。室温下典型功耗75mW,最高M作频率大于900MHz。     

采用交流电源供电的低功耗开关电容电路

提出一种新的低功耗开关电容电路设计方法.新的电路结构充分利用开关电容电路的工作特点,同时采用ACP交流电源对电路进行供电.当电路工作在采样相位阶段时,关闭OTA放大器电源以达到降低电路功耗的目的.电路仿真基于CSMC 5V 0.6μm CMOS工艺,与传统的采用DCP直流电源供电的开关电容电路相比,新的ACPSC低功耗开关电容电路可以取得降低40%电路功耗的效果.ACPSC电路技术经过流片测试,验证了电路功能的有效性.     

基于锗硅工艺的40-Gb/s分接器

采用0.35μmSiGeBiCMOS工艺设计了一个1∶2分接器,核心电路单元采用经过改进的电路结构实现。由于传统的发射极耦合逻辑结构(ECL)电路的工作速度不能达到要求,对此加以了改进,在发射极耦合逻辑结构中增加一级射极跟随器,形成发射极-发射极耦合逻辑(E2CL)结构,从而提高电路的工作速度。测试结果显示,所设计分接器的工作速度可以达到40Gb/s。整个电路采用单电源5V供电,功耗为510mW。     

基于Switched-opamp的低功耗读出电路设计

利用开关运放技术对运放进行电源管理,实现了焦平面读出电路列运放的"休眠"-"唤醒"工作模式,使列运放仅在该列信号选通时工作.这种结构级功耗优化方法缩短了运放工作时间,降低了读出电路的功耗,适合低功耗系统应用要求.并设计了两种读出控制方案,对4×4元读出电路进行了瞬态分析.比照原有设计,该方法最多可以节省读出阶段列运放83%的功耗.     

一种MEMS开关驱动电路的设计

静电驱动MEMS开关可靠工作需要较高的驱动电压,大多数射频前端系统很难直接提供,因此需要一种实现电压转换和控制的专用芯片,以满足MEMS开关的实用化需要。本文基于200V SOI CMOS工艺设计的高升压倍数MEMS开关驱动电路,采用低击穿电压的Cockcroft-Walton电荷泵结构,结合特有的Trench工艺使电路的性能大大提高。仿真结果显示驱动电路在5V电源电压、0.2pF电容和1GΩ电阻并联负载下,输出电压达到82.7V,满足大多数MEMS开关对高驱动电压的需要。     

一种适用于开关电容电路的MOS开关栅增压电路

提出了一种新的MOS器件栅增压电路,它在减小MOS开关导通电阻的同时,减少了衬偏效应以及MOS开关输出信号的失真. 该电路采用了0.13μm 1.2V/2.5V CMOS工艺,HSPICE的仿真结果表明该栅增压电路适用于高速低电压开关电容电路.     

一种适用于开关电容电路的MOS开关栅增压电路

提出了一种新的MOS器件栅增压电路,它在减小MOS开关导通电阻的同时,减少了衬偏效应以及MOS开关输出信号的失真.该电路采用了O.13μm 1.2V/2.5V CMOS工艺,HSPICE的仿真结果表明该栅增压电路适用于高速低电压开关电容电路.     

A high-speed, low-power bipolar digital circuit for Gb/s LSI's:current mirror control logic

A novel low-power bipolar circuit for Gb/s LSIs, current mirror control logic (CMCL), is described. To reduce supply voltage and currents, the current sources of emitter-coupled-logic (ECL) series gate circuits are removed and the lower differential pairs are controlled by current mirror circuits. This enables circuits with the same function as two-stacked ECL circuits to operate at supply voltage of -2.0 V and reduces the current drawn through the driving circuits for the differential pairs to 50% of the conventional level shift circuits (emitter followers) in ECL. This CMCL circuit achieves 3.1-Gb/s (D-FF) and 4.3-GHz (T-FF) operation with a power supply voltage of -2.0 V and power dissipation of only 1.8 mW/(FF)     

用于通信ASIC的高速BiCMOS逻辑电路

提出了几种通信用BiCMOS逻辑门电路的实现方案。这些逻辑门均可在低电源电压(2.0~3.0 V)下,采用BiCMOS工艺和深亚微米技术精心设计及制作,并经过比较对其作出评价。分析和实验结果表明,所设计的电路不但具有确定的逻辑功能,而且具备高速、低耗、低电源电压和全摆幅的特性,因而完全适用于高速数字通信系统中。     

A realization of a high-frequency monolithic integrator with low power dissipation and its application to an active RC filter

According as the fine LSI process technique develops, the technique to reduce power dissipation of high-frequency integrated analog circuits is getting more important. This paper describes a design of high-frequency integrator with low power dissipation for monolithic leapfrog filters. In the design of the conventional monolithic integrators, there has been a great difficulty that a high-frequency integrator which can operate at low supply voltage cannot be realized without additional circuits, such as unbalanced-to-balanced conversion circuits and common-mode feedback circuits. The proposed integrator is based on the Miller integrator. By a PNP current mirror circuit, high CMRR is realized. However, the high-frequency characteristic of the integrator is independent of PNP transistors. In addition, it can operate at low supply voltage. The excess phase shift of the integrator is compensated by insertion of the compensation capacitance. The effectiveness of the proposed technique is confirmed by PSPICE simulation. The simulation results of the integrator shows that the common-mode gain is efficiently low and the virtual ground is realized, and that moderate phase compensation can be achieved. The simulation results of the 3rd-order leapfrog filter using the integrator shows that the 50 MHz-cutoff frequency filter is obtained. Its power dissipation in operating 2 V-supply voltage is 5.22 mW.     

Design and analysis of low power high-speed 1-bit full adder cells for VLSI applications

This paper presents a low power and high speed two hybrid 1-bit full adder cells employing both pass transistor and transmission gate logics. These designs aim to minimise power dissipation and reduce transistor count while at the same time reducing the propagation delay. The proposed full adder circuits utilise 16 and 14 transistors to achieve a compact circuit design. For 1.2 V supply voltage at 0.18-μm CMOS technology, the power consumption is 4.266 μW was found to be extremely low with lower propagation delay 214.65 ps and power-delay product (PDP) of 0.9156 fJ by the deliberate use of CMOS inverters and strong transmission gates. The results of the simulation illustrate the superiority of the newly designed 1-bit adder circuits against the reported conservative adder structures in terms of power, delay, power delay product (PDP) and a transistor count. The implementation of 8-bit ripple carry adder in view of proposed full adders are finally verified and was observed to be working efficiently with only 1.411 ns delay. The performance of the proposed circuits was examined using Mentor Graphics Schematic Composer at 1.2 V single ended supply voltage and the model parameters of a TSMC 0.18-μm CMOS.     

Low-voltage high-gain differential OTA for SC circuits

A new differential operational transconductance amplifier (OTA) for SC circuits that operates with a supply voltage of less than two transistor threshold voltages is presented. Its simplicity relies on the use of a low-voltage regulated cascode circuit, which achieves very high output impedance under low-voltage restrictions. The OTA has been designed to operate with a supply voltage of V/sub DD/=1.5 V, using a 0.6 /spl mu/m CMOS technology with transistor threshold voltages of V/sub TN/=0.75 V and V/sub TP/=-0.85 V. Post-layout simulation results for a load capacitance (C/sub L/) of 2 pF show a 75 MHz gain-bandwidth product and 100 dB DC gain with a quiescent power consumption of 750 /spl mu/W.     

A high speed GaAs error-detection circuit for fiber-optictransmission systems

A high-speed GaAs IC for detection of line code vibrations is described. This 144-gate error-detection circuit for monitoring a high-bit-rate fiber-optic link has been designed and fabricated using a high-yield titanium tungsten nitride self-aligned gate MESFET process. This process routinely provides a wafer-averaged gate delay (fan-in=fan-out=2) of less than 70 ps with a power dissipation of 0.5 mW/gate. The error-detection circuits were tested on-wafer using high-frequency probe cards at a clock rate of 1.4 GHz, with a yield of 64%. Packaged circuits worked at a clock frequency of over 2.5 GHz and consumed 200-mW power at a fixed power supply voltage of 1.5 V. The circuits operate over a wide variation in power supply voltage and temperature. When operated at a package temperature of 125°C, the circuits show less than a 12% degradation in their maximum clock frequency. The circuit was inserted into a 565-Mb/s system currently using a silicon ECL part, and full functionality was verified with no necessary modifications     

A 5-ns GaAs 16-kb SRAM

A GaAs 4 K×4-b static-Ram (SRAM) with high speed and high reliability has been developed for practical systems. By adopting a novel basic circuit technique to the peripheral circuits, the RAM operates over a wide temperature range. By using a novel memory cell, the soft-error rate is reduced to less than that of commercial silicon emitter-coupled-logic (ECL) RAMs. Furthermore, by adopting a triple-level interconnection process, the chip area is reduced to 58% of that using a double-level one. The RAM operates at a single supply voltage of 1.8 V. At an ambient temperature of between 25 and 100°C, the RAM is guaranteed a 5.0-ns access time, 2.0-W power dissipation, and ±0.1-V supply voltage tolerance     

Low supply voltage operation of over-40-Gb/s digital ICs based on parallel-current-switching latch circuitry

We implemented a low-voltage latch circuit topology in a full-rate 4:1 multiplexer (MUX) using InP-HBT technology. The proposed latch circuitry incorporates parallel current switching together with inductive peaking a combination that makes it suitable for over-40-Gb/s operation at supply voltages ranging from 1.5 to 1.8 V. The full-rate 4:1 MUX provided 40-Gb/s error-free operation with a power dissipation of only 1 W at a supply voltage of 1.8 V. The D-flip/flop (D-F/F) based on this latch circuitry provided 50-Gb/s D-F/F operation at a supply voltage as low as 1.5 V. Demultiplexing operation was also confirmed for the D-F/F with this circuit technology at a data rate of up to 110Gb/s with a 1.8-V supply voltage. The latch circuitry should help enable development of a low-voltage 40-Gb/s full-rate module which can be seamlessly connected with high-speed CMOS I/O circuits.     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

BiCMOS nonthreshold logic for high-speed low-power applications

New high-speed low-power BiCMOS nonthreshold logic (BNTL) circuits are presented. These circuits offers a built-in CMOS and bipolar level conversion and are suitable for reduced power supply voltage. A 4-b carry lookahead generator (CLG) circuit is designed in BNTL, ECL, and CMOS using 0.8-μm BiCMOS technology. Circuit simulations show that this new logic provides speed comparable to or better than that provided by emitter-coupled logic (ECL) for lower power dissipation