Determination of Si/SiO2 interface roughness using weaklocalization

The interface roughness of intentionally textured Si/SiO₂ interfaces was measured using the quantum weak localization (WL) correction to the electrical conductivity at low temperatures. The deduced roughness was confirmed by observation of the Si surface replicas by atomic force microscopy (AFM). Quantitative agreement between the two methods was found (Δ=1.2 to 1.4 Å from WL and 1.35 Å from AFM). For a surface with artificially induced texture, it is found that WL can easily distinguish a significant increase in roughness relative to the smooth surfaces. AFM confirms this qualitative conclusion     

具有SiO2/SiNX/SiO2 复合绝缘层的有机薄膜晶体管

We have investigated a SiO_2/SiN_x/SiO_2 composite insulation layer structured gate dielectric for an organic thin film transistor(OTFT) with the purpose of improving the performance of the SiO_2 gate insulator. The SiO_2/SiN_x/SiO_2 composite insulation layer was prepared by magnetron sputtering.Compared with the same thickness of a SiO_2 insulation layer device,the SiO_2/SiN_x/SiO_2 composite insulation layer is an effective method of fabricating OTFT with improved electric characteristics and decrease...     

Influence of the SiO2 layer thickness on the degradation of HfO2/SiO2 stacks subjected to static and dynamic stress conditions

The substitution of the SiO₂ gate oxide in MOS devices by a material with a high-k dielectric constant is being deeply studied nowadays to solve the problem of the leakage currents that appear with the progressive scaling of SiO₂ thickness. To improve the quality of the high-k/Si interface a very thin SiO₂ film is grown between both materials. In this work, HfO₂/SiO₂ stacks with different SiO₂ thickness were subjected to different types of stress (static and dynamic) to analyze the effect of this interfacial layer of SiO₂ in the degradation of the stack. The results show that the dielectric degradation depends on the stress applied and that the thickness of the SiO₂ interfacial layer influences the advanced stages of the stack degradation.     

Effect of SiO2/Si interface roughness on gate current

In many theoretical investigations of the electric-tunnel effect through an ultrathin oxide in metal-oxide-semiconductor (MOS) structure, it is commonly assumed that the oxide is of uniform thickness. One example of nonuniformity in oxides is interface roughness. Interface roughness effects on direct tunneling current in ultrathin MOS structures are investigated theoretically in this article. The roughness at SiO₂/Si interface is described in terms of Gauss distribution. It is shown that the transmission coefficient increases with root-mean-square (rms) roughness increasing, and the effect of rms roughness on the direct tunneling current decreases with the applied voltage increasing and increases with rms roughness increasing.     

Characterising the surface roughness of AFM grown SiO2 on Si

The reliability of AFM grown SiO₂ as a gate oxide needs to be examined if nanodevices fabricated from the oxide are to be integrated into standard microelectronic technology. In this article we present our preliminary results on AFM fabrication and topographical characterisation of large area oxide, electrical characterisation is to follow. Roughness is the central issue of this work due to its importance in relation to the quality of ultra thin dielectrics.     

TiO_2/SiO_2、ZrO_2/SiO_2多层介质膜光学损耗及激光损伤研究

以TiO_2/SiO_2及ZrO_2/SiO_2多层介质膜为例,测试了不同工艺条件及不同膜系结构下薄膜样品的光学损耗及激光损伤阈值,同时对实验结果作了初步的分析讨论.     

在SiO2中掺A1对Au／纳米（SiO2／Si／SiO2）／p—Si结构电致发光的影响

利用射频磁控溅射方法,制成纳米SiO2层厚度一定而纳米Si层厚度不同的纳米（SiO2/Si/SiO2）/p-Si结构和纳米（SiO2:A1/Si/SiO2:A1)/p-Si结构,用磁控溅射制备纳米SiO2:A1时所用的SiO2/A1复合靶中的A1的面积百分比为1%。上述两种结构中Si层厚度均为1-3nm,间隔为0.2nm。为了对比研究,还制备了Si层厚度为零的样品。这两种结构在900℃氮气下退火30min,正面蒸半透明Au膜,背面蒸A1作欧姆接触后,都在正向偏置下观察到电致发光（EL）。在一定的正向偏置下,EL强度和峰位以及电流都随Si层厚度的增加而同步振荡,位相相同。但掺A1结构的发光强度普遍比不掺A1结构强。另外,这两种结构的EL具体振荡特性有明显不同,对这两种结构的电致发光的物理机制和SiO2中掺A1的作用进行了分析和讨论。     

Novel hydrogen annealing for forming SiO2 film by rapidthermal processing

Hydrogen annealing at 700-1100°C for 0-300 s has been combined with SiO₂ formation by rapid thermal processing (RTP). The SiO₂ films formed with the above processes were evaluated by C-V and I-V measurements and by time-dependent dielectric breakdown (TDDB) tests. These films provide longer time to breakdown andless positive charge generation than SiO₂ films formed without H₂ annealing. In particular, the SiO₂ formation-H₂ annealing SiO ₂ formation process is quite effective in improving the dielectric strength of the thin RTP-SiO₂ film     

脉冲激光对石英基底Ta2O5/SiO2滤光膜的损伤效应研究

随着高能激光系统的发展,对光学薄膜抵抗激光损伤能力的要求越来越高,而激光脉宽是脉冲激光对薄膜损伤行为的重要影响因素。针对Ta₂O₅/SiO₂多层膜,基于1-on-1测试方法,分析其在飞秒、皮秒、纳秒激光作用下的损伤特性。测得800 nm飞秒激光作用下的损伤阈值为1.67 J/cm₂;532 nm和1 064 nm皮秒激光作用下的损伤阈值分别为1.08 J/cm²和1.98 J/cm²;532 nm和1 064 nm纳秒激光作用下的损伤阈值分别为9.39 J/cm₂和21.57 J/cm₂,并使用金相显微镜观察了滤光膜的损伤形貌。实验结果表明：飞秒激光对滤光膜的损伤机理主要是多光子电离效应,而皮秒和纳秒激光对滤光膜的损伤机制主要是热效应。滤光膜在飞秒激光作用下的损伤阈值与皮秒激光作用下的损伤阈值相当,纳秒激光作用下的损伤阈值要高一个数量级,透射通带外损伤阈值约为通带内损伤阈值的2倍。     

非晶态SiO2过渡层对生长C轴取向LiNbO3薄膜的影响

采用磁控溅射方法,在Si衬底和LiNbO3薄膜之间引入SiO2过渡层制备LiNbO3薄膜。采用X射线衍射（XRD〉、傅里叶变换红外吸收光谱（FT-IR）和扫描电子显微镜（SEM）对LiNbO3薄膜的结晶取向、组成成分和表面形貌进行了表征,重点研究了非晶态SiO2过渡层对LiNbO3薄膜C轴取向的影响。结果表明,非晶态S...     

Hot-carrier injections in SiO2

We review the hot-carrier injection phenomena in gate-oxide and the related degradation in silicon MOSFETs. We discuss the basic degradation mechanisms and the nature of the created defects by carrier injections through the gate-oxide. Emphasis is put on the discussion of dynamic hot-carrier injections in MOSFETs and on the stress induced leakage currents in very thin (< 5 nm) gate-oxide.     

Transport and electroluminescence mechanism in Au/（Si/ SiO2）/P-Si film

Following the development of information technolo-gy,it has been a tendency to take the place of electronby photon as a carrier of information,since photons canmove thousands ti mes faster than electrons ,which cani mprove the rate of communication.Silico…     

SiOF and SiO2 deposition in a HDP reactor: tool characterization and film analysis

A high density plasma chemical vapour deposition (HDP CVD) system based on electron cyclotron resonance (ECR) plasma excitation for deposition of inter metal dielectric (IMD) is presented. With the system deposition of SiO₂ and SiOF has been performed. The influence of pressure, Ar content in the flow, total flow, bias voltage, microwave power on gap fill capability and growth rate has been investigated. A figure of merit, the product of gap filling capability and growth rate is defined. In addition measurements of the uniformity of the composition over the wafer of the deposited SiO₂ and SiOF layers were performed. The dielectric constant of the layers was measured on SiOF films with different composition. The stability of these SiOF films was also analysed. This was done by treating the films with moisture and measuring composition before and after this treatment.     

SiO2/CeO2混合磨料对硅CMP效果影响

以获得高去除速率和低表面粗糙度为目标,建立了基于纳米氧化铈-硅溶胶复配混合磨料新模式。采用小粒径、低分散度的30 nm氧化铈-硅溶胶复配混合作为磨料,利用氧化铈对硅片表面化学反应产物硅酸胺盐的强络合作用,加快了硅衬底表面化学反应进程。分析了复合磨料抛光的机理,通过Aglient 5600LS原子力显微镜,测试了抛光前后的厚度及抛光后的硅片表面微粗糙度。实验结果表明,复合磨料抛光后硅片表面在10μm×10μm范围内粗糙度方均根值0.361 nm,表面微粗糙度降低16%以上,去除率为1 680 nm/min,硅CMP速率提高8%以上,实现了高去除速率、低表面粗糙度的硅单晶抛光。     

SOI planar photonic crystal fabrication: Etching through SiO2/Si/SiO2 layer systems using fluorocarbon plasmas

Dry plasma etching of sub-micron structures in a SiO₂/Si/SiO₂ layer system using Cr as a mask was performed in a fluorocarbon plasma. It was determined that the best anisotropy could be achieved in the most electropositive plasma. A gas composition yielding the desired SOI planar photonic crystal structures was optimized from the available process gases, Ar, He, O₂, SF₆, CF₄, c-C₄F₈, CHF₃, using DC bias data sets. Application of the c-C₄F₈/(noble gas) chemistry allowed fabrication of the desired SOI planar photonic crystal. The average etching rates for the pores and ridge waveguide regions were about 71 and 97 nm/min, respectively, while the average SiO₂/Si/SiO₂ to Cr etching selectivity for the ridge waveguide region was about 33:1 in case of the c-C₄F₈/90%Ar plasma with optimized parameters.     

Effect of H2O evolving from TEOS based SiO2 film on the EEPROM cell characteristic

In this paper, we investigate the effect of water (H₂O) molecules evolving from silicon dioxide (SiO₂) film deposited by low pressure chemical vapor deposition (LPCVD) at 670 °C on the transistor characteristic of an electrically erasable programmable read only memory (EEPROM) cell. Fourier Transform Infra red (FT-IR) analysis reveals that H₂O is captured during film deposition and diffused to silicon surface during high thermal processing. The diffused H₂O molecules lower threshold voltage (V_t) of cell transistor and, thus, leakage current of the cell transistor is increased. In erased cell, V_t lowering is 0.25 V in which it increases leakage current of cell transistor from 1 to 100 pA. This results in the lowering of high voltage margin of a 512 Kb EEPROM from 2.8 to 2.6 V at 85 °C.     

Comparison of electrical stress-induced charge carrier generation/trapping and related degradation of SiO2 and HfO2/SiO2 gate dielectric stacks

We compare charge carrier generation/trapping related degradation in control oxide (SiO₂) and HfO₂/SiO₂ stack of an identical equivalent-oxide-thickness (EOT) during constant gate voltage stress of n-type metal-oxide-semiconductor (nMOS) capacitors. Irrespective of these two dielectrics, the kinetics of generation of both surface states and oxide-trapped positive charges are found to be similar. Our analysis shows that the positive oxide charge buildup during CVS is due to trapping of protons by the strained SiOSi bonds in either of the devices. We demonstrate that compared to SiO₂ devices, HfO₂ devices with an equal EOT better perform in CMOS logic applications. On the other hand, our results indicate that the control oxide is better in charge trapping memory devices. Furthermore, the lifetime of the control oxide devices is observed longer than that of HfO₂ devices at a given operating voltage.     

Distribution of trapped charges in SiO2 film of ap+-gate PMOS structure

To investigate the highly boron-doped SiO₂ film, p⁺ polysilicon-gate PMOSFETs and capacitors were fabricated using the same process as is used for surface-channel-type n⁺-gate devices, except for the gate-type doping. After the application of negatively biased Fowler-Nordheim (FN) stress, it was found that positive charges accumulate near the silicon/SiO₂ interface and electrons accumulate near the polysilicon/SiO₂ interface in p⁺-gate capacitors. DC hot carrier stress was applied to both PMOSFET gate types. The p⁺ gate's stress time dependence of I_sub is smaller than that of the n⁺ gate, and the electric field near the drain in the p⁺ -gate PMOSFET was found to be more severe than that of the n⁺ -gate device. The subthreshold slope of the p⁺-gated PMOSFET was improved and then degraded during the hot carrier stressing, while that of the n⁺-gated device did not significantly change. The actual change of V_th was larger than the value derived from Δ_gm using the channel-shortening concept. The idea of widely spreading and partially compensated electron distribution along with source-drain direction in the SiO₂ film, which assumes the existence of trapped holes in the p⁺-gate PMOSFET, is proposed to explain these phenomena     

Ultra-thin Ta2O5dielectric film for high-speed bipolar memories

A new capacitor technology, with extremely thin (5.3-20 nm) Ta2O5film deposition and weak-spot oxidation, is developed to realize high capacitance and high reliability. The Ta2O5film was reactively sputtered, followed by weak-spot oxidation. The weak-spot oxidation is achieved by placing the Ta2O5film on Si in a high-temperature dry O2ambient. The oxidation significantly improves the time-dependent-dielectric-breakdown (TDDB) characteristics and reduces the defect density of Ta2O5capacitors without reducing the capacitance by selectively oxidizing the Si surface at weak spots where the Ta2O5is locally thin or missing. The technology is based on the new discovery that Ta2O5film less than 20 nm thick shows no reduction in dielectric breakdown strength after dry O2high-temperature annealing up to 1000° C. The Ta2O5(7.5-nm) capacitor with a capacitance of 8.5 fF/µm²is applied to a high-speed bipolar memory. This makes it possible to reduce the memory cell area to one-third that of a conventional bipolar memory. The memory provides high-speed operation; access time is less than 5 ns, and sufficient soft error immunity is provided.