Reliability of assembly of chips and flex substrates using thermosonic flip-chip bonding process with a non-conductive paste

This study investigates the reliability of the assembly of chips and flex substrates using the thermosonic flip-chip bonding process with non-conductive paste (NCP). The high-temperature storage (HTS) test, the temperature cycling test (TCT), the pressure cooker test (PCT) and the high-temperature/high-humidity (HT/HH) test were conducted to examine the reliability of chips that are bonded on flex substrates. The environmental parameters used in the various reliability tests were consistent with the JEDEC standards. After the reliability tests, a peeling test was performed and the microstructure of the tested specimen observed to evaluate further the reliability.The bonding strength increased with the storage period in the HTS test. After the peeling test, a layer of copper electrodes was observed to be stuck on gold bumps over the fractured morphology of the chips when the chips and flex substrates were assembled using an ultrasonic power of 14.46 W, indicating that the bonding strength between the gold bumps and the copper electrodes was even higher than the adhesive strength of the layers that were deposited on the flex substrates. The HTS test yielded sufficient thermal energy to promote atomic interdiffusion between gold bumps and copper electrodes. Metallurgical bonding between the gold bump and the copper electrode occurred, improving the bonding strength. In the assembly of chips and flex substrates without the application of ultrasonic power in bonding process, the adhesive strength of NCP was highly reliable after HTS test, because the bonding strength was maintained after HTS test for various storage periods. The typical failure mode of PCT was interfacial delamination between NCP and flex substrates. Approximately 80% of the specimens exhibited full separation after PCT at 336 h when chips and flex substrates were assembled without applied ultrasonic power to the bonding process, revealing that the NCP cannot withstand the PCT and lost its adhesive strength. Applying an adequate ultrasonic power of 14.46 W in the bonding process not only improved the bonding strength, but also enabled the bonding strength to be maintained at high level after PCT. The high bonding strength was attributable to the strong bonding of the gold bumps on the copper electrodes after PCT for various storage periods. This experimental result demonstrates that ultrasonic power can increase the reliability of PCT on chips and flex substrates that were assembled with the NCP. The bonding strength of the gold bumps on the flex substrates did not change significantly after the TCT, revealing the great reliability of TCT on chips and flex substrates that were assembled using the thermosonic flip-chip bonding process with the NCP. The bonding strength of chips bonded to flex substrates increased with the storage periods of the HT/HH test if ultrasonic power was applied to bonding process. Neither delamination nor any defect at the bonding interface was observed. The reliability of the HT/HH test for chips bonded on flex substrates using the thermosonic flip-chip process with the NCP fulfills the requirements stated in the JEDEC standards.According to the experimental findings of various reliability tests, the chips that were bonded to flex substrates using the thermosonic bonding process with NCP met the JEDEC specifications; with the exception of the adhesive strength of NCP under PCT which must be improved.     

Enhancement of the Bondability and Die-Shear Force of Chip–Flex Substrate Assemblies by Depositing a Nickel Layer on the Flex Substrate

A nickel layer and a silver bonding layer have been deposited on copper electrodes over flex substrates to improve the bondability and die-shear force performance of chip?Cflex substrate assemblies when using the thermosonic flip-chip bonding process. For bonding temperature of 200°C, the maximum die-shear force was achieved by combining parameter values of 20.66?W ultrasonic power, 625?gf bonding force, and 0.5?s bonding time. The improved bondability and die-shear force could be attributed to better transfer of ultrasonic power across the bonding interface during thermosonic flip-chip bonding, owing to the high rigidity of the copper electrodes provided by the nickel layer. Experimental results also indicated that high bonding load is necessary at elevated ultrasonic power range to provide firm contact between the bumps and electrodes to enable smooth ultrasonic power transfer across the bonding interface. Moreover, prolonged bonding time caused cracks between the bumps and flex substrate. Close examination of the fracture morphologies after die-shear testing and after ultrasonic separation provided insight into the die-shear force performance as influenced by the process parameters and by the deposition of the nickel layer on the copper electrodes over the flex substrate.     

Gold Stud Bumps Flip-Chip Bonded onto Copper Electrodes with Titanium and Silver Layers

The purpose of this study was to develop the thermosonic flip-chip bonding process for gold stud bumps bonded onto copper electrodes on an alumina substrate. Copper electrodes were deposited with silver as the bonding layer and with titanium as the diffusion barrier layer. Deposition of these layers on copper electrodes improves the bonding quality between the gold stud bumps and copper electrodes. With appropriate bonding parameters, 100% bondability was achieved. Bonding strength between the gold stud bumps and copper electrodes was much higher than the value converted from the standards of the Joint Electron Device Engineering Council (JEDEC). The effects of process parameters, including bonding force, ultrasonic power, and bonding time, on bonding strength were also investigated. Experimental results indicate that bonding strength increased as bonding force and ultrasonic power increased and did not deteriorate after prolonged storage at elevated temperatures. Thus, the reliability of the high-temperature storage (HTS) test for gold stud bumps flip-chip bonded onto a silver bonding layer and titanium diffusion barrier layer is not a concern. Deposition of these two layers on copper electrodes is an effective and direct method for thermosonic flip-chip bonding of gold stud bumps to a substrate, and ensures excellent bond quality. Applications such as flip-chip bonding of chips with low pin counts or light-emitting diode (LED) packaging are appropriate.     

Thermosonic bonding of gold wire onto silver bonding layer on the bond pads of chips with copper interconnects

A copper pad oxidizes easily at elevated temperatures during thermosonic wire bonding for chips with copper interconnects. The bondability and bonding strength of a gold wire onto a bare copper pad are seriously degraded by the formation of a copper oxide film. A new bonding approach is proposed to overcome this intrinsic drawback of the copper pad. A silver layer is deposited as a bonding layer on the surface of copper pads. Both the ball-shear force and the wire-pull force of a gold wire bonded onto copper pads with silver bonding layers far exceed the minimum values stated in the JEDEC standard and MIL specifications. The silver bonding layer improves bonding between the gold ball and copper pads. The reliability of gold ball bonds on a bond pad is verified in a high-temperature storage (HTS) test. The bonding strength increases with the storage time and far exceeds that required by the relevant industrial codes. The superior bondability and high strength after the HTS test were interpreted with reference to the results of electron probe x-ray microanalyzer (EPMA) analysis. This use of a silver bonding layer may make the fabrication of copper chips simpler than by other protective schemes.     

Increasing the bonding strength of chips on flex substrates using thermosonic flip-chip bonding process with nonconductive paste

Thermosonic flip-chip bonding process with a nonconductive paste (NCP) was employed to improve the processability and bonding strength of the flip-chip onto flex substrates (FCOF). A non-conductive paste was deposited on the surface of the copper electrodes over the flex substrate, and a chip with eight gold bumps bonded onto the copper electrodes by the thermosonic flip-chip bonding process.For the chips and flex substrates assembly, ultrasonic power is important in the removal of some of the non-conductive paste on the surface of copper electrodes during thermosonic bonding. Accordingly, gold stud bumps in this study were directly bonded onto copper electrodes to form successful electrical paths between chips and the flex substrate. A particular ultrasonic power resulted in some metallurgical bonding between the gold bumps and the copper electrodes, increasing the bonding strength. The ultrasonic power was not only to remove the NCP from the copper electrodes, but also formed metallurgical bonds during the thermosonic flip-chip bonding process with NCP.In this study, the parameters of the bonding of chips onto flex substrates using thermosonic flip-chip bonding process with NCP were a bonding force of 4.9 N, a curing time of 40 s, a curing temperature of 140 °C and an ultrasonic power of 14.46 W. The processability and bonding strength of flip-chips on flex substrates using thermosonic bonding process with NCP was verified in this study. This process has great potential to be applied to the packaging of consumed electronic products.     

Increasing bondability and bonding strength of gold stud bumps onto copper pads with a deposited titanium barrier layer

A flip-chip assembly is an attractive scheme for use in high performance and miniaturized microelectronics packaging. Wafer bumping is essential before chips can be flip-bonded to a substrate. Wafer bumping can be used for mechanical-single point stud bump bonding (SBB), and is based on conventional thermosonic wire bonding. This work proposes depositing a titanium barrier layer between the copper film and the silver bonding layer to achieve perfect bondability and sufficiently strong thermosonic bonding between a stud bump and the copper pad.A titanium layer was deposited on the copper pads to prevent copper atoms from out-diffusing during thermosonic stud bump bonding. A silver film was then deposited on the surface of the titanium film as a bonding layer to increase the bondability and bonding strength for stud bumps onto copper pads. The integration of the silver bonding layer with a diffusion barrier layer of titanium on the copper pads yielded 100% bondability between the stud bump and pads. The strength of bonding between the gold bumps on the copper pads significantly exceeds the minimum average values in JEDEC specifications. The diffusion barrier layer of titanium effectively prevents copper atoms from out-diffusing to the silver bonding layer surface during thermosonic bonding, which fact can be interpreted with reference to the experimental results of energy dispersive spectrometry (EDS) and analyses of Auger depth profiles. This diffusion barrier layer of titanium efficiently provides perfect bondability and sufficiently strong bonding between a stud bump and copper pads with a silver bonding layer.     

Processability and reliability of nonconductive adhesives (NCAs) in fine-pitch chip-on-flex applications

The use of NCAs to form direct contact interconnections between chip bumps and substrate pads have become a viable option in interconnection technology for fine-pitch applications. However, the primary concerns with NCAs are their long-term reliability, stability, and consistent electrical performance in particulate interconnections. Results of assembly process studies and environmental testing using NCAs on flexible substrates are analyzed and discussed herein. An extensive design experiment was performed to determine which process parameters were critical in obtaining good electrical connections. A reliability evaluation of NCAs for flexible substrate applications was carried out to gain more insight into the failure mechanisms of this type of interconnect. Pressure cooker test results showed that failures occurring in NCA joints are primarily due to moisture absorption, which could lead to interfacial delamination at the substrate/adhesive interface, accompanied by hygroscopic swelling. NCAs with lower coefficients of thermal expansion also exhibited better contact resistance stability during high-temperature storage tests.     

Effect of Gold Stud Bump Topology on Reliability of Flip Chip on Flex Interconnects

The flip chip technique using conductive adhesives have emerged as a good alternative to solder flip chip methods. Different approaches of the interconnection mechanism using conductive adhesives have been developed. In this paper, test chips with gold stud bumps are flip-chipped with conductive adhesives onto a flexible substrate. An experimental study to characterize the bonding process parameters is reported. Initial results from the environmental studies show that thermal shock test causes negligible failure. On the other hand, high humidity test causes considerable failure in flip chip on flex assemblies. Improvements in the reliability of the assembly are achieved by modifying the shape of the gold stud bumps.     

Carbon nanotubes for nanoscale low temperature flip chip connections

In this work we demonstrate a new approach for ultra fine flip chip interconnections based on carbon nanotubes as a wiring material. In contrast to other works we show patterned growth of multi walled CNTs on substrates with pre-structured bond pads including a complete metallization system for electrical characterization. Furthermore, we succeeded achieving a reliable flip chip connection between CNT-covered contact pads and metal pads at temperatures lower than 200 °C. Our goal is a reversible electrical and mechanical chip assembly with CNT bumps.For bonding experiments and electrical characterization a test structure with a damascene metallization including a layer stack of TiN/Cu/TiN was prepared. For CNT growth a thin nickel catalyst layer was selectively deposited with sputtering and a lift-off technique on the contact pads. The CNTs were grown by thermal CVD with ethylene as carbon source. CNT growth parameters like catalyst thickness, gas composition, growth time and temperature were optimized to get dense CNT growth. The metal bumps of the counter chip consist of electroless deposited Ni. With the selected layout we can obtain daisy chain and four-point measurements for lossless determination of single contact resistance. We have obtained reliable electrical contacts with relatively small resistance reaching values as low as 2.2 Ω. As CNT-quality is strongly dependent on the growth temperature we observed a strong change in resistivity of the flip chip connection as the growth temperature was varied. Reliability tests showed long time stability under thermal stress proving a reliable electrical contact between the contact pads. There is an appropriate potential for further optimization of the CNT bump resistance and applying this technology for IC-devices.     

倒装芯片热电极键合工艺研究

文章将论述一种无掩模制造细小焊料凸点技术。利用热电极键合工艺将带有凸点的倒装芯片焊到基板上。此项工艺能将间距小至40μm的倒装芯片组装到基板上。文章也论述了间距为40μm、电镀AuSn钎料凸点的倒装芯片组装工艺技术。金属间化合物相的形成对焊点可靠性有重要影响,尤其是对于细小焊点。文中研究了金属间化合物相的形成与增加对可靠性的影响。讨论分析了热循环和湿气等可靠性试验结果。     

A Novel Three-Dimensional Packaging Method for Al-Metalized SiC Power Devices

A novel three-dimensional packaging method for Al-metalized SiC power devices has been developed by means of Au stud bumping technology and a subsequent vacuum reflow soldering process with Au-20Sn solder paste. Al-metalized electrodes of a SiC power chip can be robustly assembled to a direct bonded copper (DBC) substrate with this method. The bump shear strength of a Au stud bump on an Al electrode of a SiC chip increased with bonding temperature. The die shear strength of a SiC chip on the DBC substrate increased with the number of Au stud bumps which were preformed on the Al electrode. The bonded SiC-SBD chips on a DBC substrate were aged at 250 ${^circ}{rm C}$ in a vacuum furnace and the morphologies, die shear strength and electrical properties were investigated after a certain aging time. After 1000 h aging at 250 ${^circ}{rm C}$, the electrical resistance of the bonded SiC-SBD chips only increased about 0.4%, the residual die shear strength was much higher than that of the IEC749 (or JEITA) standard value, and little morphological change was observed by a micro-focus X-ray TV system. Very little diffusion between Au stud bumps and Au-20Sn solder was observed by scanning electron microscope (SEM) equipped with an energy dispersed X-ray analyzer (EDX). Intermetallic compounds (IMC) evolved at the interface of chip/solder and chip/Au stud bumps after 1000 h aging at 250 ${^circ}{rm C}$. With this method, power devices with Al bond pads can be three-dimensionally packaged.      

Investigation of flip chip under bump metallization systems of Cupads

In this study, UBM material systems for flip chip solder bumps on Cu pads were investigated using the electroless copper (E-Cu) and electroless nickel (E-Ni) plating methods; and the effects of the interfacial reaction between UBMs and Sn-36Pb-2Ag solders on the solder bump joint reliability were also investigated to optimize UBM materials for flip chip on Cu pads. For the E-Cu UBM, scallop-like Cu₆Sn₅, intermetallic compound (IMC) forms at the solder/E-Cu interface, and bump fracture occurred along this interface under a relatively small load. In contrast, at the E-Ni/E-Cu UBM, E-Ni serves as a good diffusion-barrier layer. The E-Ni effectively limited the growth of the IMC at the interface, and the polygonal-shape Ni₃ Sn₄ IMC resulted in a relatively higher adhesion strength compared with the E-Cu UBM. As a result, electroless deposited UBM systems were successfully demonstrated as low cost UBM alternatives on Cu pads. It was found that the E-Ni/E-Cu UBM material system was a better choice for solder flip chip interconnection on Cu pads than the E-Cu UBM     

Effect of bump height on the strain variation during the thermalcycling test of ACA flip-chip joints

Flip chip joining using anisotropically conductive adhesive (ACA) has become a very attractive technique for electronics packaging. Many factors can influence the reliability of the ACA flip-chip joint. Bump height, is one of these factors. In this work, the strain development during the thermal cycling test of flip-chip joining with different bump heights was studied. The effect of bump height is significant in the interface between the bumps and the pads. Bigger volume area of high strain is found for higher bump in the interface between the bumps and the pads. Our calculations show that there is practically no effect of the bump height on the strain variation in the bumps and in the pads     

Increasing bondability and ball-shear force of gold balls thermosonic bonding to flex substrates by depositing a nickel layer

To improve the bondability and ball-shear force of gold balls that are thermosonically bonded to copper electrodes over flex substrates, a nickel layer was deposited on the surface of the copper electrodes to increase their rigidity. A silver layer was then deposited on the nickel layer to prevent oxidation of the copper electrodes during the thermosonic bonding process. This nickel layer was expected to enhance the rigidity of copper electrodes over the flex substrates, increasing the thermosonic bonding efficiency of gold balls to copper electrodes over the flex substrates.Deposition the nickel layer on the copper electrodes improved the elastic modulus of the flex substrates, indicating that the nickel layer is effective in enhancing the rigidity of copper electrodes over the flex substrates. The bondability and ball-shear force of gold balls that are thermosonically bonded to copper electrodes increases with the thickness of the nickel layer given fixed bonding parameters. One hundred percent bondability and high ball-shear force can be achieved when gold balls are thermosonically bonded to copper electrodes with the deposition of a 0.5 μm-thick nickel layer. Herein, the ball-shear force was higher than that specified in JEDEC standards. Furthermore, gold balls that were thermosonically bonded to copper electrodes with a nickel layer had a large bonded area with an extensive scrape, while gold balls that were thermosonically bonded to copper electrodes without a nickel layer had a blank surface morphology. This experimental result was similar to that of tests of the elastic modulus of flex substrates, similarity can be used to explain that the effectiveness of the nickel layer in increasing the rigidity of copper electrodes, increasing the bonding efficiency at the bonding interface between gold balls and copper electrodes during thermosonic bonding process. After ball-shear test, a layer that was stuck on the ball bond was observed at the location of fracture of the ball bonds for gold balls they were thermosonically boned on copper electrodes with 0.5 μm-thick nickel layer. This observation implies that the ball-shear force of the gold balls that were bonded on the copper electrodes exceeded even the adhesive force of the layers that were deposited on the copper electrodes.The deposition of a 0.5 μm-thick nickel layer on copper electrodes over flex substrates improved the rigidity of the copper electrodes; the ultrasonic power could be propagated to the bonding interface between the gold balls and the copper electrodes, increasing the bondability and ball-shear force.     

Flip chip on board: assessment of reliability in cellular phone application

Flip chips are generally seen as a potential future "packaging" option providing an alternative to chip scale packages. In this work, the reliability of flip chip assemblies was analyzed using daisy chain test components on a schematic test vehicle designed to emulate a cellular phone environment printed wiring board (PWB). The flip chip components were assembled in a standard surface mount technology process, where the flip chip bumps were first dipped in a flux film. A test matrix consisting of a number of flip chip test components with different input/output configurations, PWBs, fluxes, and underfills was built up. The assemblies were tested for potential damage to the flip chips and their interconnects by thermal cycling and by mechanical shock in a drop. After testing, the root causes of the failures were analyzed. As a separate task, the stress/strain generation that occurs in the flip chips in the drop test was analyzed using simulation, in order to find the critical locations on the test PWB.     

Long time reliability study of soldered flip chips on flexible substrates

Due to the requirements of new light, mobile, small and multifunctional electronic products the density of electronic packages continues to increase. Especially in medical electronics like pace makers the minimisation of the whole product size is an important factor. So flip chip technology becomes more and more attractive to reduce the height of an electronic package. At the same time the use of flexible and foldable substrates offers the possibility to create complex electronic devices with a very high density. In terms of human health the reliability of electronic products in medical applications has top priority.In this work flip chip interconnections to a flexible substrate are studied with regard to long time reliability. Test chips and substrates have been designed to give the possibility for electrical measurements. Solder was applied using conventional stencil printing method. The flip chip contacts on flexible substrates were created in a reflow process and underfilled subsequently.The assemblies have been tested according to JEDEC level 3. The focus in this paper is the long time reliability up to 10,000 h in thermal ageing at 125 °C and temperature/humidity testing at 85 °C/85% relative humidity as well as thermal cycling (0 °C/+100 °C) up to 5000 cycles. Daisy chain and four point Kelvin resistances have been measured to characterise the interconnections and monitor degradation effects.The failures have been analysed in terms of metallurgical investigations of formation and growing of intermetallic phases between underbump metallisation, solder bumps and conductor lines. CSAM was used to detect delaminations at the interfaces underfiller/chip and underfiller/substrate respectively.     

Anisotropic conductive film flip chip joining using thin chips

In this study, flip chip interconnections were made on very flexible polyethylene naphthalate substrates using anisotropic conductive film. Two kinds of chips were used: chips of normal thickness and thin chips. The thin chips were very thin, only 50 μm thick. Due to the thinness of the chips they were flexible and the entire joint was bendable. The reliability properties of the interconnections established with these two different kinds of chips were compared. In addition, the effect of bending of the chip and joint area on the joint reliability was studied. Furthermore, part of the substrates was dried before bonding and the effect of that on the joint performance was investigated.The pitch of the test vehicles was 250 μm and the chips had 25 μm high gold bumps. For resistance analysis there were two four-point measuring positions in each test vehicle. For finding the optimal bonding conditions for the test vehicles, the bonding was done using two different bonding pressures, of which the better one was chosen for the final tests.Furthermore, the test vehicles were subjected to thermal cycling tests between −40 and +125 °C (half-an-hour cycle) and to a humidity test (85%/85 °C). Part of the test vehicles were bent during the tests. Finally, the structures of the joints were studied using scanning electron microscopy.     

Kinetics of copper and high Pb/high Sn bilayered Pb-Sn solder interactions

Use of bilayered Pb-Sn solders consisting of high Sn and high Pb solder compositions is an option for joining chips to organic substrates at lower temperatures in which the high Sn solder is deposited onto Cu pads on the substrates. In this work interactions between the two-layered solder and copper pads during the reflow operation have been studied for both flip chip and Ball Grid Array (BGA) applications. It has been observed that Sn from the high Sn solder migrates faster at the edges along the surface of the high Pb solder than at the interior, resulting in a non-uniform Sn concentration along the Cu-solder interface. The thickness of the intermetallic compound formed due to the interaction of Cu and Sn has also been found to be non-uniform along the solder-Cu interface. This has been attributed to the variation in the Sn concentration of the solder adjacent to the Cu pads at different positions. The intermetallic compound growth rate has been explained using a model based on Sn diffusion into copper.     

浅谈镀钯铜线的特性

随着金线价格一路上涨并创下历史新高,大型封装厂正在加大对铜线制程的投入。通过封装厂多年的摸索,发现镀钯铜线是金线很好的替代品。文章分析了镀钯铜线作为键合线材料本身的基本性质,镀钯铜线引线键合的特征和镀钯铜线PCT实验的可靠性。通过分析发现镀钯铜线材料本身有优良的导电和导热特性,同时还有很好的抗氧化性。镀钯铜线在键合过程中需要保护气体的保护,通过硬度实验发现镀钯铜线的硬度较大,因此需要在键合过程中防止弹坑的出现。通过PCT实验证实镀钯铜线具有较好的可靠性。     

A Micromachined Chip-to-Board Interconnect System Using Electroplating Bonding Technology

We demonstrate a micromachined flexible chip-to-board chip interconnect structure for a chip scale package. Micromachined flexible interconnects enable robust operation in high thermal cycling environments, even for high pinout chips due to the flexible interconnect ability to absorb thermal expansion strain. The interconnects on the chip-side and printed wiring board (PWB)-side are united by electroplating bonding technology, a direct bonding technology resulting in solder-free, underfill-free, low temperature joining by means of copper (Cu) electroplating. Over 200 surface micromachined interconnects, which have a thermal relief geometry, are radially arranged on 11 cm substrates. A chip surrogate consisting of glass with integrated platinum (Pt) microheaters mimics a real electronic device under varying thermal loads. The integrated microheaters can simultaneously test mechanical and electrical performance of the interconnects by generation of on-chip temperatures up to 150 C. Lateral and vertical displacement of the interconnects in the thermal environment are measured and simulated. A mechanical reliability test of the chip scale package is successfully performed for 5000 cycles with thermal cycles of 5 min between 40 C to 147 C. No failures were observed during this period.