Power and Interface Features of Thermosonic Flip-Chip Bonding

Driving voltage and current signals of piezoceramic transducer were measured directly by using digital storage oscilloscope, and interface microcharacteristics of the specimens of flip-chip bonding were inspected by using a transmission electron microscope. Results show such a trend that power curves of badly bonding were much lower than that of hard bonding, and indicated a monitoring system of ultrasonic bonding reliability. The acceleration of ultrasonic vibration was about several ten thousand times as acceleration of gravity, which activates dislocations inside the metal crystalline lattice which act as the fast diffusion channels. Dislocation diffusion is more prominent than the crystal diffusion when the temperature is low. Differing from thermal melting mechanism of the reflow bonding, the ultrasonic bonding is much faster than the reflow solder bonding.      

热超声倒装过程中的建模和多参量仿真

热超声键合是一个极其复杂的瞬态过程,利用常规手段不易了解此局部区域内的瞬态特性.针对这个问题,基于MSC.Marc大型非线性有限元分析软件建立了热超声倒装的几何模型,利用其强大的非线性分析能力对热声倒装进行了热力耦合有限元分析,得出了不同摩擦状况对正应力和切应力的分布及大小的影响,金凸点的塑性应变在键合界面上的分布及演变规律,切向位移加载前后键合界面所受正应力和切应力的大小及分布的变化情况,仿真结果对热超声倒装芯片连接工艺的理论研究有着重要的参考价值.     

芯片封装互连新工艺热超声倒装焊的发展现状

介绍了一种芯片封装互连新工艺热超声倒装芯片连接工艺.在比较当前多种芯片封装方式的基础上,总结了这一工艺的特点及优越性,并详细论述了当前这一工艺的技术进展与理论研究状况,指出该工艺是芯片封装领域中具有发展潜力的新工艺.     

Low-Temperature Bonding of Laser Diode Chips on Silicon Substrates Using Plasma Activation of Au Films

A low-temperature bonding of vertical-cavity surface-emitting laser (VCSEL) chips on Si substrates was achieved by using plasma activation of Au films. After the surfaces of Au films were cleaned using an Ar radio frequency plasma, bonding was carried out by contact in ambient air with applied static pressure. The experimental results showed that surface morphological change (the reduction of asperity width) as well as removal of adsorbed organic contaminants by plasma treatment significantly improved the quality of joints. At a bonding temperature of 100degC, the die-shear strength exceeded the failure criteria of MIL-STD-883.     

倒装键合中助焊剂涂敷的工艺优化

助焊剂涂敷是C4凸点焊料的倒装键合中的关键工艺步骤之一,涂敷均匀和稳定性决定了回流焊后整体成品的质量和可靠性,同时影响倒装键合设备的生产效率。在实际生产中,现有的助焊剂涂敷系统影响设备提升生产效率,并且暴露出生产过程中助焊剂泄漏量过大的问题。通过分析现有涂敷系统的问题和助焊剂泄漏的成因,优化设计了一种更高效的助焊剂涂敷系统,有效提升了设备生产率,使泄漏量对生产的影响降低到最小。     

Thermosonic Wire Bonding Process Simulation and Bond Pad Over Active Stress Analysis

In this paper, a transient nonlinear dynamic finite element framework is developed, which integrates the wire bonding process and the silicon devices under bond pad. Two major areas are addressed: one is the impact of assembly 1st wire bonding process and another one is the impact of device layout below the bond pad. Simulation includes the ultrasonic transient dynamic bonding process and the stress wave transferred to bond pad device and silicon in the 1st bond. The Pierce strain rate dependent model is introduced to model the impact stain hardening effect. Ultrasonic amplitude and frequency are studied and discussed for the bonding process. In addition, different layouts of device metallization under bond pad are analyzed and discussed for the efforts to reduce the dynamic impact response of the bond pad over active design. Modeling discloses the stress and deformation impacts to both wire bonding and pad below device with strain rate, different ultrasonic amplitudes and frequencies, different friction coefficients, as well as different bond pad thickness and device layout under pad. The residual stress, after cooling down to a lower temperature, is discussed for the impact of substrate temperature.     

Optimization of Thermomechanical Reliability of Board-Level Flip-Chip Packages Implemented With Organic or Silicon Substrates

A design that optimizes package-level along with board-level thermomechanical reliability of a flip-chip package implemented with an organic or a silicon substrate is provided for the package subjected to an accelerated thermal cycling test condition. Different control factors including thickness of substrate, die, board, and polyimide or soldermask are considered. The optimal design is obtained using an L₉ (3⁴) orthogonal array according to the Taguchi optimization method. Importance of each of these control factors is also ranked.     

Evolution of Contact Resistance during the Bonding Process of NCA Flip-Chip Interconnections

Non-conductive adhesive (NCA) flip-chip interconnects are emerging as an attractive alternative to lead or lead-free solder interconnects due to their environmental friendliness, lower processing temperatures, and extendability to fine-pitch applications. The electrical connectivity of an NCA interconnect relies solely on the pure mechanical contact between the integrated circuit (IC) bump and the substrate pad; the electrical conductivity of the contact depends on the mechanical contact pressure, which in turns depends to a large extent on the cure shrinkage characteristics of the NCA. Therefore, it is necessary to monitor the evolution of the electrical conductivity which could reflect the impact of cure- and thermal-induced stresses during the curing and cooling process, respectively. In this article, in situ measurement of the development of contact resistance during the bonding process of test chips was developed by using a mechanical tester combined with a four-wire resistance measurement system. A drop of resistance induced by the cure stress during the bonding process is clearly observed. With decreasing bonding temperature, the drop of contact resistance induced by cure shrinkage becomes larger, while the cooling-induced drop of resistance becomes smaller. The evolution of contact resistance agrees well with experimental observations of cure stress build-up. It is found that vitrification transformation during the curing of the adhesive could lead to a large cure stress and result in the reduction of the␣contact resistance. Furthermore, no obvious changes were observed when the applied load was removed at the end of bonding.     

Flip-Chip Bonding of MEMS Scanner for Laser Display Using Electroplated AuSn Solder Bump

A MEMS scanner has been flip-chip bonded by using electroplated AuSn solder bumps. The microelectromechanical systems (MEMS) scanner is mainly composed of two structures having vertical comb fingers. To optimize the bonding condition, the MEMS scanner was flip-chip bonded with various bonding temperatures. Scanning electron microscopy (SEM) with an energy dispersive X-ray (EDX) spectroscopic system was used to observe the microstructures of the joints and analyze the element compositions of them. The die shear strength increased as the bonding temperature increased. During the thermal aging test, the delamination occurred at the interconnection of the MEMS scanner bonded at 340 degC. It is inferred that the Au layer serving as pad metallization has been dissolved in the molten AuSn solder totally, and subsequently the Cr layer was directly exposed to the AuSn solder. Judging by the results of both die shear test and thermal aging test, the optimal bonding temperature was found to be approximately 320 degC. Finally, using this MEMS scanner, we obtained an optical scanning angle of 32deg when driven by the ac control voltage of the resonant frequency in the range of 22.1-24.5 kHz with the 100-V dc bias voltages     

热超声键合换能系统设计及性能分析

在热超声键合系统中,超声换能系统是键合装备的核心部分。基于等效电路法和解析法设计换能系统,获得换能系统的基本结构尺寸;基于有限元方法建立系统的仿真模型,获得系统的振动模态特性;采用阻抗分析仪与Doppler测振仪对系统进行性能分析。实验表明,实测频率与设计频率吻合,换能系统阻抗为12.7Ω,振动位移达到3.725μm,满足超声芯片封装的工艺要求。     

A Study on the Thermal Reliability of Cu/SnAg Double-Bump Flip-Chip Assemblies on Organic Substrates

The Cu/SnAg double-bump structure is a promising candidate for fine-pitch flip-chip applications. In this study, the interfacial reactions of Cu (60 μm)/SnAg (20 μm) double-bump flip chip assemblies with a 100 μm pitch were investigated. Two types of thermal treatments, multiple reflows and thermal aging, were performed to evaluate the thermal reliability of Cu/SnAg flip-chip assemblies on organic printed circuit boards (PCBs). After these thermal treatments, the resulting intermetallic compounds (IMCs) were identified with scanning electron microscopy (SEM), and the contact resistance was measured using a daisy-chain and a four-point Kelvin structure. Several types of intermetallic compounds form at the Cu column/SnAg solder interface and the SnAg solder/Ni pad interface. In the case of flip-chip samples reflowed at 250°C and 280°C, Cu₆Sn₅ and (Cu, Ni)₆Sn₅ IMCs were found at the Cu/SnAg and SnAg/Ni interfaces, respectively. In addition, an abnormal Ag₃Sn phase was detected inside the SnAg solder. However, no changes were found in the electrical contact resistance in spite of severe IMC formation in the SnAg solder after five reflows. In thermally aged flip-chip samples, Cu₆Sn₅ and Cu₃Sn IMCs were found at the Cu/SnAg interface, and (Cu, Ni)₆Sn₅ IMCs were found at the SnAg/Ni interface. However, Ag₃Sn IMCs were not observed, even for longer aging times and higher temperatures. The growth of Cu₃Sn IMCs at the Cu/SnAg interface was found to lead to the formation of Kirkendall voids inside the Cu₃Sn IMCs and linked voids within the Cu₃Sn/Cu column interfaces. These voids became more evident when the aging time and temperature increased. The contact resistance was found to be nearly unchanged after 2000 h at 125°C, but increases slightly at 150°C, and a number of Cu/SnAg joints failed after 2000 h. This failure was caused by a reduction in the contact area due to the formation of Kirkendall and linked voids at the Cu column/Cu₃Sn IMC interface.     

楔焊中使用球焊劈刀的可行性分析

传统的键合专用装备中,分为球焊设备和楔焊设备,两者使用不同的换能器,不同种类劈刀,不同的焊接形式。比对了两种焊接形式的共同点,通过改造设备,焊接试验得出凸点的形状,引线的拉断力测试,总结和分析利用球焊设备、劈刀来完成楔形焊接的可行性。     

铜丝球键合工艺及可靠性机理

文章针对铜丝键合工艺在高密度及大电流集成电路封装应用中出现的一系列可靠性问题,对该领域目前相关的理论和研究成果进行了综述,介绍了铜丝球键合工艺、键合点组织结构及力学性能、IMC生长情况、可靠性机理及失效模式。针对铜丝球键合工艺中易氧化、硬度高等难点,对特定工艺进行了阐述,同时也从金属间化合物形成机理的角度重点阐述了铜丝球键合点可靠性优于金丝球键合点的原因。并对铜丝球键合及铜丝楔键合工艺前景进行了展望。     

铝线邦定的可靠性及其应用

通过对铝线邦定在芯片上的可靠性进行研究和试验．结果表明影响其可靠性的因素非常多，如邦定功率、压力以及时间等。本文引用了国际上数篇有关邦定论文的结论，从实际应用出发，阐述了它们的失效状态、干扰因素及控制方法。最后介绍了邦定线在实际应用中的判定方法和技术革新．从而使工程师们在实际应用中能够进一步了解其特性。     

提高基板键合可靠性的等离子清洗工艺研究

通过等离子轰击可以有效提高金丝键合的可靠性。氩气等离子清洗后,基板容易金丝键合,破坏性拉力测试后键合点留压点,键合力有明显提高。5880基板最优的清洗参数是功率200 W,清洗时间600 s,气体流量150 ml/min,并且等离子处理之后2 h内完成键合,效果最佳。     

Reliability of Conductive Adhesives as a Pb-free Alternative in Flip-Chip Applications

The temperature-humidity reliability of anisotropic conductive film (ACF) and non-conductive film (NCF) interconnects is investigated by measuring the interconnect resistance during temperature-humidity testing (THT) at 85°C and 85% relative humidity. The four-point probe method was used to measure the interconnect resistance of the adhesive joints constructed with Au bumps on Si chips and Cu pads on flexible printed circuits (FPCs). The interconnect resistance of the ACF joints was markedly higher than that of the NCF joints, mainly due to the constriction of the current flow and the intrinsic resistance of the conductive particles in the ACF joints. The interconnect resistances of both interconnects decreased with increasing bonding force, and subsequently converged to about 10 mΩ and 1 mΩ at a bonding force of 70 N and 80 N, for the ACF and NCF joints, respectively. During the THT, two different conduction behaviors were observed: increased interconnect resistance and the termination of Ohmic behavior. The former was due to the decreased contact area caused by z-directional swelling of the adhesives, whereas the latter was caused by either contact opening in the adhesive joints or interface cracking.     

改进晶片键合质量可靠性的综合分析方法

对提高半导体工业键合工艺可靠性进行实例研究.首先进行键合工艺技术分析,采用了一种定性方法来辨识故障.实验证实,改进的键合工艺可以降低关键事件对晶片偏转的影响.综合了控制与可靠性工程方面的知识,提出了一种混合的分析方法.     

模板对倒装焊焊点形态的影响及其可靠性研究

本文通过用于焊点形态预测软件SURFACE EVOLVER的输入数据文件,得到倒装焊焊点形态.参考模板开口指导说明(IPC-7525),拟定模板开口方案,得到相应的焊点形态.通过建立有限元模型,运用ANSYS软件对含铅焊点在热循环加载条件下的应力应变和疲劳寿命进行分析.根据预测得到的热疲劳寿命,找出了适合本文模型的模板结构参数,同时分析了其它设计与工艺参数和焊点可靠性之间的关系.     

Comparing the Impacts of the Capillary and the Molded Underfill Process on the Reliability of the Flip-Chip BGA

In the assembly process for the conventional capillary underfill (CUF) flip-chip ball grid array (FCBGA) packaging the underfill dispensing creates bottleneck. The material property of the underfill, the dispensing pattern and the curing profile all have a significant impact on the flip-chip packaging reliability. Due to the demand for high performance in the CPU, graphics and communication market, the large die size with more integrated functions using the low-K chip must meet the reliability criteria and the high thermal dissipation. In addition, the coplanarity of the flip-chip package has become a major challenge for large die packaging. This work investigates the impact of the CUF and the novel molded underfill (MUF) processes on solder bumps, low-K chip and solder ball stress, packaging coplanarity and reliability. Compared to the conventional CUF FCBGA, the proposed MUF FCBGA packaging provides superior solder bump protection, packaging coplanarity and reliability. This strong solder bump protection and high packaging reliability is due to the low coefficient of thermal expansion and high modulus of the molding compound. According to the simulation results, the maximum stress of the solder bumps, chip and packaging coplanarity of the MUF FCBGA shows a remarkable improvement over the CUF FCBGA, by 58.3%, 8.4%, and 41.8% (66 $mu {rm m}$), respectively. The results of the present study indicates that the MUF packaging is adequate for large die sizes and large packaging sizes, especially for the low-K chip and all kinds of solder bump compositions such as eutectic tin-lead, high lead, and lead free bumps.