Design and implementation of a modulator-based free-space optical backplane for multiprocessor applications

Design and implementation of a free-space optical backplane for multiprocessor applications is presented. The system is designed to interconnect four multiprocessor nodes that communicate by using multiplexed 32-bit packets. Each multiprocessor node is electrically connected to an optoelectronic VLSI chip which implements the hyperplane interconnection architecture. The chips each contain 256 optical transmitters (implemented as dual-rail multiple quantum-well modulators) and 256 optical receivers. A rigid free-space microoptical interconnection system that interconnects the transceiver chips in a 512-channel unidirectional ring is implemented. Full design, implementation, and operational details are provided.     

Performance scaling comparison for free-space optical and electrical interconnection approaches

Projected performance metrics of free-space optical and electrical interconnections are estimated and compared in terms of smart-pixel input-output bandwidth density and practical geometric packaging constraints. The results suggest that three-dimensional optical interconnects based on smart pixels provide the highest volume, latency, and power-consumption benefits for applications in which globally interconnected networks are required to implement links across many integrated-circuit chips. It is further shown that interconnection approaches based on macro-optical elements achieve better scaling than those based on micro-optical elements. The scaling limits of micro-optical-based architectures stem from the need for repeaters to overcome diffraction losses in multichip architectures with high bisection bandwidth. The overall results provide guidance in determining whether and how strongly a free-space optical interconnection approach can be applied to a given multiprocessor problem.     

Hybrid free-space optical bus system for board-to-board interconnections

A free-space optical bus system is described for board-to-board interconnections at the backplane level. The system uses active optoelectronic modules as the interface between the circuit boards and the electrical backplane. Substrate-mode holograms are used to implement signal broadcast operations between boards, and each board on the backplane shares common free-space channels for transmitting and receiving signals. System-design considerations are given, and the potential performance of the optical bus system is evaluated. An experimental demonstration is also presented for the signal broadcast operation through cascaded substrate-mode holograms at a data rate of 622 Mb/s.     

Design and characterization of a microchannel optical interconnect for optical backplanes

The design, modeling, and experimental characterization of a microchannel-based free-space optical interconnect is described. The microchannel interconnect was used to implement a representative portion of an optical backplane that was based on field-effect transistor, self-electro-optic device smart-pixel transceivers. Telecentric relays were used to form the optical interconnect, and two modes based on two different optical window clusterings were implemented. The optical system design, including the optical geometry for different degrees of clustering of windows supported by a lenslet relay and the image mapping associated with a free-space optical system, is described. A comparison of the optical beam properties at the device planes, including the spot size and power uniformity of the spot array, as well as the effects of clipping and misalignment for the different operating modes, is presented. In addition, the effects of beam clipping and misalignment for the different operating modes is presented. We show that microchannel free-space optical interconnects based on a window-clustering scheme significantly increase the connection density. A connection density of 2222 connections/cm(2) was achieved for this prototype system with 2 x 2 window clustering.     

Low-order adaptive optics for free-space optoelectronic interconnects

The concept of adaptive optics for improving the cost-performance of free-space optoelectronic interconnects is discussed. Adaptive optics as a design option for optical interconnect systems is presented and discussed. A practical demonstrator that performs low-order correction was built and tested. Slowly varying misalignments, including thermal effects, were compensated for in a 622-Mbit/s free-space optical data link.     

Optoelectronic Systems Based on InGaAs- Complementary-Metal-Oxide-Semiconductor Smart-Pixel Arrays and Free-Space Optical Interconnects

Free-space optical interconnects have been identified as a potentially important technology for future massively parallel-computing systems. The development of optoelectronic smart pixels based on InGaAs/AlGaAs multiple-quantum-well modulators and detectors flip-chip solder-bump bonded onto complementary-metal-oxide-semiconductor (CMOS) circuits and the design and construction of an experimental processor in which the devices are linked by free-space optical interconnects are described. For demonstrating the capabilities of the technology, a parallel data-sorting system has been identified as an effective demonstrator. By use of Batcher's bitonic sorting algorithm and exploitation of a perfect-shuffle optical interconnection, the system has the potential to perform a full sort on 1024, 16-bit words in less than 16 mus. We describe the design, testing, and characterization of the smart-pixel devices and free-space optical components. InGaAs-CMOS smart-pixel, chip-to-chip communication has been demonstrated at 50 Mbits/s. It is shown that the initial system specifications can be met by the component technologies.     

Practical realization of massively parallel fiber-free-space optical interconnects

We propose a novel approach to realizing massively parallel optical interconnects based on commercially available multifiber ribbons with MT-type connectors and custom-designed planar-integrated free-space components. It combines the advantages of fiber optics, that is, a long range and convenient and flexible installation, with those of (planar-integrated) free-space optics, that is, a wide range of implementable functions and a high potential for integration and parallelization. For the interface between fibers and free-space optical systems a low-cost practical solution is presented. It consists of using a metal connector plate that was manufactured on a computer-controlled milling machine. Channel densities are of the order of 100/mm(2) between optoelectronic VLSI chips and the free-space optical systems and 1/mm(2) between the free-space optical systems and MT-type fiber connectors. Experiments in combination with specially designed planar-integrated test systems prove that multiple one-to-one and one-to-many interconnects can be established with not more than 10% uniformity error.     

Misalignment correction for optical interconnects using vertical cavity semiconductor optical amplifiers

In board-to-board optical interconnects, the misalignment between the board and the backplane connections can cause both optical loss and interchannel cross talk. A vertical cavity semiconductor optical amplifier (VCSOA) is proposed to correct optical misalignment in an optical connector between the board and the backplane. Angular or lateral misalignment can be corrected with the designed module. The correction ability is determined by the acceptance angle of the VCSOA, which was characterized to be 9.4 degrees full angle at a 3 dB gain drop for a 30 microW optical signal at 1 GHz. The lateral misalignment correction ability is 0.16f, where f is the focal length of the mini lens to converge the input light onto the VCSOA.     

Tolerancing of board-level-free-space optical interconnects

For optical interconnects to become a mature technology they must be amenable to electronic packaging technology. Two main obstacles to including free-space optical interconnects are alignment and heat-dissipation issues. Here we study the issues of alignment tolerancing that are due to assembly and manufacturing variations (passive-element tolerancing) over long board-level distances (>10 cm) for free-space optical interconnects. We also combine these variations with active optoelectronic device variations (active-element tolerancing). We demonstrate a computer-aided analysis procedure that permits one to determine both active- and passive-element tolerances needed to achieve some system-level specification, such as yield or cost. The procedure that we employ relies on developing a detailed design of the system to be studied in a standard optical design program, such as code v. Using information from this model, we can determine the integrated power falling on the detector, which we term optical throughput, by performing Gaussian propagation or general Fresnel propagation (if significant vignetting occurs). This optical throughput can be used to determine system-level performance criteria, such as bit-error rate. With this computer-aided analysis technique, a sensitivity analysis of all the variations under study is made on a system with realistic board-level interconnect distances to find each perturbation's relative effects (with other perturbations set to 0) on the power falling on the detector. This information is used to set initial tolerances for subsequent tolerancing analysis and design runs. A tolerancing analysis by Monte Carlo techniques is applied to determine if the yield or cost (yield is denned as the percentage of systems that have acceptable system performance) is acceptable. With a technique called parametric sampling, a subsequent tolerancing design run can be applied to optimize this yield or cost with little increase in computation. We study a design example and show that most of the tolerances can be achieved with current technology.     

Diffractive optics applied to free-space optical interconnects

The optimum design of free-space optical interconnection systems utilizing diffractive optics is determined from a practical engineering standpoint for systems ranging from space invariant to fully space variant. System volume is calculated in terms of parameters such as the f-number of the diffractive lens, the wavelength of light, and also the total number, size, and separation of the optical sources and detectors. Performance issues such as interconnection complexity, diffraction efficiency, and signal-tonoise ratio are discussed. Diffractive optics fabricated by electron-beam direct-write techniques are used to provide experimental results for both shuffle-exchange and twin-butterfly free-space optical interconnects.     

Multiscale free-space optical interconnects for intrachip global communication: motivation, analysis, and experimental validation

The use of optical interconnects for communication between points on a microchip is motivated by system-level interconnect modeling showing the saturation of metal wire capacity at the global layer. Free-space optical solutions are analyzed for intrachip communication at the global layer. A multiscale solution comprising microlenses, etched compound slope microprisms, and a curved mirror is shown to outperform a single-scale alternative. Microprisms are designed and fabricated and inserted into an optical setup apparatus to experimentally validate the concept. The multiscale free-space system is shown to have the potential to provide the bandwidth density and configuration flexibility required for global communication in future generations of microchips.     

Guided-wave and free-space optical interconnects for parallel-processing systems: a comparison

Guided-wave and free-space optical interconnects are compared based on insertion loss, link efficiency, connection density, time delay, and power dissipation for three types of connection networks. Three types of free-space interconnect systems are analyzed that are representative of a wide variety of free-space systems: space-variant basis-set and space-invarient systems. Results indicate that the connection density of a space-variant free space system has a connection density roughly equivalent to a two level guided-wave system with a pitch of ~10 μm (for a 1-μm wavelength) and a core refractive index of 2.0. It is also shown that the connection density of basis-set and space-invariant free-space systems can be several orders of magnitude higher than fundamental limits on the connection density of dual-level guided-wave interconnect systems when large-scale highly connected networks are employed.     

Non-display applications and the next generation of liquid crystal over silicon technology

The next generation of applications for liquid crystal (LC) over silicon technology will be non-display oriented systems such as adaptive optical interconnects, optical switches and optical image processors. These new non-display applications have a different set of material parameters, which means that existing display-based materials are not entirely optimal. This is particularly the case when the application is driven by phase modulation at high frame rates (more than 1 kHz). An example of such a non-display application is in adaptive optical interconnects. Optical data transmission between printed circuit boards is becoming more and more important as the data rate in electronic systems increases into the gigahertz region. One way of avoiding the data bottlenecks in board to board interconnects is to use optical links to transmit the data. Recent research into free-space optical links has shown that a high level of manufacturing tolerance must be used to maintain the link. However, one way of avoiding these limitations is to use a reconfigurable LC phase hologram as a beam-steering element to compensate for movement between the boards and maintain the optical data path.     

Experimental and numerical analyses of misalignment tolerances in free-space optical interconnects

A comparison of numerical analyses with experimental measurements suggests that both the ray-tracing and the Gaussian beam-propagation models overestimate the misalignment tolerances for on-axis beams and fail to predict the large longitudinal focal shift that occurs for off-axis beams propagating in free-space optical interconnects.     

Tolerance stackup effects in free-space optical interconnects

A numerical analysis indicates that tolerance stackup effects in free-space optical interconnects are significant even for short systems containing few components. Results prove that worst-case or root-sum-square analyses are not adequate to predict probable performance accurately. A Monte Carlo analysis must be performed.     

Experimental demonstration of the optical multi-mesh hypercube: scaleable interconnection network for multiprocessors and multicomputers

A prototype of a novel topology for scaleable optical interconnection networks called the optical multi-mesh hypercube (OMMH) is experimentally demonstrated to as high as a 150-Mbit/s data rate (2(7) - 1 nonreturn-to-zero pseudo-random data pattern) at a bit error rate of 10(-13)/link by the use of commercially available devices. OMMH is a scaleable network [Appl. Opt. 33, 7558 (1994); J. Lightwave Technol. 12, 704 (1994)] architecture that combines the positive features of the hypercube (small diameter, connectivity, symmetry, simple routing, and fault tolerance) and the mesh (constant node degree and size scaleability). The optical implementation method is divided into two levels: high-density local connections for the hypercube modules, and high-bit-rate, low-density, long connections for the mesh links connecting the hypercube modules. Free-space imaging systems utilizing vertical-cavity surface-emitting laser (VCSEL) arrays, lenslet arrays, space-invariant holographic techniques, and photodiode arrays are demonstrated for the local connections. Optobus fiber interconnects from Motorola are used for the long-distance connections. The OMMH was optimized to operate at the data rate of Motorola's Optobus (10-bit-wide, VCSEL-based bidirectional data interconnects at 150 Mbits/s). Difficulties encountered included the varying fan-out efficiencies of the different orders of the hologram, misalignment sensitivity of the free-space links, low power (1 mW) of the individual VCSEL's, and noise.     

Analysis of optical channel cross talk for free-space optical interconnects in the presence of higher-order transverse modes

We analyze the effect of cross-talk noise on the performance of free-space optical interconnects (FSOIs). In addition to diffraction-caused cross talk, we consider the effect of stray-light cross-talk noise, an issue that, to the best of our knowledge, was not addressed previously. Simulations were performed on a microlens-based FSOI system using the modal composition and beam profiles experimentally extracted from a commercial vertical-cavity surface-emitting laser. We demonstrate that this cross-talk noise introduces significant degradation to interconnect performance, particularly for multitransverse-mode laser sources. A simple behavioral model is also developed that accurately approximates the cross talk noise for a range of optical sources and interconnect configurations.     

Free-space parallel multichip interconnection system

A parallel data-communication scheme is described for interchip communication with free-space optics. We present a proof-of-concept and feasibility demonstration of a practical modular packaging approach in which free-space optical interconnect modules can be simply integrated on top of an electronic multichip module (MCM). Our packaging architecture is based on a modified folded 4-f imaging system that is implemented with off-the-shelf optics, conventional electronic packaging techniques, and passive assembly techniques to yield a potentially low-cost packaging solution. The prototype system, as built, supports 48 independent free-space channels with eight separate laser and detector chips, in which each chip consists of a one-dimensional array of 12 devices. All chips are assembled on a single ceramic carrier together with three silicon complementary metal-oxide semiconductor chips. Parallel optoelectronic (OE) free-space interconnections are demonstrated at a speed of 200 MHz. The system is compact at only 10 in.(3) (~164 cm(3)) and is scalable because it can easily accommodate additional chips as well as two-dimensional OE device arrays for increased interconnection density.     

Multichip module with planar-integrated free-space optical vector-matrix-type interconnects

Even in the semiconductor industry, free-space optical technology is nowadays seen as a prime option for solving the continually aggravating problem with VLSI chips, namely, that the interconnect technology has failed to keep pace with the increase in communication volume. To make free-space optics compatible with established lithography-based design and fabrication techniques the concept of planar integration was proposed approximately a decade ago. Here its evolution into a photonic microsystems engineering concept is described. For demonstration, a multichip module with planar-integrated freespace optical vector-matrix-type interconnects was designed and built. It contains flip-chip-bonded vertical-cavity surface emitting laser arrays and a hybrid chip with an array of multiple-quantum-well p-i-n diodes on top of a standard complementary metal-oxide semiconductor circuit as key optoelectronic hardware components. The optical system is integrated into a handy fused-silica substrate and fabricated with surface-relief diffractive phase elements. It has been optimized for the given geometrical and technological constraints and provides a good interconnection performance, as was verified in computer simulations on the basis of ray tracing and in practical experiments.     

Two-bounce optical arbitrary permutation network

The two-bounce free-space arbitrary interconnection architecture is presented. It results from a series of three-dimensional topological transformations to the Benes network, the minimum rearrangeable nonblocking network. Although functionally equivalent to the Benes network, it requires only two stages of global (spanning multiple chips) optical interconnections. The remaining stages of the modified Benes interconnection network are local and are implemented electronically (on individual chips). The two-bounce network is optimal in the sense that it retains the Benes minimum number of electronic switching resources yet also minimizes the number of optical links needed for global interconnection. Despite the use of higher-order k-shuffle (k > 2) global optical interconnects, the number of 2 x 2 switching elements is identical to the two-shuffle Benes network: there is no need for k x k crossbar switches for local interconnection at each stage. An experimental validation of the two-bounce architecture is presented.