共查询到18条相似文献,搜索用时 156 毫秒
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周景龙 《微电子学与计算机》2014,(5):32-35
提出了一种基于高速FFT结构的算法硬件设计与实现,FFT采用基4算法,旋转因子采用CORDIC算法生成,节省了存储资源,最后在硬件平台上测试,取得了很好的抗干扰效果. 相似文献
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马滕斯(Martens)提出了一种效率高(可与WFTA法和PFA法相比拟)、结构简单(与FFT法相似)的DFT计算方法RGFA。作者已经证明,在基2的情况下,RCFA与旋转因子合并的频率抽取FFT算法是完全等价的。本文给出了旋转因子合并的时间抽取FFT算法,从而使得在任何条件下,目前使用的FFT算法都可以用外部特性完全相同、内部结构基本相同的高效算法旋转因子合并FFT算法来代替。本文还给出了实现旋转因子合并FFT算法的软件。 相似文献
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针对有限区间哈默斯坦(Hammerstein)非线性时变系统,该文提出一种加权迭代学习算法用以估计系统时变参数。首先将Hammerstein系统输入非线性部分进行多项式展开,采用迭代学习最小二乘算法辨识系统的时变参数。为了防止数据饱和,采用带遗忘因子的迭代学习最小二乘算法,进而引入权矩阵,采用加权迭代学习最小二乘算法改进系统跟踪误差,以提高辨识精度。该文分别给出3种算法的推导过程并进行仿真验证。结果表明,与迭代学习最小二乘算法和带遗忘因子迭代学习最小二乘算法相比,加权迭代学习最小二乘算法具有辨识精度高、跟踪误差小以及迭代次数少等优点。 相似文献
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The fast Fourier transform (FFT) is an algorithm widely used to compute the discrete Fourier transform (DFT) in real-time digital signal processing. High-performance with fewer resources is highly desirable for any real-time application. Our proposed work presents the implementation of the radix-2 decimation-in-frequency (R2DIF) FFT algorithm based on the modified feed-forward double-path delay commutator (DDC) architecture on FPGA device. Need for a complex multiplier to carry out the multiplication of complex twiddle factors and large memory to store the twiddle factors are the main concerns for FFT implementation. Propose work aims to address these issues. In this work, a high-performance radix-16 COordinate Rotational DIgital Computer (CORDIC) algorithm based rotator is proposed to carry out the complex twiddle factor multiplication. Further, CORDIC needs only rotational angles to carry out complex multiplication, which reduces the need for large memory to store the twiddle factors. To compute the total rotation for n-bit precision, our proposed radix-16 CORDIC algorithm takes n/4 iteration as compared to n iteration of the radix-2 CORDIC algorithm. Our proposed architecture of the radix-2 decimation-in-frequency (R2DIF) algorithm is implemented on a Virtex−7 series FPGA. Further, the detailed comparison is presented between our proposed FFT implementation and other recently proposed FFT implementations. Experimental results suggest that proposed implementation has less latency and hardware utilization as compared to recently proposed implementations. 相似文献
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Martens proposed a highly efficient and simply formed DFT algorithm——RCFA,whose efficien-cy is comparable with that of WFTA or that of PFA,and whose structure is similar to that of FFT.Theauthors have proved that,in the case of radix 2,the RCFA is exactly equivalent to the twiddle factor mergedfrequency-decimal FFT algorithm.The twiddle factor merged time-decimal FFT algorithm is providedin this paper.Thus,in any case,the FFT algorithm used currently can be replaced by the more efficientalgorithm——the twiddle factor merged FFT algorithm,with exactly the same external property and thesimilar internal structure.Also in this paper,the software for implementing the twiddle factor merged FFTalgorithm(TMFFT)is provided. 相似文献
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对于大点数FFT处理器,提出了一种新的旋转因子生成方法。首先对三角函数曲线分段进行折线近似,将线段端点及斜率存入存储器,然后通过查表以及插值计算的方法来生成旋转因子。在保证FFT计算精度的前提下,极大地降低了对旋转因子存储器容量的需求,对大点数FFT处理器的单片ASIC实现具有重要意义。 相似文献
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Lee H.-Y. Park I.-C. 《IEEE transactions on circuits and systems. I, Regular papers》2007,54(4):889-900
This paper presents an area-efficient algorithm for the pipelined processing of fast Fourier transform (FFT). The proposed algorithm is to decompose a discrete Fourier transform (DFT) into two balanced sub-DFTs in order to minimize the total number of twiddle factors to be stored into tables. The radix in the proposed decomposition is adaptively changed according to the remaining transform length to make the transform lengths of sub-DFTs resulting from the decomposition as close as possible. An 8192-point pipelined FFT processor designed for digital video broadcasting-terrestrial (DVB-T) systems saves 33% of general multipliers and 23% of the total size of twiddle factor tables compared to a conventional pipelined FFT processor based on the radix-22 algorithm. In addition to the decomposition, several implementation techniques are proposed to reduce area, such as a simple index generator of twiddle factor and add/subtract units combined with the two's complement operation 相似文献
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设计和实现超高速快速傅里叶变换器(FFT)在雷达与未来无线通信等系统中具有重要意义。该文提出首个全并行架构的FFT处理器,其避免了复杂的路由寻址以及数据访问冲突等问题,基于较大基进行分解降低运算复杂度。由于旋转因子已知和固定,大量的乘法转化为了定系数乘法。同时由于采用了串行的计算单元,在达到全并行结构的高速度同时硬件复杂度相对较低;所有的硬件计算单元处于满载的条件,其硬件效率能达到100%。根据实际的实现结果,所提出的512点FFT处理器结构能够达到5.97倍速度面积比的提升,同时硬件开销仅占用了Xilinx V7-980t FPGA 30%的查找表资源与9%的寄存器资源。 相似文献
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基于CORDIC的一种高速实时定点FFT的FPGA实现 总被引:10,自引:1,他引:9
本文论述了一种利用CORDIC算法在FPGA上实现高速实时定点FFF的设计方案。利用CORDIC算法来实现复数乘法,与使用乘法器相比降低了系统的资源占用率,提高了系统速度[1]。设计基于基4时序抽取FFT算法,采用双端口内置RAM和流水线串行工作方式。本设计针对256点、24位长数据进行运算,在XilnxSpartan2E系列的xc2s300e器件下载验证通过,完成一次运算约为12μs,可运用于高速DSP、数字签名算法等对速度要求高的领域。 相似文献
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基于改进FFT算法的OFDM调制/解调模块设计 总被引:4,自引:4,他引:0
文章对传统FFT算法进行了改进,改进后的算法将N点DFT分解成二维√N点DFT的组合,在结构上更适合于用流水线方式实现FFT.文章首先对算法进行了推导,然后基于该算法设计了一个64点、32位字长的定点IFFT/FFT模块,用于802.11a中OFDM的调制/解调.与传统的流水线FFT比较,该模块中的复数乘法运算全部采用移位相加操作完成,因而消除了乘法器及旋转因子ROM的使用,降低了功耗.最后,对该模块进行了验证仿真.结果表明,在流水线饱和的情况下,该模块完成一个64点的FFT运算只需要8个时钟周期,在20MHZ时钟频率下,该模块的功耗为0.26W,完全能满足移动通信中对于高速度、低功耗的要求. 相似文献