A weak-to-strong inversion mismatch model for analog circuit design

This paper reports on a new CMOS transistor mismatch model that is continuous from weak to strong inversion. The model is completely described by analytical equations which are based on either the ACM or EKV transistor models. Large signal ACM and EKV transistor equations including the relevant parameters for mismatch are used for fitting the measured data. Five parameters are found to be relevant for predicting mismatch from weak to strong inversion: specific current I _s , threshold voltage V _T0, gamma γ, θ _o (dependent on mobility degradation and source-drain series resistances), and θ _e (dependent on velocity saturation and drain series resistance). Arrays of NMOS and PMOS transistors of 30 different sizes were fabricated in a 0.35 μm CMOS process. For each transistor size 12 different curves were measured. Different mismatch parameter extraction methods were used and compared. Average current mismatch prediction error was found to be in the range between 4 and 10% in the whole bias range from weak to strong inversion. Worst case mismatch prediction errors were in the range 23–61%. Since mismatch was predicted for a large number of sizes, the model could be implemented in a conventional circuit simulator to predict transistor mismatch not only as a function of transistor area but as function of transistor width and length independently. It was found that minimum mismatch is not always achieved by square transistors, and that mismatch is less sensitive to reducing width than to reducing length.     

A physical compact model of DG MOSFET for mixed-signal circuit applications- part I: model description

To use double-gate (DG) MOSFET for mixed-signal circuit applications, especially for circuits in which the two gates are independently driven, such as in the case of dynamic-threshold and fixed-potential-plane operations, physical compact models that are valid for all modes of operations are necessary for accurate design and analysis. Employing physically rigorous current-voltage (I-V) relationship in subthreshold and above-threshold regions as asymptotic cases, we have constructed a model that joins the two operating regions by using carrier-screening functions. We have included consistently source/drain series resistance, low drain-field mobility, and small-geometry effects of drain-induced barrier lowering (DIBL), MOS interface mobility, velocity saturation and channel-length modulation (CLM) with validation from two-dimensional (2-D) distributed simulation. All model parameters can be extracted from large-signal I-V characteristics in dc conditions with given geometrical data. Parameter extraction methods and verification from simulation are presented in Part II.     

Understanding MOSFET mismatch for analog design

Despite the significance of matched devices in analog circuit design, mismatch modeling for design application has been lacking. This paper addresses misconceptions about MOSFET mismatch for analog design. V/sub t/ mismatch does not follow a simplistic 1/(/spl radic/area) law, especially for wide/short and narrow/long devices, which are common geometries in analog circuits. Further, V/sub t/ and gain factor are not appropriate parameters for modeling mismatch. A physically based mismatch model can be used to obtain dramatic improvements in prediction of mismatch. This model is applied to MOSFET current mirrors to show some nonobvious effects over bias, geometry, and multiple-unit devices.     

A physics-based MOSFET noise model for circuit simulators

Discussed is a physics-based MOSFET noise model that can accurately predict the noise characteristics over the linear, saturation, and subthreshold operating regions but which is simple enough to be implemented in any general-purpose circuit simulator. Expressions for the flicker noise power are derived on the basis of a theory that incorporates both the oxide-trap-induced carrier number and correlated surface mobility fluctuation mechanisms. The model is applicable to long-channel, as well as submicron n- and p-channel MOSFETs fabricated by different technologies, and all the model parameters can be easily extracted from routine I-V and noise measurements     

A unified short-channel compact model for cylindrical surrounding-gate MOSFET

For the first time, a continuous and explicit model valid in all operating regions, for undoped short-channel cylindrical gate-all-around (GAA) MOSFETs, is presented in this study. From a two-dimensional analysis, the threshold voltage roll-off, the drain-induced barrier lowering (DIBL) and the subthreshold swing are explicitly modeled. Short-channel effects are then implemented into a continuous drain-current model based on an effective surface potential approach using the gradual channel approximation. Improving the model behavior in the saturation operating region by accounting the channel pinch-off displacement, channel length modulation is studied and implemented as well. Analytical results are compared to TCAD-Atlas numerical simulations and validate the short-channel model in all operating modes making it suitable for circuit design simulations.     

A compact scattering model for the nanoscale double-gate MOSFET

An analytically compact model for the nanoscale double gate metal-oxide semiconductor field effect transistor (MOSFET) based on McKelvey's flux theory is developed. The model is continuous above and below threshold and from the linear to saturation regions. Most importantly, it describes nanoscale MOSFETs from the diffusive to ballistic regimes. In addition to its use in exploring the limits and circuit applications of double gate MOSFETs, the model also serves as an example of how semiclassical scattering theory can be used to develop physically sound models for nanoscale transistors     

A physical compact model of DG MOSFET for mixed-signal circuit applications - part II: Parameter extraction

For pt. see ibid., vol. 50, no. 10, p. 2135 (2003). Based on the physical double-gate MOSFET model described in Part I, we present a systematic parameter extraction methodology that avoids parameter interdependence between different physical effects whenever possible. Several extraction schemes are compared for precise modeling of small-signal and large-signal characteristics. The physical model and the extraction methodology are verified through the reproduction of the simulated drain current, incremental drain resistance, and transconductance per unit current, which are parameters of particular interest to mixed-signal circuit designs.     

A compact model for flicker noise in MOS transistors for analog circuit design

Designers need accurate models to estimate 1/f noise in MOS transistors as a function of their size, bias point, and technology. Conventional models present limitations; they usually do not consistently represent the series-parallel associations of transistors and may not provide adequate results for all the operating regions, particularly moderate inversion. In this brief, we present a consistent, physics-based, one-equation-all-regions model for flicker noise developed with the aid of a one-equation-all-regions dc model of the MOS transistor.     

Small-signal MOSFET models for analog circuit design

Presents first-order large-signal MOSFET models and derives corresponding small-signal models. The parameters of the small-signal models are related to operating-point bias and to the parameters of the IC process used to fabricate the device. The impact upon small-signal performance of many second-order effects present in small-geometry MOSFETs is explored. A representative analog circuit, fabricated with a 1 /spl mu/m feature-size NMOS technology, is analyzed using the small-signal models derived. Results of approximate analysis, without the use of computer aids, are compared with detailed computer simulation results.     

A continuous compact MOSFET model for fully- and partially-depletedSOI devices

A fully continuous compact SOI MOSFET model for circuit simulations, that automatically accounts for the for the correct body depletion condition, is presented. Unlike previously reported models that are derived for either fully-depleted (FD) or partially-depleted (PD) devices, our model accounts for the possible transitions between FD and PD behavior during the device operation     

An improved MOSFET model for circuit simulation

Problems that have continued to remain in some of the recently published MOSFET compact models are demonstrated in this paper. Of particular interest are discontinuities observed in these models at the boundary between forward and reverse mode operation. A new MOSFET model is presented that overcomes the errors present in state-of-the-art models. Comparison with measured data is also presented to validate the new model     

MOSFET substrate current model for circuit simulation

A simple, accurate MOSFET substrate current model suitable for a circuit simulator is presented. The effect of substrate bias on substrate current is modeled without introducing additional parameters. The accuracy of this model is demonstrated by its ability to fit the experimental data for both standard and LDD devices with average errors of less than 6%. The new model is compared with the substrate current models reported in the literature. In addition, the temperature dependence of the substrate current in the range of 0-120°C is also modeled. The new model has been implemented in a circuit-level hot-electron reliability simulator, and the results obtained from simulation of an inverter circuit are presented     

一种单材料双功函数栅MOSFET解析模型

An analytical surface potential model for the single material double work function gate(SMDWG) MOSFET is developed based on the exact resultant solution of the two-dimensional Poisson equation. The model includes the effects of drain biases, gate oxide thickness, different combinations of S-gate and D-gate length and values of substrate doping concentration. More attention has been paid to seeking to explain the attributes of the SMDWG MOSFET, such as suppressing drain-induced barrier lowering(DIBL), accelerating carrier drift velocity and device speed. The model is verified by comparison to the simulated results using the device simulator MEDICI. The accuracy of the results obtained using our analytical model is verified using numerical simulations. The model not only offers the physical insight into device physics but also provides the basic designing guideline for the device.     

A compact double-gate MOSFET model comprising quantum-mechanicaland nonstatic effects

In this work, we investigate the electrical properties of the Double-Gate MOSFET (DG-MOSFET), which turn out to be very promising for device miniaturization below 0.1 μm. A compact model which accounts for charge quantization within the channel, Fermi statistics, and nonstatic effects in the transport model is worked out. The main results of this investigation are: (1) the ideality factor in subthreshold is equal to unity, i.e., the slope of the turn-on characteristic is 60 mV/decade at room temperature; (2) the drain-induced barrier lowering is minimized by the shielding effect of the double gate, which allows us to reduce the channel length below 30 nm; and (3) the device transconductance per unit width is maximized by the combination of the double gate and by a strong velocity overshoot which occurs in response to the sudden variation of the electric field at the source end of the channel, and which can be further strengthened near the drain in view of the short device length. As a result, a sustained electron velocity of nearly twice the saturation velocity is achievable. The above results prove that the potential performance advantages of the double-gate device architecture may be worth the development effort     

A novel surface potential-based short channel MOSFET model for circuit simulation

In this paper a novel analytical approximation method for surface potential (ψ_s) calculation in compact MOSFET model is presented. It achieves excellent accuracy and good calculation speed over all regions from accumulation to strong inversion. With this approximation method, a surface potential-based compact model for short channel MOSFET is developed. Comparison with measured data is also presented to validate the new model.     

On gate leakage current partition for MOSFET compact model

Aggressive scaling of the gate-oxide thickness has made gate-tunneling current an essential aspect of MOSFET modeling and this leakage current density continues to increase for every process generation. Accurate compact models for gate-tunneling current and its source/drain partition are extremely critical to valid circuit performance in the 90 nm technology or beyond. Gate current partition has been studied by several authors [Cao K, et al. “BSIM4 gate leakage model including source–drain partition,” in IEDM Tech. Dig., San Francisco, CA, Dec. 2000. p. 815–8; R. van Langevelde et al., Gate current: modeling, ΔL extraction and impact on RF performance, in IEDM Tech. Dig., Washington, DC, Dec. 2001. p. 289–92; Shih W-K, et al., “A general partition scheme for gate leakage current suitable for MOSFET compact models,” in IEDM Tech. Dig., Washington DC., Dec. 2001. p. 293–6]. In this paper, an insight on the common/difference of these different gate leakage current partition schemes into source/drain has been provided and the accuracy of BSIM4 [Cao K, et al. “BSIM4 gate leakage model including source–drain partition,” in IEDM Tech. Dig., San Francisco, CA, Dec. 2000. p. 815–8] partition scheme is confirmed with comparing to the new derived equation, which incorporates the gate current into the inhomogeneous term calculation.     

A compact MOST model for design analysis

A dc model of the 4-terminal MOS transistor is described that eliminates the need for piecewise definition of the channel current while maintaining sufficient physical correspondence to accurately represent modern MOS devices used in arrays. The determination of model parameters is straightforward.     

Three-dimensional table look-up MOSFET model for precise circuit simulation

A three-dimensional table look-up MOSFET modeling technique is described. The table, which is able to deal with future submicron devices, is constructed with a few thousand work memory capacity requirement by suppressing data redundancy. Sufficiently high accuracy, with less than point several percent error, is achieved by using a special interpolation, which is called curve shape fitting technique. Computational time to perform the interpolation from the table is much less than that for the analytical model.     

SP: an advanced surface-potential-based compact MOSFET model

This work describes an advanced physics-based compact MOSFET model (SP). Both the quasistatic and nonquasi-static versions of SP are surface-potential-based. The model is symmetric, includes the accumulation region, small-geometry effects, and has a consistent current and charge formulation. The surface potential is computed analytically and there are no iterative loops anywhere in the model. Availability of the surface potential in the source-drain overlap regions enables a physics-based formulation of the extrinsic model (e.g., gate tunneling current) and allows for a noise model free of discontinuities or unphysical interpolation schemes. Simulation results are used to illustrate the interplay between the model structure and circuit design.