A physically based,accurate compact model of direct tunneling gate current considering quantum mechanical effects in nanoscale metal‐oxide‐semiconductor field‐effect transistors

We present a physically based, accurate model of the direct tunneling gate current of nanoscale metal‐oxide‐semiconductor field‐effect transistors considering quantum mechanical effects. Effect of wave function penetration into the gate dielectric is also incorporated. When electrons tunnel from the metal oxide semiconductor inversion layer to the gate, the eigenenergies of the quasi‐bound states turn out to be complex quantities. The imaginary part of these complex eigenenergies, Γ_ij, are required to estimate the finite lifetimes of these states. We present an empirical equation of Γ_ij as a function of surface potential. Inversion layer electron concentration is determined using eigenenergies, calculated by modified Airy function approximation. Hence, a compact model of direct tunneling gate current is proposed using a novel approach. Good agreement of the proposed compact model with self‐consistent numerical simulator and published experimental data for a wide range of substrate doping densities and oxide thicknesses states the accuracy and robustness of the proposed model. The proposed model can well be extended for devices with high‐κ/stack gate dielectrics introducing necessary modifications. Copyright © 2011 John Wiley & Sons, Ltd.     

An ultra‐thin oxide sub‐1 V CMOS bandgap voltage reference

This paper presents a sub‐1 V CMOS bandgap voltage reference that accounts for the presence of direct tunneling‐induced gate current. This current increases exponentially with decreasing oxide thickness and is especially prevalent in traditional (non‐high‐κ/metal gate) ultra‐thin oxide CMOS technologies (t_ox < 3 nm), where it invalidates the simplifying design assumption of infinite gate resistance. The developed reference (average temperature coefficient, T_{C_AVG}, of 22.5 ppm/°C) overcomes direct tunneling by employing circuit techniques that minimize, balance, and cancel its effects. It is compared to a thick‐oxide voltage reference (T_{C_AVG} = 14.0 ppm/°C) as a means of demonstrating that ultra‐thin oxide MOSFETs can achieve performance similar to that of more expensive thick(er) oxide MOSFETs and that they can be used to design the analog component of a mixed‐signal system. The reference was investigated in a 65 nm CMOS technology with a nominal V_DD of 1 V and a physical oxide thickness of 1.25 nm. Copyright © 2013 John Wiley & Sons, Ltd.     

Numerical Simulation for Direct Tunneling Current in Poly-Si-Gate MOS Capacitors

We have numerically simulated gate tunneling current in MOS capacitors. Price has demonstrated that the Gamow formulation can be applied to analysis of the escape of electrons from channel into gate in MOSFETs [P.J. Price, Appl. Phys. Lett., 82, 2080 (2003)]. We have integrated the Gamow method into a Schrödinger-Poisson solver for metal-gate and poly-Si-gate n-type MOS capacitors. The numerical results of the tunneling current are then compared with experimental results.     

An analytic drain current model for long‐channel undoped gate stack surrounding‐gate MOSFETs including interface fixed charges

On the basis of the exact solution of Poisson's equation and Pao–Sah double integral for long‐channel bulk MOSFETs, a continuous and analytic drain current model for the undoped gate stack (GS) surrounding‐gate (SRG) metal–oxide–semiconductor field‐effect transistor (MOSFET) including positive or negative interface fixed charges near the drain junction is presented. Considering the effect of the interface fixed charges on the flat‐band voltage and the electron mobility, the model, which is expressed with the surface and body center potentials evaluated at the source and drain ends, describes the drain current from linear region to saturation region through a single continuous expression. It is found that the surface and body center potentials are increased/decreased in the case of positive/negative interface fixed charges, respectively, and the positive/negative interface fixed charges can decrease/increase the drain current. The model agrees well with the 3D numerical simulations and can be efficiently used to explore the effects of interface fixed charges on the drain current of the gate stack surrounding‐gate MOSFETs of the charge‐trapped memory device. Copyright © 2013 John Wiley & Sons, Ltd.     

Novel current‐source multilevel inverter driven by single gate drive power supply

This paper proposes a novel current‐source multilevel inverter, which is based on a current‐source half‐bridge topology. Multilevel inverters are effective for reducing harmonic distortion in the output voltage and the output current. However, the multilevel inverters require many gate drive power supplies to drive switching devices. The gate drive circuits using a bootstrap circuit and a pulse transformer can reduce the number of the gate drive power supplies, but the pulse width of the output PWM waveform is limited. Furthermore, high‐speed power switching devices are indispensable to create a high‐frequency power converter, but various problems, such as high‐frequency noise, arise due to the high dv/dt rate, especially in high‐side switching devices. The proposed current‐source multilevel inverter is composed of a common emitter topology for all switching devices. Therefore, it is possible to operate it with a single power supply for the gate drive circuit, which allows stabilizing the potential level of all the drive circuits. In this paper, the effectiveness of the proposed circuit is verified through experimental results. © 2008 Wiley Periodicals, Inc. Electr Eng Jpn, 166(2): 88–95, 2009; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20475     

Compact 2D modeling and drain current performance analysis of a work function engineered double gate tunnel field effect transistor

The ongoing trend of device dimension miniaturization is attributed to a large extent by the development of several non-conventional device structures among which tunneling field effect transistors (TFETs) have attracted significant research attention due to its inherent characteristics of carrier conduction by built-in tunneling mechanism which in turn mitigates various short channel effects (SCEs). In this work, we have, incorporated the innovative concept of work function engineering by continuously varying the mole fraction in a binary metal alloy gate electrode along the horizontal direction into a double gate tunneling field effect transistor (DG TFET), thereby presenting a new device structure, a work function engineered double gate tunneling field effect transistor (WFEDG TFET). We have presented an explicit analytical surface potential modeling of the proposed WFEDG TFET by the solving the 2-D Poisson’s equation. From the surface potential expression, the electric field has been derived which has been utilized to formulate the expression of drain current by performing rigorous integration on the band-to-band tunneling generation rate over the tunneling region. Based on this analytical modeling, an overall performance comparison of our proposed WFEDG TFET with its normal DG TFET counterpart has been presented in this work to establish the superiority of our proposed structure in terms of surface potential and drain current characteristics. Analytical results have been compared with SILVACO ATLAS device simulator results to validate our present model.     

Device circuit co‐design to reduce gate leakage current in VLSI logic circuits in nano regime

In this paper, nanoscale metal–oxide–semiconductor field‐effect transistor (MOSFET) device circuit co‐design is presented with an aim to reduce the gate leakage curren t in VLSI logic circuits. Firstly, gate leakage current is modeled through high‐k spacer underlap MOSFET (HSU MOSFET). In this HSU MOSFET, inversion layer is induced in underlap region by the gate fringing field through high‐k dielectric (high‐k) spacer, and this inversion layer in the underlap region acts as extended source/drain region. The analytical model results are compared with the two‐dimensional Sentaurus device simulation. Good agreement is obtained between the model and Sentaurus simulation. It is observed that modified HSU MOSFET had improved off current, subthreshold slope, and drain‐induced barrier lowering characteristics. Further, modified HSU MOSFET is also analyzed for gate leakage in generic logic circuits. Copyright © 2015 John Wiley & Sons, Ltd.     

An empirical I‐V model of tunneling real‐space transfer transistors for monostable–bistable transition logic element application

We proposed an empirical I‐V model to represent the negative differential resistance (NDR) regime of fabricated tunneling real‐space transfer transistors (TRSTTs). For TRSTTs to have great potential in monostable–bistable transition logic element (MOBILE) design, our model is able to accurately reproduce the NDR regime including gate‐source‐bias‐controlled NDR values and modulated peak to valley drain current ratios. The modeled I‐V curves, tranconductances, and NDRs with multiple gate biases are in good agreement with measured data. The key parameters in the model have clear physical meanings, and the value of these parameters is easy to be extracted directly from the test I‐V curves. The model is used to simulate a practical MOBILE, and excellent agreement between the simulated and measured data was found. Copyright © 2015 John Wiley & Sons, Ltd.     

Degradation of direct‐tunneling gate oxide under hot hole injection

The degradation of ultrathin SiO₂ films accompanied by the hole direct tunneling is investigated using a substrate hot hole (SHH) injection technique. Hot holes from the substrate as well as cold holes in the inversion layer are injected into the gate oxides in p‐channel MOSFETs with p⁺ poly‐Si gates, while the gate bias is kept low enough to avoid simultaneous electron injection from the gate. During the SHH stress, in contrast to the case of thicker oxide films, a strong correlation is observed between the oxide film degradation and the injected hole energy, whereas no degradation occurs due to the hole direct tunneling from the inversion layer. These experimental findings indicate the existence of threshold energy for trap creation process, which has been predicted by the theoretical study of hole‐injection‐induced structural transformation of oxygen vacancy in SiO₂. © 2002 Wiley Periodicals, Inc. Electr Eng Jpn, 140(4): 54–61, 2002; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.2008     

A 3D analytical modeling of tri-gate tunneling field-effect transistors

In this paper, a three-dimensional (3D) analytical solution of the electrostatic potential is derived for the tri-gate tunneling field-effect transistors (TG TFETs) based on the perimeter-weighted-sum approach. The model is derived by separating the device into a symmetric and an asymmetric double-gate (DG) TFETs and then solving the 2D Poisson’s equation for these structures. The subthreshold tunneling current expression is extracted by numerical integrating the band-to-band tunneling generation rate over the volume of the device. It is shown that the potential distributions, the electric field profile, and the tunneling current predicted by the analytical model are in close agreement with the 3D device simulation results without the need of fitting parameters. Additionally, the dependence of the tunneling current on the device parameters in terms of the gate oxide thickness, gate dielectric constant, channel length, and applied drain bias is investigated and also demonstrated its agreement with the device simulations.     

Modelling of source‐coupled logic gates

In this paper, the modelling of CMOS SCL gates is addressed. The topology both with and without output buffer is treated, and the noise margin as well as propagation delay performance are analytically derived, using standard BSIM3v3 model parameters. The propagation delay model of a single SCL gate is based on proper linearization of the circuit and the assumption of a single‐pole behaviour. To generalize the results obtained to cascaded gates, the effect of the input rise time and the loading effect of an SCL gate are discussed. The expressions obtained are simple enough to be used for pencil‐and‐paper evaluations and are helpful from the early design phases, as they relate SCL gates performance to design and process parameters, allowing the designer to gain an intuitive understanding of performance dependence on design parameters and technology. The model has been validated by comparison with extensive simulations using a 0.35‐µm CMOS process. The model agrees well with the simulated results, since in realistic cases the difference is less than 20% both for noise margin and delay. Therefore, the model proposed can be profitably used for pencil‐and‐paper evaluations and for computer‐based timing analysis of complex SCL circuits. Copyright © 2002 John Wiley & Sons, Ltd.     

Calculation of Direct Tunneling Current through Ultra-Thin Gate Oxides Using Complex Band Models For SiO2

We report the calculation of gate leakage currents through the ultra-thin gate oxides (2.6–3.4 nm) in MOSFETs. We simulate J-V characteristics for the direct tunneling of valence electrons and inversion layer holes, which are measured using a charge separation technique. A two-band model is employed to express the complex band structure of the gate oxide, and its validity is discussed by calculating the complex band structure of -cristobalite based on the second nearest neighbor sp ³ s* tight-binding scheme.     

An MTJ‐based non‐volatile flip‐flop for high‐performance SoC

The conventional magnetic tunneling junction (MTJ)‐based non‐volatile D flip‐flop (NVDFF) has a slow D‐Q delay and a tradeoff between its D‐Q delay and its sensing current. In addition, a sufficient write current cannot be obtained with the core device, since two MTJs exist in the write path and a write current degradation problem occurs due to the precharge transistors. The proposed MTJ‐based non‐volatile semidynamic flip‐flop (NVSDFF) has a semidynamic structure that ensures a fast D‐Q delay and separates the sensing circuit from the D‐Q signal path to reduce the sensing current without affecting the D‐Q delay. The proposed NVSDFF also provides a sufficient write current by merely using the core device, since only one MTJ exists in the write path. In addition, the head switch, which is added to remove the write current degradation problem, further reduces the sensing current. Thus, the proposed NVSDFF has a higher read disturbance margin than the previous NVDFF with an IO device. The HSPICE simulation results with the industry‐compatible 45 nm model parameter show that the D‐Q delay in the proposed NVSDFF is 50.5% of that of the previous NVDFF with an IO device, and the sensing current, 32.3%. In the proposed NVSDFF, the read disturbance margin is 15.9% larger than in the previous NVDFF with an IO device, and the area is 17.8% smaller. Copyright © 2012 John Wiley & Sons, Ltd.     

A power‐efficient current‐mode neural/muscular stimulator design for peripheral nerve prosthesis

This paper presents a 16‐channel power‐efficient neural/muscular stimulation integrated circuit for peripheral nerve prosthesis. First, the theoretical analysis is presented to show the power efficiency optimization in a stimulator. Moreover, a continuous‐time, biphasic exponential‐current‐waveform generation circuit is designed based on Taylor series approximation and implemented in the proposed stimulation chip to optimize the power efficiency. In the 16‐channel stimulator chip design, each channel of the stimulator consists of a current copier, an exponential current generator, an active charge‐balancing circuit, and a 24‐V output stage. Stimulation amplitude, pulse width, and frequency can be set and adjusted through an external field‐programmable gate array by sending serial commands. Finally, the proposed stimulator chip has been fabricated in a 0.18‐μm advanced complementary metal‐oxide‐semiconductor process with 24‐V laterally diffused metal oxide semiconductor option. The maximum stimulation power efficiency of 95.9% is achieved at the output stage with an electrode model of 10‐kΩ resistance and 100‐nF capacitance. Animal experiment results further demonstrate the power efficiency improvement and effectiveness of the stimulator.     

Drain current model of double‐gate MOSFETs considering both electrons and holes

We present a rigorously derived current solution for undoped double‐gate (DG) MOSFETs with two carriers, which is based on surface potentials. The third‐order Newton–Raphson (NR) method is used to solve the surface‐potential equations resulting from the application of the boundary conditions to the general Poisson solution, with an initial guess very close to the true solution. The results demonstrate surface‐potential solutions for DG MOSFETs with 2–7 iterations to achieve an accuracy of 10⁻¹⁵. The drain current model for two carriers is presented as a benchmark to test the accuracy of one‐carrier current approximation. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A novel empirical study of the two‐dimensional non‐linear drain‐current behaviour in sub‐micrometre MOS transistors

This paper presents a simple, quasi‐static, non‐linear (saturated mode) NMOS drain‐current model for Volterra‐series analysis. The model is based on a linear transconductance, a linear drain‐source conductance and a purely non‐linear drain‐source current generator. The drain‐current dependency on both drain‐source and gate‐source voltages is included. Model parameters are then extracted from direct numerical differentiation of DC I/V measurements performed on a 160 × 0.25 µm NMOS device. This paper presents the Volterra analysis of this model, including algebraic expressions for intercept points and output spectrum. The model has been verified by comparing measured two‐tone iIP₂ and iIP₃ with the corresponding model predictions over a wide range of bias points. The correspondence between the modelled and measured response is good. Copyright © 2005 John Wiley & Sons, Ltd.     

Gate leakage behavior of source/drain-to-gate non-overlapped MOSFET structure

In this paper, novel nanoscale MOSFET with Source/Drain-to-Gate Non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behavior of novel MOSFET structure has been investigated with help of compact analytical model and Sentaurus Simulation. Fringing gate electric field through the dielectric spacer induces inversion layer in the non-overlap region to act as extended source/drain region. It is found that optimal source/drain-to-gate non-overlapped and high-k spacer structure has reduced the gate leakage current to great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and drain induced barrier lowering characteristic with a slight degradation in source/drain series resistance and effective gate capacitance.     

Modeling and comparative analysis of DC characteristics of AlGaN/GaN HEMT and MOSHEMT devices

In this paper, a charge control model is developed for AlGaN/GaN High Electron Mobility Transistor (HEMT) and Metal Oxide Semiconductor High Electron Mobility Transistor (MOSHEMT) by considering the triangular potential well in the two‐dimensional electron gas (2DEG) and simulated with matlab . The obtained results from the developed model are compared with the experimental data for drain current, transconductance, gate capacitance and threshold voltage of both devices. The physics‐based models for 2DEG charge density, threshold voltage and gate capacitance have been developed. By using these developed models, the drain current for both linear and saturation modes is derived. The predicted threshold voltage with the variation of barrier thickness has been plotted. A positive threshold voltage can be obtained by decreasing the barrier thickness that builds up the foundation for enhancement mode MOSHEMTs. The predicted C‐V, I_d‐V_gs, I_d‐V_ds and transconductance characteristics show an excellent agreement with the experimental results from the literature and hence validate the developed model. The results clearly establish the potential of using AlGaN/GaN MOSHEMT approach for high power microwave and switching applications. Copyright © 2015 John Wiley & Sons, Ltd.     

Modeling the Inelastic Scattering Effect on the Resonant Tunneling Current

Resonant tunneling current with the inelastic scattering effect is modeled basing on the sequential tunneling approach. Simulations are performed for the case of a silicon double gate (n⁺)polySi/SiO₂/(i)Si/SiO₂/(n⁺)polySi structure