基于电源、地桥的电源网络布线后优化

随着集成电路规模的不断增大,电源网络的重要性日趋显著,电源网络的分布直接影响芯片的电压降(IR-drop)。一种布线后通过在空闲处插入电源桥和地桥的方法,可以在不增加芯片面积的情况下,改善IR-drop效应。实验结果表明在芯片布局利用率不高的情况下(70~75%),该方法可以使IR-drop得到明显的优化。     

静态时序分析在100M以太网卡控制芯片设计中的应用

本文介绍了用于数字集成电路设计验证的静态时序分析的基本原理，并以100M以太网卡控制芯片设计为例，具体描述了静态时序分析在该网卡控制芯片中的应用。     

ASIC综合后的静态验证方法的研究

介绍了基于深亚微米CMOS工艺ASIC电路设计流程中的静态验证方法。将这种验证方法与以往的劝态验证方法进行了比较，结果表明，前者比后者更加高效和准确。由此可以说明，静态验证完全可以取代劝态验证，并且静态验证比动态验证更加适合超大规模集成电路的发展趋势。     

深亚微米ASIC设计中的静态时序分析

随着集成电路的飞速发展,芯片能否进行全面成功的静态时序分析已成为其保证是否能正常工作的关键.描述了静态时序分析的原理,并以准同步数字系列(PDH)传输系统中16路E1 EoPDH(ethemet over PDH)转换器芯片为例,详细介绍了针对时钟定义、端口约束等关键问题的时序约束策略.结果表明,静态时序分析对该芯片的时序收敛进行了很好的验证.     

ASIC设计中的静态时序分析技术

随着工艺线宽的减小,时序问题开始主导集成电路设计。为了解决全芯片的互连延时,需要全芯片分析和优化。PrimeTime 是Synopsys 公司全芯片和门级静态时序分析工具。PrimeTime 用来分析大型同步数字专用集成电路。静态时序分析是一种彻底的分析、调试、验证设计的方法。     

CMOS集成电路静态功耗电流测试的重要性研究

目前,国内生产厂和用户针对CMOS集成电路静态电流的测试,仍基于现有的标准和产品规范。但是,采用这些测试方法来测试合格的器件,在使用过程中却发现了某些电路静态电流超差的现象。通过比较目前国内外的标准和规范所规定的方法,分析其存在的问题,并说明了静态电流测试的重要性。通过实验进行了验证说明,并提出了解决问题的建议。     

晶上系统电源分配网络建模及IR-drop研究

为预测和评估晶上系统电性能，提出了一种结合电磁和分析模拟的晶上系统电源分配网络（PDN）建模方法。该方法将PDN结构划分为单独组件，用电磁工具和公式计算提取无源电阻、电感、电容参数后，按组件位置组装成等效电路模型。通过与三维全波仿真自阻抗曲线比较对模型进行了验证，并基于模型，用ADS研究了模组位置排布、垂直互连密度、芯片功耗及去耦电容对电压降（IR-drop）的影响。结果表明：模型自阻抗曲线与三维全波仿真基本吻合；在一定范围内，合理排布模组位置、增加垂直互连密度、减少芯片功耗、使用较大去耦电容能降低IR-drop，为晶上系统设计和制造提供了参考。     

动圈式扬声器驱动力的数值分析研究

采用有限元静态磁路数值分析方法,分析动圈式扬声器单元的驱动力特性,并将分析结果与Klippel R&D系统的测试结果进行比较,验证了该方法的正确性。该方法不仅可替代有经验的电声工程师预估扬声器磁路特性,还可发现和验证产品设计与实际生产制造可能存在的差异。     

航天嵌入式软件静态测试方法研究

航天器在轨运行场景高度复杂,部分场景很难在地面实现真实状态下的动态验证.通过对近30年来航天软件在轨、在研以及第三方评测发现缺陷的分析与研究,提出了一套涵盖检查单法、变量分析法、中断访问冲突分析法、代码逻辑分析法、工具静态扫描分析法在内的以人工代码审查为主、工具静态扫描分析为辅的静态测试方案.检查单法侧重于检查项的对照...     

联用动态EMMI与FIB的集成电路失效分析

EMMI被广泛应用于集成电路的失效分析和机理判定。针对端口I-V特性曲线的异常现象,采用静态电流的发光效应对漏电点进行光发射定位。静态电流法无法全面测试集成电路内部逻辑单元,需要使用动态信号驱动集成电路,使内部失效部位能够产生光发射。对样品在动态失效工作状态进行光发射捕捉,再结合良品对比、电路原理图和版图分析等辅助手段进行故障假设,以定位失效点,最后利用FIB系统对电路进行剖面切割制样,找出物理损伤点。对砷化镓数字集成电路的不稳定软失效案例进行分析,动态EMMI法与FIB系统联用可成功应用于芯片内部金属化互连异常的失效分析,解决传统静态光发射法无法定位的技术难题。     

Decreased Effectiveness of On-Chip Decoupling Capacitance in High-Frequency Operation

This paper shows the decreased effectiveness of on-chip decoupling capacitance in high-frequency operation. On-chip decoupling capacitance is often used to decrease the variation of the propagation delay caused by power/ground noise, i.e., dynamic IR-drop and/or delta-I noise. However, it is shown in this paper that decoupling capacitance is only effective for coping with dynamic IR-drop if the recharging time between switching events is sufficient. In other words, the effectiveness of decoupling capacitance for dynamic IR-drop in high-frequency operation is less than that of a fully-charged decoupling capacitor. The recharging time and the effectiveness of a decoupling capacitor depend on the propagation delay of the average circuit path which is used to determine the total switching current of a given macro/chip and clock cycle time. If the propagation delay of the critical paths is approximately equal to that of the average circuit path, then it is shown in this paper that adding decoupling capacitance never improves the maximum frequency of the system due to dynamic IR-drop limitations. On the other hand, if the propagation delay of the critical paths is larger than that of the average circuit path, then the maximum frequency is improved by adding decoupling capacitance. In both cases, a new metric, called the apparent capacitance, can be used to help make correct decisions about decoupling capacitance planning.     

Compact physical IR-drop models for chip/package co-design of gigascale integration (GSI)

The supply voltage decrease and power density increase of future GSI chips demand accurate models for the IR-drop. Compact physical IR-drop models of on-chip power/ground distribution networks are derived for two generic types of packages. In the early stages of design, these models enable accurate estimates of all required power/ground grid interconnect dimensions and chip pad counts that are needed for power distribution. The models also quantify the tradeoff between on-chip interconnect dimensions and the number of I/O pads required for power distribution and therefore enable rigorous chip/package co-design. Comparison with SPICE simulations show less than 1% and 5% error for the wire-bond package and the flip-chip package, respectively.     

深亚微米IC物理设计流程中的串扰控制

信号完整性的设计收敛已经成为当前深亚微米集成电路物理设计流程中的关键问题。对信号完整性收敛产生不利影响的有三个因素：串扰、直流电压降和电迁移。其中影响最大的是串扰,串扰噪声会产生大量的时序违规、逻辑错误。主要关注基于串扰控制的物理设计方法,包括新的流程、各个设计阶段对串扰的分析及修正的方法,以达到快速的时序收敛。并且根据真实的设计实例,提出了几点有效的控制串扰的方法和对于信号完整性管理比较有价值的观点。     

Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits

Power-gating is one of the most promising and widely adopted solutions for controlling sub-threshold leakage power in nanometer circuits. Although single-cycle power-mode transition reduces wake-up latency, it develops large discharge current spikes, thereby causing IR-drop and inductive ground bounce for the neighboring circuit blocks, which can suffer from power plane integrity degradation. We propose a new reactivation solution that helps in controlling power supply fluctuations and achieving minimum reactivation times. Our structure limits the turn-on current below a given threshold through a sequential activation of the sleep transistors (STs), which are connected in parallel and sized using a novel optimal sizing algorithm. We also introduce a distributed physical implementation, which allows minimum layout disruption after ST insertion and minimizes routing congestion.     

Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing

At-speed scan testing, based on ATPG and ATE, is indispensable to guarantee timing-related test quality in the DSM era. However, at-speed scan testing may incur yield loss due to excessive IR-drop caused by high test (shift & capture) switching activity. This paper discusses the mechanism of circuit malfunction due to IR-drop, and summarizes general approaches to reducing switching activity, by which highlights the problem of current solutions, i.e. only reducing switching activity for one capture while the widely used at-speed scan testing based on the launch-off-capture scheme uses two captures. This paper then proposes a novel X-filling method, called double-capture (DC) X-filling, for generating test vectors with low and balanced capture switching activity for two captures. Applicable to dynamic & static compaction in any ATPG system, DC X-filling can reduce IR-drop, and thus yield loss, without any circuit/clock modification, timing/circuit overhead, fault coverage loss, and additional design effort.

一种基于AGA的RBF网络混合学习算法

基于目前RBF网络学习方法中的一些不足,提出了一种基于AGA的混合学习方法,即应用AGA对网络隐单元RBF个数和宽度σ同时优选,并将最佳隐单元数作为K-均值聚类数得到隐单元中心,隐层到输出层的权值由LS法确定。针对K-均值聚类算法对初始值敏感的问题,算法在最后阶段对其执行多次运算,由此选择最佳结果。仿真结果表明,该方法在大样本情况下,训练得到的网络在精度和结构上得到了良好的结合。     

天线组阵中基于循环相关的BPSK信号合成方法研究

深空网天线组阵中的干扰信号会严重影响信号的合成性能.针对全频谱合成方式下的SIMPLE合成算法,推导了干扰相关时合成信号的信噪比计算公式.分析了基于循环互相关的载波相位差估计方法,提出了BPSK信号循环自相关的相位差估计方法,并首次将两种方法应用到了天线组阵信号合成技术中.理论分析和仿真实验表明,在不增加额外计算量的基...     

Optimization Using a Modified Second-Order Approach With Evolutionary Enhancement

An optimization algorithm is presented which effectively combines the desirable characteristics of both gradient descent and evolutionary computation into a single robust algorithm. The method uses a population-based gradient approximation which allows it to recognize surface behavior on both large and small scales. By adjusting the population radius between iterations, the algorithm is able to escape local minima by shifting its focus onto global trends rather than local behavior. The algorithm is compared experimentally with existing methods over a set of relevant test cases, and each method is ranked on the basis of both reliability and rate of convergence. For each case, the algorithm is shown to outperform other methods in terms of both measures of performance, truly making it the best of both worlds.      

A combined algorithm for simulating fiber lasers based on the shooting and relaxation methods

The characteristics of the shooting and relaxation methods for solving the model of an ytterbium-doped double-clad fiber laser are discussed in detail by comparing their accuracies. Accordingly we propose a combined algorithm by taking advantage of the merits of both methods, which can automatically adjust initial trial values in calculations according to the desired requirement of accuracy. The results for verifying the efficiency and reliability of our proposed algorithm show that the level of accuracy and speed can completely satisfy the conventional requirements of numerical simulations.