低噪音放大器(LNA)多层板设计

介绍了低噪音放大器电路的多芯片技术设计与工艺分析.详细介绍了低噪音放大器多层布线版图以及每层的工艺实现步骤;通过对低噪音放大器电路的多层结构的设计与工艺实现,可以知道多层布线的发展是使电路小型化的一种途径,逐步提高电路的微型化的设计与制造的技术,最终实现电路微集成化的工作.     

Viterbi译码算法Soft Core IP的低功耗设计

介绍了Viterbi译码算法SoftCoreIP的一种低功耗实现方案,对其中的核心功能单元ACS(Adder_Compare_Select)提出了一种改进的设计结构,并介绍了电路时钟的优化技术及低功耗设计技术,经实验证明,确实达到了降低功耗、减小电路规模的设计目的。     

抗辐照SOI256kB只读存储器的ESD设计

ESD设计技术已成为业界提升SOI电路可靠性的一个瓶颈技术。文章介绍了一款具有抗辐照能力、基于SOI／CMOS工艺技术研制的容量为256kB只读存储器电路的ESD设计方案。结合电路特点详细分析了其ESD设计的难点,阐述了从工艺、器件和电路三个方面如何密切配合,进行SOI电路ESD设计的分析思路和解决方法。电路基于0．8...     

电气互联技术的现状及发展趋势

简要介绍了国外电气互联技术的现状，从电路可制造性设计、堆叠装配、FPC组装设计与工艺、PCB可制造性分析及虚拟设计技术、微波电路互联结构及绿色清洗技术等7个方面分析了电气互联先进制造技术的发展方向。     

某雷达发射机测试台监控电路的设计

介绍某雷达发射机测试台监控电路的设计。这一监控电路采用了模块化的设计思路,引入了可编程器件技术及光电隔离技术,从而提高了整个测试台的可靠性和可维护性。     

液晶电视屏接口电路的应用设计

随着高清电视显示技术的发展,液晶电视作为目前最优的显示终端得到了广泛的应用。本文主要从液晶电视屏接口电路构成的角度来介绍液晶电视屏接口电路的应用设计,包括时序控制接口电路的设计和背光接口电路的设计。     

一款深亚微米抗辐照芯片的设计与实现

设计了一款适用于航空航天领域的深亚微米抗辐照四路串口收发电路,重点介绍了逻辑设计、后端设计和抗辐照加固设计。电路采用0.18μm CMOS工艺加工,使用工艺加固、单元加固及电路设计加固等多层次加固技术,有效地提高了电路的抗辐照能力。     

应用邻域相关处理技术的激光报警控制显示电路

简要介绍了一种能提高激光报警精度的新技术－邻域相关处理技术。详细阐述了应用该技术研制的激光报警装置的控制显示电路。这种电路充分利用与电路、或电路、异或电路的功能,把一个较为复杂的判断电路,变成简单的逻辑组合电路。通过电路试验和整机对激光的接收试验,证明该电路满足设计要求,达到邻域相关处理技术的预期目标。     

小型化光纤陀螺关键技术研究

在航天和制导系统中,光纤陀螺的小型化日趋关键。主要从光纤陀螺的光路、电路和多轴复用等三方面介绍了其小型化技术。对于电路部分,介绍了我所设计的电路模块的设计原理;针对光路部分,主要进行光学集成器件的小型化关键技术——光学耦合技术的分析;在多轴复用技术方面,提出了目前常用的几种复用技术。这三方面技术为实现光纤陀螺的小型化提供了技术途径。     

TMS320C30数字信号处理器及其在舰载高频串行调解器中的应用

本文概述了Texas仪器公司第三代数字信号处理器TMS320C30的主要特点及技术性能，并从应用的角度，详细介绍了用TMS320C30实现串行MODEM中解调器的硬件结构、设计思想、及具体存贮器分配、读写时序、等待电路等。最后介绍了用TLC32044实现的A／D、D／A电路等外围接口电路的设计和调试技术。     

亚微米门阵列ASIC设计技术

本文主要论述亚微米CMOS门阵列的设计技术,包括建库技术,可测性设计技术、时钟设计技术、电源、地设计技术、电路结构优化、余量设计技术等,最后给出了应用实例。     

A CMOS gate array architecture for digital signal processingapplications

A new CMOS gate array architecture for digital signal processing (DSP) is presented. The basic cell structure takes into account the high degree of regularity of DSP datapaths. Therefore, it supports in particular the implementation of systolic arrays in connection with a pipelining scheme of one addition per half clock cycle. Together with a new gate array approach (macrocell design style), macrocells can be implemented efficiently on the new architecture. All DSP macrocells use dynamic transmission gate latches. Furthermore, the routing is done exclusively by cell abutment which results in short intercell routing. The macrocell design style is compared with the conventional gate array approach. In the common gate array approach, conventional gate array architectures are used together with conventional design equipment and layout strategies. The comparison shows a reduction in area and power consumption by a factor of 2.5 and 3.7, respectively. The efficiency increases by a factor of at least nine. These results were proved by analog circuit simulations and test chip measurements     

Design methodology of a 1.2-/spl mu/m double-level-metal CMOS technology

An advanced high-performance CMOS process and associated gate array and semicustom design approaches are described. Designed for rapid custom application, the process utilizes an n-well 1.2-/spl mu/m gate length and two layers of metal. The gate array has a density of 10000 2-input gates with typical delays of 1.25 ns, while the semicustom approach offers densities of 30000 gates with typical loaded delays of 1.0 ns.     

Design methodology of a 1.2-µm double-level-metal CMOS technology

An advanced high-performance CMOS process and associated gate array and semicustom design approaches are described. Designed for rapid custom application, the process utilizes an n-well 1.2-µm gate length and two layers of metal. The gate array has a density of 10000 2-input gates with typical delays of 1.25 ns while the semicustom approach offers densities of 30000 gates with typical loaded delays of 1.0 ns.     

A Scan-Testable 6000 Gate Array

In this paper hardware and software aspects of the AGA6000 are described. The AGA6000 is the first member of a new family of Philips gate arrays. It is a high-speed double-layer metal gate array in which special flip-flop rows are implemented. These flip-flop rows automatically insert a scan path in a gate array design. A scan-path test vector generation program guarantees a complete hardware testing of the devices with a 100-percent fault coverage for single stuck-at-one/stuck-at-zero faults. This gate array family was announced in [1].     

低功耗肖特基TTL300门阵列电路

本文对ST300门阵列电路作了简要介绍,描述了单元电路和I/O驱动电路的电路设计、版图设计和版图结构以及人工布线与计算机辅助设计制版系统相结合的布线技术。     

Hierarchical interconnection structures for field programmable gatearrays

Field programmable gate arrays (FPGA's) suffer from lower density and lower performance than conventional gate arrays. Hierarchical interconnection structures for field programmable gate arrays are proposed. They help overcome these problems. Logic blocks in a field programmable gate array are grouped into clusters. Clusters are then recursively grouped together. To obtain the optimal hierarchical structure with high performance and high density, various hierarchical structures with the same routability are discussed. The field programmable gate arrays with new architecture can be efficiently configured with existing computer aided design algorithms. The k-way min-cut algorithm is applicable to the placement step in the implementation. Global routing paths in a field programmable gate array can be obtained easily. The placement and global routing steps can be performed simultaneously. Experiments on benchmark circuits show that density and performance are significantly improved     

A 100-MHz 64-tap FIR digital filter in 0.8-μm BiCMOS gate array

A 64-tap FIR (finite impulse response) digital filter that has been designed using a newly developed filter compiler and fabricated in a 0.8-μm triple-level interconnect BiCMOS gate array technology is presented. The filter has been tested and is fully functional at a 100-MHz clock rate. These results are obtained by combining an optimized architecture and gate array floorplan with submicrometer BiCMOS technology. The filter occupies 49 mm², which is approximately two-thirds of the 100 K gate array core. The design uses an equivalent of 55 K gates (two-input NAND gates). The device input/output are 100 K emitter-coupled-logic (ECL) compatible     

A highly automated semi-custom approach for VLSI

The structured approach is aimed at optimizing the chip physical design while keeping design resources and time at a reasonable level. The logic is partitioned into data flow logic and control logic; a specialized physical structure has been defined to match the data flow logic structure and the gate array has been chosen for control logic implementation, both physical structures being customizable. A general purpose library and a set of design automation programs have been developed to allow fast physical design of the functional partitions according to the applications. A bipolar 16-bit slice microprocessor has been designed with this approach and built; compared to the widely used gate array chip implementation, it shows an improvement of 2 in gate density and 1.5 in power dissipation. The physical design of this 2000 gates chip took only two months.