From synchronous to GALS: A new architecture for FPGAs

The conflictual demand of faster and larger designs is increasingly difficult to answer by the advances of solid state technology alone. At some point, it is expected that designers and manufacturers will have to give up the traditional synchronous design methodology for a Globally Asynchronous Locally Synchronous (GALS) one. Such changes imply more synchronization constraints, but also more flexibility. Consequently, this paper proposes a novel Field-Programmable Gate Arrays (FPGA) architecture that is compatible with existing devices and that can also support GALS designs. The main objective is simple: the proposed architecture must appear unchanged for synchronous design, but it must also include a minimal amount of basic components to prevent metastability for efficient asynchronous communications. Thus, the paper presents the constraint equations required to implement such a circuit. It also presents a pausible clock generator application and simulation results for the proposed architecture. All results demonstrate that with a few additional customized circuits, a standard FPGA cell can become appropriate for GALS methodologies.     

High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors

Chip multiprocessors with globally asynchronous locally synchronous (GALS) clocking styles are promising candidates for processing computationally-intensive and energy-constrained workloads. The GALS methodology simplifies clock tree design, provides opportunities to use clock and voltage scaling jointly in system submodules to achieve high energy efficiencies, and can also result in easily scalable clocking systems. However, its use typically also introduces performance penalties due to additional communication latency between clock domains. We show that GALS chip multiprocessors (CMPs) with large inter-processor first-inputs–first-outputs (FIFOs) buffers can inherently hide much of the GALS performance penalty while executing applications that have been mapped with few communication loops. In fact, the penalty can be driven to zero with sufficiently large FIFOs and the removal of multiple-loop communication links. We present an example mesh-connected GALS chip multiprocessor and show it has a less than 1% performance (throughput) reduction on average compared to the corresponding synchronous system for many DSP workloads. Furthermore, adaptive clock and voltage scaling for each processor provides an approximately 40% power savings without any performance reduction. These results compare favorably with the GALS uniprocessor, which compared to the corresponding synchronous uniprocessor, has a reported greater than 10% performance (throughput) reduction and an energy savings of approximately 25% using dynamic clock and voltage scaling for many general purpose applications.      

High Rate Data Synchronization in GALS SoCs

Globally asynchronous, locally synchronous (GALS) systems-on-chip (SoCs) may be prone to synchronization failures if the delay of their locally-generated clock tree is not considered. This paper presents an in-depth analysis of the problem and proposes a novel solution. The problem is analyzed considering the magnitude of clock tree delays, the cycle times of the GALS module, and the complexity of the asynchronous interface controllers using a timed signal transition graph (STG) approach. In some cases, the problem can be solved by extracting all the delays and verifying whether the system is susceptible to metastability. In other cases, when high data bandwidth is not required, matched-delay asynchronous ports may be employed. A novel architecture for synchronizing inter-modular communications in GALS, based on locally delayed latching (LDL), is described. LDL synchronization does not require pausable clocking, is insensitive to clock tree delays, and supports high data rates. It replaces complex global timing constraints with simpler localized ones. Three different LDL ports are presented. The risk of metastability in the synchronizer is analyzed in a technology-independent manner     

一种基于标准逻辑单元的GALS异步封装电路

基于点对点GALS模型,给出了异步封装电路的信号状态转换图(STG),基于Petrify设计了一种基于标准逻辑单元的GALS异步封装电路,包括同步/异步接口电路、具有分频及暂停功能的局部时钟等设计.由于所设计的异步封装电路具有不存在延时器件、没有使用特殊的异步逻辑单元等特点,所以论文基于两个同步计数器实现了GALS点对点模型进行仿真和FPGA验证,结果显示了整个异步封装及其GALS系统性能的正确性.     

A new contactless smart card IC using an on-chip antenna and anasynchronous microcontroller

This paper describes a new generation of contactless smart card chip which integrates an on-chip coil connected to a power reception system and an emitter/receiver module compatible with the ISO 14443 standard, together with an asynchronous quasi-delay insensitive (QDI) 8-bit microcontroller. Beyond the contactless smart card application field, this new chip demonstrates that system-on-chip integrating power reception and management, radio-frequency communication, and signal processing is feasible. It associates analog/digital parts as well as synchronous/asynchronous logics and has been fabricated in a CMOS six metal layers 0.25-μm technology from STMicroelectronics     

片上网络GALS接口设计

本文提出了一种基于握手协议的GALS接口设计方法。该接口采用异步FIFO作为输入缓冲区,有效降低了数据传输延迟;采用环形缓冲的概念来管理缓冲区,使接口具有了可扩展性。FPGA验证结果表明,该接口保证了适配单元与网络路由之间完成准确的异步传输,4通道的接口共占用了405个ALUT（Adaptive Look-Up Table）和支持211 MHz的时钟频率。     

短波同步正交跳频网设计

常规短波跳频网由于自身的特性,常采用异步方式组网,限制了抗干扰能力的充分发挥。同步基准为设计性能优良的短波同步正交跳频网提供了条件。同步组网各跳频网络具有统一的时间基准,而异步组网时各跳频网络没有。为达到在任一瞬间,均不会发生频率碰撞,在总结常规跳频网络的特性的基础上,提出了基于同步基准的短波同步正交跳频组网的设计方法,并分析了短波同步正交跳频网的特性。     

有线数字电视前端系统的同步研究和实现

随着有线电视数字化的全面推行，时钟同步问题成为前端播出的一项新的课题和挑战。本文对数字电视前端各种同步方式进行了研究和比较，阐述各自特点和局限性，建设了一套高精度、安全可靠、可扩展的时钟同步系统。     

Synchronization in digital system design

A unified framework and terminology is presented for synchronization design in digital systems, borrowing techniques and terminologies from digital system and digital communication design disciplines. The throughput of synchronous and asynchronous interconnect is compared, emphasizing how it is affected by interconnect delay. A discussion is presented of opportunities to apply principles long used in digital communications to the design of digital systems, with the goal of reducing the dependence on interconnect delay     

Core与总线系统的异步通信接口设计

文章基于GALS（Globally Asynchronous Locally Synchronous）设计理念，提出一个Core的异步接口设计模型：门控时钟停Core机制、握手机制、电平转脉冲逻辑等构成的异步控制信号处理模型：异步FIFO和双FIFO结构构成的异步数据处理模型。此结构允许Core和总线系统在完全异步的时钟域上工作。FPGA验证结果表明．该模型能正确地实现两者问的信号同步，并能满足具体应用的带宽需求。     

Scan Test Strategy for Asynchronous-Synchronous Interfaces

In the coming years, the well-known synchronous design style will not be able to keep pace with the increase speed and capabilities of integration of advanced processes. New design paradigms, like core reuse of the already designed synchronous modules and asynchronous designs, are considered in order to cope with the ever increasing complexity. The future SoCs will contain multiple synchronous and asynchronous cores. Asynchronous design will become more and more common among digital designers, while synchronous-asynchronous interactions will emerge as a key issue in the future SoC designs.This paper will present test strategies for 2-phase asynchronous-synchronous interfaces and vice versa. It will be shown how test vectors can be automatically generated using commercially available ATPG tools. The generated ATPG vectors will be able to test all stuck-at-faults within the asynchronous-synchronous interfaces.     

新型FSK电力线收发器ST7540及其应用

介绍了新型单片式FSK电力线收发器ST7540的特点及工作原理,并给出基于ST7540的应用电路。ST7540采用半双工同步/异步FSK通信方式,专为低压电力线数据传输而设计,较好地克服了低压电力线载波传输中的技术问题,可广泛应用于空间限制,成本敏感的家庭和建筑物自动化以及遥控监视系统。     

Designing asynchronous standby circuits for a low-power pager

We have designed asynchronous standby circuits for a pager decoder which dissipate four times less power and are 40% larger in size than synchronous designs. For the total pager unit this means a 37% reduction in power dissipation for nearly no additional area. The decoded chip, which apart from the standby circuits is completely synchronous, has been fabricated and was first-time-right. Two problems had to be solved to incorporate asynchronous subcircuits in a synchronous environment: synchronization and testing. A synchronization scheme is described that allows a free intermixing of asynchronous and synchronous modules and a test strategy is proposed in which the scan test facilities in the synchronous environment are used to test the asynchronous modules. One function is prevalent in the standby circuits, namely counting. In an appendix we present the asynchronous design of a so-called loadable counter whose power consumption does not depend on its size     

Modeling logical and temporal synchronization in hypermedia systems

The paper introduces a unified formal model for the complete and accurate specification of both temporal and logical (i.e., link) synchronization within hypermedia distributed and weakly synchronous systems. This new model extends time Petri nets with hierarchical design capabilities and new firing rules. These new firing rules enlighten the notion of hypermedia synchronization through powerful combinations of temporal and logical synchronization. Moreover, the proposed model offers an easy and concise modeling technique of asynchronous events in hypermedia systems     

Ultrafast time-domain technology and its application in all-optical signal processing

In this paper, we review recent advances in ultrafast optical time-domain technology with emphasis on the use in optical packet switching. In this respect, several key building blocks, including high-rate laser sources applicable to any time-division-multiplexing (TDM) application, optical logic circuits for bitwise processing, and clock-recovery circuits for timing synchronization with both synchronous and asynchronous data traffic, are described in detail. The circuits take advantage of the ultrafast nonlinear transfer function of semiconductor-based devices to operate successfully at rates beyond 10 Gb/s. We also demonstrate two more complex circuits-a header extraction unit and an exchange-bypass switch-operating at 10 Gb/s. These two units are key blocks for any general-purpose packet routing/switching application. Finally, we discuss the system perspective of all these modules and propose their possible incorporation in a packet switch architecture to provide low-level but high-speed functionalities. The goal is to perform as many operations as possible in the optical domain to increase node throughput and to alleviate the network from unwanted and expensive optical-electrical-optical conversions.     

DSA techniques for fast and robust acquisition of DS/CDMA scrambling codes

This article introduces the key concepts, organization, and operations of distributed sample-based acquisition (DSA) systems, which have previously been introduced for fast and robust synchronization of the long-period scrambling codes in DS/CDMA environments. In DSA systems, the transmitter samples and sends the state of its main sequence generator, or main shift register generator (SRG), in a distributed manner over the short-period igniter sequence, and the receiver detects and applies the state samples to correct the state of its main SRG, thereby acquiring SRG synchronization after a round of state reception. Acquisition performance of DSA techniques is extremely fast and robust compared to typical correlation-based acquisition techniques of comparable complexity. This article discusses the operation and performance of DSA techniques in the DS/CDMA communication environment as well as their applications to intercell synchronous and asynchronous cellular systems.     

Self-timing and vector processing in RSFQ digital circuittechnology

As the operating speed of rapid single flux quantum (RSFQ) integrated circuits and systems increases, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, the authors present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. They also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High-speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists of two self-timed shift registers and an on-chip 8-28-GHz clock generator     

跳频卫星通信同步技术研究

跳频同步是跳频通信技术的关键.考虑到抗干扰的需要,将跳频体制引入到卫星通信中.比较常规跳频同步实现方法的优缺点,根据设备低复杂度以及同步捕获时间短的要求,将同步头+ TOD的同步方法引入到跳频卫星通信系统中,研究了同步序列格式,同步头的结构,同步频率的算法,设计了初始同步的方案.     

Gigabit networking research at Bellcore

A communication architecture appropriate for gigabit networks, the multimedia end-to-end communication architecture (MECA), is described. MECA provides multimedia applications with the service they require in a single communication system. MECA encompasses the network, host-network interface, and associated protocols. The architectural characteristics of MECA are compared with those of existing communication systems and the TP++ transport protocol used by MECA is compared to existing transport protocols. Three host-network interfaces built for AURORA, a five-gigabit testbed network that includes an experimental asynchronous transfer mode (ATM) network running over a synchronous optical network (SONET), are described. The Sunshine ATM switch that supports MECA using a scalable Batcher-Banyan switching fabric and highly programmable port controllers is discussed     

GALDS: a complete framework for designing multiclock ASICs and SoCs

A Globally Asynchronous, Locally Synchronous (GALS) system with dynamic voltage and frequency scaling can use the slowest frequency possible to accomplish a task with minimal power consumption. With the mechanism for implementing dynamic voltage scaling at each synchronous domain left up to the designer, our Globally Asynchronous, Locally Dynamic System (GALDS) provides a top-down, system-level means to maximize power reduction in an integrated circuit and facilitate system-on-a-chip (SoC) design. Our solution includes three distinct components: a novel bidirectional asynchronous FIFO to communicate between independently clocked synchronous blocks , an all-digital dynamic clock generator to quickly and glitchlessly switch between frequencies and a digitally controlled oscillator to generate the global fixed frequency clocks required by the all-digital dynamic clock generator. In addition to being capable of reducing power consumption when combined with dynamic voltage scaling, a GALDS design benefits from numerous other advantages such as simplified clock distribution, high performance operation and faster time-to-market through the modular nature of the architecture.