Forward error correction based on block turbo code with 3-bit soft decision for 10-Gb/s optical communication systems

The first experimental demonstration of a forward error correction (FEC) for 10-Gb/s optical communication systems based on a block turbo code (BTC) is reported. Key algorithms, e.g., extrinsic information, log-likelihood ratio, and soft decision reliability, are optimized to improve the correction capability. The optimum thresholds for a 3-bit soft decider are investigated analytically. A theoretical prediction is verified by experiment using a novel 3-bit soft decision large scale integrated circuit (LSI) and a BTC encoder/decoder evaluation circuit incorporating a 10-Gb/s return-to-zero on-off keying optical transceiver. A net coding gain of 10.1 dB was achieved with only 24.6% redundancy for an input bit error rate of 1.98/spl times/10/sup -2/. This is only 0.9 dB away from the Shannon limit for a code rate of 0.8 for a binary symmetric channel. Superior tolerance to error bursts given by the adoption of 64-depth interleaving is demonstrated. The ability of the proposed FEC system to achieve a receiver sensitivity of seven photons per information bit when combined with return-to-zero differential phase-shift keying modulation is demonstrated.     

基于扩展格雷码的高速数据传输加固设计

星载雷达系统由于其工作环境和高速信号传输特性,在数据传输过程中无可避免的会因为各种干扰而出现误码.为了加固高速信号抵抗传输过程中的误码干扰,采用能纠错3位的完备码格雷码,经添加一位奇偶校验位扩展得到的扩展格雷码设计了编译码电路.根据扩展格雷码的生成矩阵和校验矩阵,以及一种硬判决译码算法,基于FPGA实现了扩展格雷码的并行信息编译码器以及串行信息编译码器.行为仿真结果表明该扩展格雷码编码器能正常实现连续编码,同时在模拟星载雷达系统因为干扰而出现的误码时,该译码器能自我纠正编码分组内3个以内的任意误码组合,达到了数据传输加固的目的.     

一种交织汉明码编译码器设计及其FPGA实现

随着信号传输速度的提高,高速信号抗干扰能力也越来越低,人们对信号可靠性有了更高的要求.为了抵抗高速信号在传输过程中因为各种干扰而产生误码,人们提出了纠错编码理论.其中汉明码是最早提出的一类纠错编码,具有译码电路简单,译码延时小的优点,但是其只能纠正一位随机错误.为了提高汉明码的纠错能力,结合其译码优点,利用交织的方式设计了一种交织汉明码.根据循环汉明码的生成多项式,设计了并行输出的汉明码编码器和具有双译码电路的译码器,并利用移位寄存器设计了交织器和解交织器,构成了交织汉明码编译码电路.基于FPGA实现该交织汉明码编译码器,行为仿真结果表明,该交织汉明码大大提高了汉明码的纠错能力.     

21位光电编码器数据处理系统

为了减少绝对式光电编码器的体积,增强编码器的数据处理能力,设计了一种21位光电编码器数据处理系统。该编码器码盘采用矩阵码盘形式,分为粗码和精码,粗码12位,其中一位校正码道,精码为一周4096对线。数据处理部分采用DSP芯片和AD转换器相结合,将所有码道的信息全部输入到AD转换器,DSP根据AD转换器的值将原始信号转换为21位编码器的角度信息并显示。该编码器外径为160mm,采用自准直仪和正17面体对该编码器精度进行检测,精度均方差为1.09s。     

面积优先的CCSDS Turbo码编译码器的设计与实现

本文设计出符合CCSDS标准的Turbo编译码器,包含伪随机序列模块与帧同步模块.在实现编码器时针对标准要求,对伪随机化处理及其恢复和帧同步检测提出了解决方案;而在相应的译码器设计中,本文权衡硬件实现复杂度与处理时延等因素,优先考虑面积因素提高元件的重复利用率和降低复杂度,并阐述了其实现过程.最后基于Verilog HDL设计出RTL级14位固点数据的Turbo编译码器以及仿真验证平台,与用MATLAB语言设计的相同指标的浮点数据译码器进行性能比较,得到设计验证.     

基于FPGA的IRIG-B(DC)解码编码器设计

针对机载测试系统以IRIG-B（DC）码作为整个系统的时间源,提出一种基于FPGA的解码编码器设计。该设计采用FPGA为主控制器,实现IRIG-B（DC）码的解码、秒脉冲生成、IRIG-B码编码等功能,当外部IRIG-B码输入中断时,可按系统时间产生IRIG-B码输出。主要阐述了IRIG-B（DC）码的格式,详细介绍了IRIG-B（DC）码解码编码器的软硬件设计,在实验室搭建测试环境对该设计进行了测试验证,结果表明该设计能够稳定可靠运行。     

基于CPLD的Manchester编码器与解码器

曼彻斯特(Manchester)编码作为一种数据传输方式,在工业控制领域应用广泛。但其编码和解码基于锁相环实现,电路复杂。现介绍一种基于CPLD实现的Manchester编码器与解码器。实践证明,该设计易于与现有系统集成,实现方便,性能可靠。     

CNN‐based architecture for real‐time object‐oriented video coding applications

This paper presents a new CNN‐based architecture for real‐time video coding applications. The proposed approach, by exploiting object‐oriented CNN algorithms and MPEG encoding capabilities, enables low bit‐rate encoder/decoder to be designed. Simulation results using Claire video sequence show the effectiveness of the proposed scheme. Copyright © 2005 John Wiley & Sons, Ltd.     

New algorithms for preserving edges in low‐bit‐rate wavelet‐based image compression

With the growing importance of low‐bandwidth applications such as wireless access to the Internet, images are often sent or received at low bit rates. At these bit rates, images suffer from significant distortion and artifacts, making it difficult for those viewing the images to understand them. In this paper, we present two progressive compression algorithms that focus on preserving the clarity of important image features, such as edges, at compression ratios of 100:1 and higher. The first algorithm transmits a standard SPIHT bit stream and then detects the location of edges in the compressed image. The decoder applies a linear edge‐enhancement procedure to improve the clarity of the encoded edges. The second algorithm extracts the locations of straight‐line edges in the image at the encoder, and the decoder applies edge extraction, combination, and a linear edge‐enhancement procedure to improve the clarity of the edges. With both algorithms, features in the images that may be important for recognition are well preserved, even at very low bit rates. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

石油测井中纠错编码的设计及其FPGA实现

针对石油测井中可靠性的要求,本文提出了一种纠错编码的设计方案。该设计采用基于乘积码的编码方案,外码和内码采用的都是BCH码。并详细介绍了用FPGA实现该编码方案的方法,包括BCH码的编译码和交织编码。     

Resolution Improvement of All-Optical Analog-to-Digital Conversion Employing Self-frequency Shift and Self-Phase-Modulation-Induced Spectral Compression

We demonstrate and investigate resolution improvement of optical quantization using soliton self-frequency shift (SSFS) and optical coding using optical interconnection for an all-optical analog-to-digital conversion (ADC). Incorporating spectral compression into the optical quantization allows us to improve the resolution bit according to the spectral compression ratio with keeping its throughput. The proposed scheme consists of optical quantization using SSFS and self-phase modulation (SPM) induced spectral compression and optical coding using optical interconnection based on a binary conversion table. In optical quantization, the powers of input signals are discriminated by referring to the center wavelengths after the SSFS. The compression of the spectral width allows us to emphasize the differences of their center wavelengths, and improve the number of resolution bits. Optical interconnection generates a bit-parallel binary code by appropriate allocation of a level identification signal, which is provided as a result of optical quantization. Experimental results show the eight periods transfer function, that means, the four read-out bit operation of the proposed scheme in binary code. Simulation results indicate that the proposed optical quantization has the potential of 100 GS/s and 4-b resolution, which could surpass the electrical bandwidth limitations.     

基于FPGA的卷积码的编/译码器设计

卷积码作为通信系统中重要的编码方式,以其良好的编码性能,合理的译码方法,被广泛应用。本文在介绍卷积码原理的基础上,详细阐述了基于FPGA的卷积码的编/译码器的设计。值得一提的是,卷积码的译码采用维特比译码算法,利用了状态路径度量计算、保存路径转移过程和回溯译码等方法,在硬件实现上能有效地减少存储量、降低功耗,提高整个编/译码器的性能。最后进行了模拟仿真,结果显示编译码的效果比较理想,达到了设计的目的。     

基于FPGA实现HD-15530编译码器

现场可编程门阵列(FPGA)具有集成度高,体积小的特点,在文中介绍用FPGA实现曼彻斯特编译码器(HD-15530)的设计方案,并通过时序仿真的验证,证明方案合理。用FPGA来实现HD-15530功能,能够降低系统的功耗,提高系统的可靠性。     

Monolithically integrated InP-based photonic chip development for O-CDMA systems

This work discusses photonic integration efforts toward developing an InP-based monolithically integrated photonic chip for optical code-division multiple-access (O-CDMA) system applications. The chip design includes the colliding pulsed mode (CPM) locked laser, the Mach-Zehnder interferometer-based threshold detector (MZI), and the monolithic O-CDMA encoder/decoder chip based on array-waveguide-gratings and phase modulator arrays. The compact 4 /spl times/ 1 cm monolithic chip can replace a complex and large O-CDMA setup based on bulk optics. The integration technique involves active-passive integration using dry etching, metal organic chemical vapor deposition growth, and lateral hydride vapor phase epitaxy regrowth technologies. The fabricated CPM showed stable 1.54 ps modelocked laser output, the MZI showed excellent O-CDMA threshold detection, and the O-CDMA encoder showed Walsh-code O-CDMA encoding. Further, the fabricated devices showed excellent planarity, which accelerate our progress toward monolithic integration of O-CDMA systems.     

无线智能家居通信系统抗干扰编解码器的实现

无线智能家居通信系统数据传输过程中,不可避免地会受到室内障碍物、窜内同频率通信设备等干扰因素的影响,造成数据通信可靠性下降.根据无线智能家居通信系统及MCU接口特点,设计了一套基于16 bit MCU接口的(15,11)循环汉明码编解码硬件实现方案,对有效降低误码率、提高系统通信效率具有积极意义.     

无线激光通信中差错控制实验研究

微波通信灵活方便,光纤通信码速率高,无线激光通信兼具微波和光纤通信的优势,但受大气环境的影响不容忽视,差错控制是克服无线激光通信环境影响的一个有效方法。常见的纠错码有RS码、Turbo码和Ldpc码,分别将RS（15,9）码、RS（30,10）码,码长为128码率为1/2的LDPC码、交织长度为64码率为1/3的Turbo码引入无线激光通信系统中,按照设计的实验方案,进行一年多时间的实际测量,对几种前向纠错码的性能进行了比较,实验结果表明：RS（30,10）码纠错能力最强,Turbo码纠错性能稍逊于RS（30,10）码。RS（15,9）码与码长为128,码率1/2的LDPC码的纠错性能相差不大。在不同的雨天环境中,通过采用前向纠错码,可以将误码率从10^-4降低到10^-6以下;在雪天,可以将误码率从10^-3降低到10^-5以下;在大雾条件下,可以将误码率从10^-3降低到10^-5以下;在一般晴好天气下,可以使误码率降低到10-9以下。     

星载高精度小型多圈绝对式编码器设计

为了满足星载相机中调焦相机电机转动精度和圈数记忆要求,设计了小型多圈绝对式光电编码器。根据星载相机的精度要求,对1级绝对式光学码盘进行了小型化设计;根据电机转动的计数要求,设计了2级绝对式矩阵码盘计数系统;最后,对设计的小型多圈绝对式光电编码器进行了精度检测。小型多圈星载绝对式光电编码器外形尺寸为直径40mm×50mm、重量为200g、分辨力为40″、精度±100",圈数16圈。本编码器能实现相机中电机转动圈数记忆功能,且体积小、精度高,可满足星载相机的要求。     

一种适合于伺服应用的新型绝对式光电编码器

文章介绍了一种适合于伺服应用的新型绝对式光电编码器。该编码器的盘片采用循环移位二进制编码,在显著减小体积的同时也降低了成本。同时针对伺服系统中控制器无电时编码器由电池供电的工况,采用磁性传感单元作为电池供电时的位置检测机构,降低了耗电量,显著延长了电池的更换周期,便于使用与维护。     

一种新型可编程多功能多媒体处理平台的研究与实现

本文旨在提出一种可编程多功能多媒体处理平台方案.首先深入了解基于TMS320DM642媒体处理器的多功能多媒体处理平台硬件系统的设计原理,然后深刻理解算法并针对平台优化算法,最后通过修改与硬件相关的软件,将软件系统移植到DM642平台卜.在该平台上实现了标准清晰度数字电视信源解码器(含TS流解复用、D1分辨率的MPEG-2视频解码和MPEG-2音频解码)、MPEG-4视频解码器(D1分辨率)和基于H.264标准的网络视频监控系统(CIF图像实时解码和QCIF图像实时编码).     

磁编码器算法分析与研究

磁编码器使用线性霍尔元件作为主体,结构简单,易实现微型化,适应恶劣环境能力强.实际应用中,磁编码器的分辨率和精度除受制于线性霍尔元件的精度外,也与AD采样精度、磁编码器算法有密切关系.在分析比较磁编码器的几种实现算法的基础上,给出了高精度的实现方案,在使用10 bit AD的基础上,可达到超过0.1 °的分辨率.