Characterization of $m$-Sequences of Lengths $2^{2k}-1$ and $2^{k}-1$ With Three-Valued Cross Correlation

Considered is the distribution of the cross correlation between in-sequences of length 2^2k -1, where m = 2k, and m-sequences of shorter length 2^k -1. New pairs of m -sequences with three-valued cross correlation are found and the complete correlation distribution is determined. Finally, we conjecture that there are no more cases with a three-valued cross correlation apart from the ones proven here.     

A Decorrelating Design-for-Digital-Testability Scheme for $Sigma{-}Delta$ Modulators

This paper presents a novel decorrelating design-for-digital-testability $({rm D}^{3}{rm T})$ scheme for $Sigma{-}Delta$ modulators to enhance the test accuracy of using digital stimuli. The input switched-capacitor network of the modulator under test is reconfigured as two or more subdigital-to-charge converters in the test mode. By properly designing the digital stimuli, the shaped noise power of the digital stimulus can be effectively attenuated. As a result, the shaped noise correlation as well as the modulator overload issues are alleviated, thus improving the test accuracy. A second-order $Sigma{-}Delta$ modulator design is used as an example to demonstrate the effectiveness of the proposed scheme. The behavioral simulation results showed that, when the signal level of the stimulus tone is less than $-$5 dBFS, the signal-to-noise ratios obtained by the digital stimuli are inferior to those obtained by their analog counterparts of no more than 1.8 dB. Circuit-simulation results also demonstrated that the ${rm D}^{3}{rm T}$ scheme has the potential to test moderate nonlinearity. The proposed ${rm D}^{3}{rm T}$ scheme has the advantages of achieving high test accuracy, low circuit overhead, high fault observability, and the capability of conducting at-speed tests.      

Design Considerations for Cascade $Delta Sigma $ ADC's

This brief discusses the design tradeoffs for cascaded delta-sigma (DeltaSigma) analog-to-digital converters. Increasing the order of the first loop allows a tradeoff between aggressive noise shaping and moderate operational transconductance amplifier (OTA) specifications. A comparison between fourth-order topologies indicates that for a cascade 3-1 topology, 55-dB OTA gain is sufficient for 96-dB signal-to-noise-distortion ratio while 5% coefficient mismatch results in less than 4-dB degradation. Dependent on the ratio between the power consumption of the digital recombination and decimation filter and that of the analog loop filter, the optimal topology can be chosen. A cascade 3-1 converter is most efficient when this ratio lies between 0.54 and 0.97. A design in a 65-nm CMOS technology demonstrates the performance of a cascade 3-1 converter.     

Enhancement-Mode Metamorphic HEMT on GaAs Substrate With 2 S/mm $g_{m}$ and 490 GHz $f_{T}$

This letter presents the results of an enhancement mode metamorphic high-electron-mobility transistor device on a GaAs substrate with a 70% indium composition channel. A 35-nm gate length device exhibits a 490-GHz current gain cutoff frequency (f_T), a transconductance (g_m) of 2 S/mm, a threshold voltage (V_th) of 0.11 V (enhancement mode) and a low on- resistance of 0.37 Omega mm. These attributes make the device well- suited for millimeter-wave circuit applications.     

Impacts of $hbox{N}_{2}$ and $hbox{NH}_{3}$ Plasma Surface Treatments on High-Performance LTPS-TFT With High-$kappa$ Gate Dielectric

Low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) with high- $kappa$ gate dielectrics and plasma surface treatments are demonstrated for the first time. Significant field-effect mobility $mu_{rm FE}$ improvements of $sim$86.0% and 112.5% are observed for LTPS-TFTs with $hbox{HfO}_{2}$ gate dielectric after $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments, respectively. In addition, the $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments can also reduce surface roughness scattering to enhance the field-effect mobility $mu_{rm FE}$ at high gate bias voltage $V_{G}$, resulting in 217.0% and 219.6% improvements in driving current, respectively. As a result, high-performance LTPS-TFT with low threshold voltage $V_{rm TH} sim hbox{0.33} hbox{V}$, excellent subthreshold swing S.S. $sim$0.156 V/decade, and high field-effect mobility $mu_{rm FE} sim hbox{62.02} hbox{cm}^{2}/hbox{V} cdot hbox{s}$ would be suitable for the application of system-on-panel.      

A Comparative NBTI Study of $hbox{HfO}_{2}$, $hbox{HfSiO}_{x}$, and SiON p-MOSFETs Using UF-OTF $I_{rm DLIN}$ Technique

The time, temperature, and oxide-field dependence of negative-bias temperature instability is studied in $hbox{HfO}_{2}/hbox{TiN}$, $ hbox{HfSiO}_{x}/hbox{TiN}$, and SiON/poly-Si p-MOSFETs using ultrafast on-the-fly $I_{rm DLIN}$ technique capable of providing measured degradation from very short (approximately microseconds) to long stress time. Similar to rapid thermal nitrided oxide (RTNO) SiON, $hbox{HfO}_{2}$ devices show very high temperature-independent degradation at short (submilliseconds) stress time, not observed for plasma nitrided oxide (PNO) SiON and $hbox{HfSiO}_{x}$ devices. $hbox{HfSiO}_{x}$ shows lower overall degradation, higher long-time power-law exponent, field acceleration, and temperature activation as compared to $hbox{HfO}_{2}$, which are similar to the differences between PNO and RTNO SiON devices, respectively. The difference between $ hbox{HfSiO}_{x}$ and $hbox{HfO}_{2}$ can be attributed to differences in N density in the $hbox{SiO}_{2}$ IL of these devices.      

High-Performance $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ -Channel MOSFETs With High-$kappa$ Gate Dielectrics and $alpha$-Si Passivation

Long and short buried-channel $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ MOSFETs with and without $alpha$-Si passivation are demonstrated. Devices with $alpha$-Si passivation show much higher transconductance and an effective peak mobility of 3810 $hbox{cm}^{2}/ hbox{V} cdot hbox{s}$. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 $muhbox{A}/muhbox{m}$ at $V_{g} - V_{t} = hbox{1.6} hbox{V}$ and peak transconductance of 715 $muhbox{S}/muhbox{m}$. In addition, the virtual source velocity extracted from the short-channel devices is 1.4–1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance $hbox{In}_{0.7}hbox{Ga}_{0.3} hbox{As}$-channel MOSFETs passivated by an $alpha$ -Si layer are promising candidates for advanced post-Si CMOS applications.      

Nonvolatile-Memory Characteristics of $hbox{AlO}^{-}$ -Implanted $hbox{Al}_{2}hbox{O}_{3}$

The nonvolatile-memory (NVM) characteristics of $hbox{AlO}^{-}$ -implanted $hbox{Al}_{2}hbox{O}_{3}$ structures are reported and shown to exhibit promising behaviors, including fast program/erase speeds and high-temperature data retention. Photoconductivity spectra show the existence of two dominant trap levels, located at around 2 and 4 eV below the conduction band minimum of $hbox{Al}_{2}hbox{O}_{3}$, and our calculations show that these levels are likely attributed to the defects in the $hbox{Al}_{2}hbox{O}_{3}$, such as the Al–O divacancy. The relative concentrations of these defects vary with the implant fluence and are shown to explain the NVM characteristics of the samples irradiated to different fluences.      

A 200-$mu$V/e$^{-}$ CMOS Image Sensor With 100-ke$^{-}$ Full Well Capacity

A high-sensitivity CMOS image sensor keeping a high full-well capacity has been developed by introducing a new pixel having a small floating diffusion (FD) capacitance connected to a lateral overflow integration capacitor (LOFIC) through a MOS switch. The conceptual advantage of the small FD approach over conventional column amplifier approaches is compared and demonstrated. To ensure both the high sensitivity and the high full-well capacity, the low-light and the bright-light signals (S1 and S2) are output and reproduced without a visible SNR degradation at the S1/S2 switching point. As the most critical problem, the increase of the conversion gain variation in this approach is suppressed by applying a self-aligned offset structure to the small FD. A 1/4-in VGA format CMOS image sensor fabricated through 0.18-mum 2P3M process achieves 2.2-e^- rms noise floor with 200-muV/e^- conversion gain and 100-ke^- full-well capacity.     

Underdetermined Anechoic Blind Source Separation via $ell^{q}$-Basis-Pursuit With $q≪1$

In this paper, we address the problem of underdetermined blind source separation (BSS) of anechoic speech mixtures. We propose a demixing algorithm that exploits the sparsity of certain time-frequency expansions of speech signals. Our algorithm merges lscr^q -basis-pursuit with ideas based on the degenerate unmixing estimation technique (DUET) [Yiotalmaz and Rickard, "Blind Source Separation of Speech Mixtures via Time-Frequency Masking," IEEE Transactions on Signal Processing, vol. 52, no. 7, pp. 1830-1847, July 2004]. There are two main novel components to our approach: 1, our algorithm makes use of all available mixtures in the anechoic scenario where both attenuations and arrival delays between sensors are considered, without imposing any structure on the microphone positions, and 2, we illustrate experimentally that the separation performance is improved when one uses lscr^q-basis-pursuit with q < 1 compared to the q = 1 case. Moreover, we provide a probabilistic interpretation of the proposed algorithm that explains why a choice of 0.1 les q les 0.4 is appropriate in the case of speech. Experimental results on both simulated and real data demonstrate significant gains in separation performance when compared to other state-of-the-art BSS algorithms reported in the literature.     

Eigendecomposition of Images Correlated on $S^{1}$, $S^{2}$, and $SO(3)$ Using Spectral Theory

Eigendecomposition represents one computationally efficient approach for dealing with object detection and pose estimation, as well as other vision-based problems, and has been applied to sets of correlated images for this purpose. The major drawback in using eigendecomposition is the off line computational expense incurred by computing the desired subspace. This off line expense increases drastically as the number of correlated images becomes large (which is the case when doing fully general 3-D pose estimation). Previous work has shown that for data correlated on S ¹ , Fourier analysis can help reduce the computational burden of this off line expense. This paper presents a method for extending this technique to data correlated on S ² as well as SO(3) by sampling the sphere appropriately. An algorithm is then developed for reducing the off line computational burden associated with computing the eigenspace by exploiting the spectral information of this spherical data set using spherical harmonics and Wigner-D functions. Experimental results are presented to compare the proposed algorithm to the true eigendecomposition, as well as assess the computational savings.     

Improved Electrical Properties of Ge p-MOSFET With $ hbox{HfO}_{2}$ Gate Dielectric by Using $hbox{TaO}_{x} hbox{N}_{y}$ Interlayer

The electrical characteristics of germanium p-metal-oxide-semiconductor (p-MOS) capacitor and p-MOS field-effect transistor (FET) with a stack gate dielectric of HfO₂/TaOxNy are investigated. Experimental results show that MOS devices exhibit much lower gate leakage current than MOS devices with only HfO₂ as gate dielectric, good interface properties, good transistor characteristics, and about 1.7-fold hole-mobility enhancement as compared with conventional Si p-MOSFETs. These demonstrate that forming an ultrathin passivation layer of TaOxNy on germanium surface prior to deposition of high-k dielectrics can effectively suppress the growth of unstable GeOx, thus reducing interface states and increasing carrier mobility in the inversion channel of Ge-based transistors.     

High Density and Low Leakage Current in $ hbox{TiO}_{2}$ MIM Capacitors Processed at 300 $^{circ} hbox{C}$

We report Ir/TiO₂/TaN metal-insulator-metal capacitors processed at only 300degC, which show a capacitance density of 28 fF/mum² and a leakage current of 3 times 10^-8 (25degC) or 6 times 10^-7 (125degC) A/cm² at -1 V. This performance is due to the combined effects of 300degC nanocrystallized high-kappa TiO₂, a high conduction band offset, and high work-function upper electrode. These devices show potential for integration in future very-large-scale-integration technologies.     

High-Performance Poly-Silicon TFTs Using a High-$k$ $hbox{PrTiO}_{3}$ Gate Dielectric

In this letter, a polycrystalline-silicon thin-film transistor (poly-Si TFT) with a high- $k$ $hbox{PrTiO}_{3}$ gate dielectric is proposed for the first time. Compared to TFTs with a $hbox{Pr}_{2}hbox{O}_{3}$ gate dielectric, the electrical characteristics of poly-Si TFTs with a $hbox{PrTiO}_{3}$ gate dielectric can be significantly improved, such as lower threshold voltage, smaller subthreshold swing, higher $I_{rm on}/I_{rm off}$ current ratio, and larger field-effect mobility, even without any hydrogenation treatment. These improvements can be attributed to the high gate capacitance density and low grain-boundary trap state. All of these results suggest that the poly-Si TFT with a high- $k$ $hbox{PrTiO}_{3}$ gate dielectric is a good candidate for high-speed and low-power display driving circuit applications in flat-panel displays.      

Reducing the Number of Comparators in Multibt $Delta Sigma $ Modulators

Multibit feedback, being one way of lowering DeltaSigma modulators power consumption, has a major obstacle: the number of components in the internal analog-to-digital converter (ADC) and digital-to-analog converter (DAC). Nevertheless, the number of comparators in the ADC can be significantly reduced depending on the order of noise-shaping and the oversampling ratio. In this paper, we propose an auto-ranging algorithm with a mechanism to keep the structure stable that emulates more quantization levels than that allowed by the number of comparators. As the recourse to segmented DACs allows lowering the complexity of the mismatch shaping encoder, the auto-ranging ADC brings the benefits of multibit feedback without the usual increase in size and power consumption. The internal number of bits in DeltaSigma modulators is no more restricted by the difficulty of building the flash ADC with a low voltage supply.     

AlGaN/GaN MOS-HEMT With $hbox{HfO}_{2}$ Dielectric and $hbox{Al}_{2}hbox{O}_{3}$ Interfacial Passivation Layer Grown by Atomic Layer Deposition

We have developed a novel AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistor using a stack gate HfO₂/Al₂O₃ structure grown by atomic layer deposition. The stack gate consists of a thin HfO₂ (30-A) gate dielectric and a thin Al₂O₃ (20- A) interfacial passivation layer (IPL). For the 50-A stack gate, no measurable C-V hysteresis and a smaller threshold voltage shift were observed, indicating that a high-quality interface can be achieved using a Al₂O₃ IPL on an AlGaN substrate. Good surface passivation effects of the Al₂O₃ IPL have also been confirmed by pulsed gate measurements. Devices with 1- mum gate lengths exhibit a cutoff frequency (fT) of 12 GHz and a maximum frequency of oscillation (f _MAX) of 34 GHz, as well as a maximum drain current of 800 mA/mm and a peak transconductance of 150 mS/mm, whereas the gate leakage current is at least six orders of magnitude lower than that of the reference high-electron mobility transistors at a positive gate bias.     

Dual-Gate Graphene FETs With $f_{T}$ of 50 GHz

A dual-gate graphene field-effect transistor is presented, which shows improved radio-frequency (RF) performance by reducing the access resistance using electrostatic doping. With a carrier mobility of 2700 cm²/V · s, a cutoff frequency of 50 GHz is demonstrated in a 350-nm-gate-length device. This f_T value is the highest frequency reported to date for any graphene transistor, and it also exceeds that of Si MOS field-effect transistors at the same gate length, illustrating the potential of graphene for RF applications.     

Scaling Properties of $hbox{Ge}$ –$hbox{Si}_{x}hbox{Ge}_{1 - x}$ Core–Shell Nanowire Field-Effect Transistors

We demonstrate the fabrication of high-performance $hbox{Ge}$ –$hbox{Si}_{x}hbox{Ge}_{1 - x}$ core–shell nanowire (NW) field-effect transistors with highly doped source (S) and drain (D) and systematically investigate their scaling properties. Highly doped S and D regions are realized by low-energy boron implantation, which enables efficient carrier injection with a contact resistance much lower than the NW resistance. We extract key device parameters, such as intrinsic channel resistance, carrier mobility, effective channel length, and external contact resistance, as well as benchmark the device switching speed and on/off current ratio.      

A Programmable 25-MHz to 6-GHz $K/L$ Frequency Multiplier With Digital $K_{rm vco}$ Compensation

A programmable rational-$K/L$ frequency multiplier that can synthesize any frequency between 25 MHz and 6 GHz from an input clock ranging from 1 to 5.5 GHz is presented. The architecture employs a fractional-$N$ input clock divider followed by a fractional- $N$ PLL. In contrast to conventional architectures, this allows large $K$ and $L$ , whose maximum values are limited only by the word-length of digital $SigmaDelta$ modulators. Additionally, to alleviate large $K_{rm vco}$ variation and fractional spurs, which are inevitable in wide tuning range VCOs and fractional-$N$ synthesizers, new compensation techniques are implemented without involving additional circuitry. This is an ideal solution to support a programmable serializer/deserializer on a field-programmable gate array.      

Stochastic Modeling of the Transform-Domain $varepsilon {rm LMS}$ Algorithm

This paper presents a statistical analysis of the transform-domain least-mean-square (TDLMS) algorithm, resulting in a more accurate model than those discussed in the current open literature. The motivation to analyze such an algorithm comes from the fact that the TDLMS presents a higher convergence speed for correlated input signals, as compared with other adaptive algorithms possessing a similar computational complexity. Such a fact makes it a highly competitive alternative to some applications. Approximate analytical models for the first and second moments of the filter weight vector are obtained. The TDLMS algorithm has an orthonormal transformation stage, accomplishing a decomposition of the input signal into distinct frequency bands, in which the interband samples are practically uncorrelated. On the other hand, the intraband samples are correlated; the larger the number of bands, the higher their correlation. The model is then derived taking into account such a correlation, requiring that a high-order hyperelliptic integral be computed. In addition to the proposed model, an approximate procedure for computing high-order hyperelliptic integrals is presented. A regularization parameter is also considered in the model expressions, permitting to assess its impact on the adaptive algorithm behavior. An upper bound for the step-size control parameter is also obtained. Through simulation results, the accuracy of the proposed model is assessed.