An FIR-Embedded Noise Filtering Method for $Delta Sigma$ Fractional-N PLL Clock Generators

This paper describes a noise filtering method for $Delta Sigma$ fractional- $N$ PLL clock generators to reduce out-of-band phase noise and improve short-term jitter performance. Use of a low-cost ring VCO mandates a wideband PLL design and complicates filtering out high-frequency quantization noise from the $Delta Sigma$ modulator. A hybrid finite impulse response (FIR) filtering technique based on a semidigital approach enables low-OSR $Delta Sigma$ modulation with robust quantization noise reduction despite circuit mismatch and nonlinearity. A prototype 1-GHz $Delta Sigma$ fractional-$N$ PLL is implemented in 0.18 $muhbox{m}$ CMOS. Experimental results show that the proposed semidigital method effectively suppresses the out-of-band quantization noise, resulting in nearly 30% reduction in short-term jitter.      

Analysis of Reset Discharge Characteristics in AC-Plasma Display Panel With Various Sustain Gaps Using $V_{t}$ Close-Curve

The effects of various sustain gaps on the reset discharge characteristics, particularly the discharge stability, are examined based on a $V_{t}$ close-curve analysis. The $V_{t}$ close-curve analysis shows that the reset discharge region producing a stable discharge under an MgO cathode condition is reduced in proportion to the increase in the sustain gap, resulting in discharge instability when a conventional reset waveform is applied with a wide-sustain-gap (over 200 $muhbox{m}$) structure. Based on the $V_{t}$ close-curve analysis, a modified reset waveform suitable for a wide-sustain-gap $(= hbox{200} muhbox{m})$ structure is proposed to prevent an unstable discharge. The effects of two parameters $V_{{rm add}hbox{-}{rm bias}}$ and $V_{{rm com}hbox{-}{rm bias}}$ in the modified reset waveform on the reset discharge as well as the address and first sustain discharges, are examined in detail.      

An Edge Missing Compensator for Fast Settling Wide Locking Range Phase-Locked Loops

An edge missing compensator (EMC) is proposed to approach the function of an ideal PD with $pm 2 ^{N-1} times 2pi $ linear range with $N$-bit EMC. A PLL implemented with a 9-bit EMC achieves 320 MHz frequency hopping within 10 $~mu{hbox {s}}$ logarithmically which is about 2.4 times faster than the conventional design. The reference spur of the PLL is ${-}{hbox {48.7~dBc}}$ and the phase noise is ${-}hbox{88.31~dBc/Hz}$ at 10 kHz offset with $K_{rm VCO}= -$ 2 GHz/V.      

A 0.55 V 60 dB-DR Fourth-Order Analog Baseband Filter

A 0.55 V supply voltage fourth-order low-pass continuous-time filter is presented. The low-voltage operating point is achieved by an improved bias circuit that uses different opamp input and output common-mode voltages. The fourth-order filter architecture is composed by two Active- ${rm G}_{rm m}{-}{rm RC}$ biquadratic cells, which use a single opamp per-cell with a unity-gain-bandwidth comparable to the filter cut-off frequency. The $-$ 3 dB filter frequency is 12 MHz and this is higher than any other low-voltage continuous-time filter cut-off frequency. The $-$3 dB frequency can be adjusted by means of a digitally-controlled capacitance array. In a standard 0.13 $mu{rm m}$ CMOS technology with ${V}_{THN}approx 0.25 {rm V}$ and ${V}_{THP}approx 0.3 {rm V}$, the filter operates with a supply voltage as low as 0.55 V. The filter $({rm total} {rm area}=0.47 {rm mm}^{2})$ consumes 3.4 mW. A 8 dBm-in-band IIP3 and a 13.3 dBm-out-of-band IIP3 demonstrate the validity of the proposal.      

RF Power Measurements of InAlN/GaN Unstrained HEMTs on SiC Substrates at 10 GHz

Unstrained high-electron mobility transistors (HEMTs) were fabricated from InAlN/GaN on semi-insulating SiC substrates. The devices had 0.24-$muhbox{m}$ T-gates with a total width of $hbox{2} times hbox{150} muhbox{m}$. Final passivated performance values for these devices are $I_{max} = hbox{1279} hbox{mA/mm}$, $I_{rm DSS} = hbox{1182} hbox{mA/mm}$ , $R_{c} = hbox{0.43} Omega cdot hbox{mm}$, $rho_{s} = hbox{315} Omega/hbox{sq}$, $f_{T} = hbox{45} hbox{GHz}$, $f_{max({rm MAG})} = hbox{64} hbox{GHz}$, and $g_{m} = hbox{268} hbox{mS/mm}$. Continuous-wave power measurements at 10 GHz produced $P_{rm sat} = hbox{3.8} hbox{W/mm}$, $G_{t} = hbox{8.6} hbox{dB}$, and $hbox{PAE} = hbox{30}%$ at $V_{rm DS} = hbox{20} hbox{V}$ at 25% $I_{rm DSS}$ . To our knowledge, these are the first power measurements reported at 10 GHz for this material.      

Characterization and Modeling of RF-Performance $(f_{T})$ Fluctuation in MOSFETs

The fluctuation of RF performance (particularly for $f_{T}$ : cutoff frequency) in the transistors fabricated by 90-nm CMOS technology has been investigated. The modeling for $f_{T}$ fluctuation is well fitted with the measurement data within approximately 1% error. Low-$V_{t}$ transistors (fabricated by lower doping concentration in the channel) show higher $f_{T}$ fluctuation than normal transistors. Such a higher $f_{T}$ fluctuation results from $C_{rm gg}$ (total gate capacitance) variation rather than $g_{m}$ variation. More detailed analysis shows that $C_{rm gs} + C_{rm gb}$ (charges in the channel and the bulk) are predominant factors over $C_{rm gd}$ (charges in LDD/halo region) to determine $C_{rm gg}$ fluctuation.      

Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires

This letter demonstrates a vertical silicon-nanowire (SiNW)-based tunneling field-effect transistor (TFET) using CMOS-compatible technology. With a $hbox{Si} hbox{p}^{+}{-}hbox{i}{-} hbox{n}^{+}$ tunneling junction, the TFET with a gate length of $sim$200 nm exhibits good subthreshold swing of $sim$ 70 mV/dec, superior drain-induced-barrier-lowering of $sim$ 17 mV/V, and excellent $I_{rm on} {-} I_{rm off}$ ratio of $sim!!hbox{10}^{7}$ with a low $I_{rm off} (sim!!hbox{7} hbox{pA}/muhbox{m})$. The obtained 53 $muhbox{A}/muhbox{m} I_{rm on}$ can be further enhanced with heterostructures at the tunneling interface. The vertical SiNW-based TFET is proposed to be an excellent candidate for ultralow power and high-density applications.      

Role of Nitrogen Atoms in Reduction of Electron Charge Traps in Hf-Based High- κ Dielectrics

Effects of nitrogen incorporation on suppression of electron charge traps in Hf-based high- $kappa$ gate dielectrics have been studied by first-principles calculations, focusing on interactions between N atoms and electrons trapped at oxygen vacancies $(V_{rm O}{hskip0.2pt}hbox{'s})$. Our total energy calculations revealed that the formation energy of a doubly occupied state of $V_{rm O}$ is significantly increased in $hbox{HfO}_{x} hbox{N}_{y}$ compared to that in $hbox{HfO}_{2}$ . This clearly indicates that the electron charge traps at $V_{rm O}{ hskip0.2pt}hbox{'s}$ are considerably suppressed by N incorporation.      

High-Temperature Microwave Performance of Submicron AlGaN/GaN HEMTs on SiC

The effect of temperature on the small-signal radio-frequency (RF) performance of submicron AlGaN/GaN high-electron-mobility transistors on SiC has been studied from room temperature (RT) up to 600 K. A relation between ambient and channel temperatures has been established by means of finite-element simulations. The thermal behavior of the intrinsic parameters $C_{rm gs}$, $C_{rm gd}$, $g_{m, {rm int}}$, and $g_{rm ds}$ has been extracted accurately from RF measurements by means of the small-signal equivalent circuit. Main dc parameters $(I_{D}, g_{m, {rm ext}})$ show reductions close to 50% between RT and 600 K, mainly due to the decrease in the electron mobility and drift velocity. In the same range, $f_{T}$ and $f_{max}$ suffer a 60% decrease due to the reduction in $g_{m, {rm ext}}$ and a slight increase of $C_{rm gs}$ and $C_{rm gd}$. An anomalous thermal evolution of $C_{rm gd}$ at low $I_{D}$ has been identified, which is indicative of the presence of traps.      

Performance Improvement of N-Type $hbox{TiO}_{x}$ Active-Channel TFTs Grown by Low-Temperature Plasma-Enhanced ALD

We report on performance improvement of $n$-type oxide–semiconductor thin-film transistors (TFTs) based on $hbox{TiO}_{x}$ active channels grown at 250 $^{circ}hbox{C}$ by plasma-enhanced atomic layer deposition. TFTs with as-grown $hbox{TiO}_{x}$ films exhibited the saturation mobility $(mu_{rm sat})$ as high as 3.2 $hbox{cm}^{2}/hbox{V}cdothbox{s}$ but suffered from the low on–off ratio $(I_{rm ON}/I_{rm OFF})$ of $hbox{2.0} times hbox{10}^{2}$. $hbox{N}_{2}hbox{O}$ plasma treatment was then attempted to improve $I_{rm ON}/I_{rm OFF}$. Upon treatment, the $hbox{TiO}_{x}$ TFTs exhibited $I_{rm ON}/I_{rm OFF}$ of $hbox{4.7} times hbox{10}^{5}$ and $mu_{rm sat}$ of 1.64 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, showing a much improved performance balance and, thus, demonstrating their potentials for a wide variety of applications such as backplane technology in active-matrix displays and radio-frequency identification tags.      

An Analytical Method to Extract the Physical Parameters of a Solar Cell From Four Points on the Illuminated $J{-}V$ Curve

For a variety of solar cells, it is shown that the single exponential $J{-}V$ model parameters, namely—ideality factor $eta$ , parasitic series resistance $R_{s}$, parasitic shunt resistance $R_{rm sh}$, dark current $J_{0}$, and photogenerated current $J_{rm ph}$ can be extracted simultaneously from just four simple measurements of the bias points corresponding to $V_{rm oc}$, $sim!hbox{0.6}V_{rm oc}$, $J_{rm sc}$, and $sim! hbox{0.6}J_{rm sc}$ on the illuminated $J{-}V$ curve, using closed-form expressions. The extraction method avoids the measurements of the peak power point and any $dJ/dV$ (i.e., slope). The method is based on the power law $J{-}V$ model proposed recently by us.      

On Parallelepiped-Shaped Passbands for Multidimensional Nonseparable ${bf M}$th-Band Low-Pass Filters

The “shape” of the desired frequency passband is an important consideration in the design of nonseparable multidimensional ($M$ -D) filters in $M$-D multirate systems. For $M$-D ${bf M}$th-band filters, the passband shape should be chosen such that the ${bf M}$th-band constraint is satisfied. The most commonly used shape of the passband for $M$-D ${bf M}$ th-band low-pass filters is the so-called symmetric parallelepiped (SPD) ${rm SPD}(pi {bf M}^{- {rm T}})$ . In this paper, we consider the more general parallelepiped passband ${rm SPD}(pi {bf L} ^{rm T})$, and derive conditions on $ {bf L} $ such that the ${bf M}$ th-band constraint is satisfied. This result gives some flexibility in designing $M$-D ${bf M}$th-band filters with parallelepiped shapes other than the commonly used case of $ {bf L} = {bf M}^{- 1}$. We present design examples of 2-D ${bf M}$th-band filters to illustrate this flexibility in the choice of $ {bf L} $.      

First Internal Spacers' Introduction in Record High $I_{rm ON}/I_{rm OFF} hbox{TiN/HfO}_{2}$ Gate Multichannel MOSFET Satisfying Both High-Performance and Low Standby Power Requirements

For the first time, internal spacers have been introduced in multichannel CMOSFET (MCFET) structures, featuring a decrease of the intrinsic $CV/I$ delay by 39%. The process steps introduced for this new MCFET technological option are studied and optimized in order to achieve excellent $I_{rm ON}/I_{rm OFF}$ characteristics (NMOS: 2.33 $hbox{mA}/muhbox{m}$ at 27 $hbox{pA}/muhbox{m}$ and PMOS: 1.52 $hbox{mA}/muhbox{m}$ at 38 $hbox{pA}/muhbox{m}$). A gate capacitance $C_{rm gg}$ reduction of 32% is measured, thanks to $S$-parameter extraction. Moreover, a significant improvement of the analogical figure of merit is measured compared with optimized fully depleted silicon-on-insulator planar reference; the voltage gain $A_{rm VI}(= g_{m}/g_{rm ds})$ is improved by 92%.      

High-Performance 0.1-$muhbox{m}$ Gate AlGaN/GaN HEMTs on Silicon With Low-Noise Figure at 20 GHz

The realization of high-performance 0.1-$muhbox{m}$ gate AlGaN/GaN high-electron mobility transistors (HEMTs) grown on high-resistivity silicon substrates is reported. Our devices feature cutoff frequencies as high as $f_{T} = hbox{75} hbox{GHz}$ and $f_{rm MAX} = hbox{125} hbox{GHz}$, the highest values reported so far for AlGaN/GaN HEMTs on silicon. The microwave noise performance is competitive with results achieved on other substrate types, such as sapphire and silicon carbide, with a noise figure $F = hbox{1.2}{-}hbox{1.3} hbox{dB}$ and an associated gain $G_{rm ass} = hbox{8.0}{-}hbox{9.5} hbox{dB}$ at 20 GHz. This performance demonstrates that GaN-on-silicon technology is a viable alternative for low-cost millimeter-wave applications.      

A Decorrelating Design-for-Digital-Testability Scheme for $Sigma{-}Delta$ Modulators

This paper presents a novel decorrelating design-for-digital-testability $({rm D}^{3}{rm T})$ scheme for $Sigma{-}Delta$ modulators to enhance the test accuracy of using digital stimuli. The input switched-capacitor network of the modulator under test is reconfigured as two or more subdigital-to-charge converters in the test mode. By properly designing the digital stimuli, the shaped noise power of the digital stimulus can be effectively attenuated. As a result, the shaped noise correlation as well as the modulator overload issues are alleviated, thus improving the test accuracy. A second-order $Sigma{-}Delta$ modulator design is used as an example to demonstrate the effectiveness of the proposed scheme. The behavioral simulation results showed that, when the signal level of the stimulus tone is less than $-$5 dBFS, the signal-to-noise ratios obtained by the digital stimuli are inferior to those obtained by their analog counterparts of no more than 1.8 dB. Circuit-simulation results also demonstrated that the ${rm D}^{3}{rm T}$ scheme has the potential to test moderate nonlinearity. The proposed ${rm D}^{3}{rm T}$ scheme has the advantages of achieving high test accuracy, low circuit overhead, high fault observability, and the capability of conducting at-speed tests.      

Electrical Properties of $hbox{Ga}_{2}hbox{O}_{3}/ hbox{GaAs}$ Interfaces and GdGaO Dielectrics in GaAs-Based MOSFETs

Electrical properties of $hbox{Ga}_{2}hbox{O}_{3}/hbox{GaAs}$ interfaces with GdGaO cap dielectrics used in recent enhancement-mode GaAs-based NMOSFETs which perform in line with theoretical model predictions are presented. Capacitors with GdGaO thickness ranging from 3.0 to 18 nm ($hbox{0.9} leq hbox{EOT} leq hbox{3.9} hbox{nm}$) have been characterized by capacitance–voltage measurements. Midgap interface state density $D_{rm it}$, effective workfunction $phi_{m}$, fixed charge $Q_{f}$, dielectric constant $kappa$, and low field leakage current density are $hbox{2} times hbox{10}^{11} hbox{cm}^{-2} cdot hbox{eV}^{-1}$, 4.93 eV, $-hbox{8.9} times hbox{10}^{11} hbox{cm}^{-2}$, 19.5, and $hbox{10}^{-9}{-} hbox{10}^{-8} hbox{A/cm}^{2}$, respectively. The presence of interfacial Gd was confirmed to dramatically degrade electrical interface properties. The data illuminate the intimate interplay between heterostructure and interface engineering to achieve optimum MOSFET operation.      

N-Channel MOSFETs With Embedded Silicon–Carbon Source/Drain Stressors Formed Using Cluster-Carbon Implant and Excimer-Laser-Induced Solid Phase Epitaxy

In this letter, we report the use of a novel cluster-carbon $(hbox{C}_{7} hbox{H}_{7}^{+})$ implant and pulsed-excimer-laser-induced solid-phase-epitaxy technique to form embedded silicon–carbon (Si:C) source/drain (S/D) stressors. A substitutional carbon concentration $C_{rm sub}$ of $sim$ 1.1% was obtained in this letter. N-channel MOSFETs (n-FETs) integrated with embedded silicon–carbon (Si:C) S/D stressors formed using the novel cluster-carbon implant and pulsed-laser-anneal technique demonstrate improvement in current drive of 14% over control n-FETs formed with Si preamorphization implant. $I_{rm OFF}{-}I_{rm DSAT}$ comparison shows a 15% $I_{rm DSAT}$ enhancement for n-FETs with embedded Si:C S/D at an $I_{rm OFF} = hbox{1} hbox{nA}/muhbox{m}$ despite a slightly higher series resistance.      

Low-Threshold Strained Quantum-Well GaSb-Based Lasers Emitting in the 2.5- to 2.7-$mu$ m Wavelength Range

GaInAsSb–GaSb strained quantum-well (QW) ridge waveguide diode lasers emitting in the wavelength range from 2.51 to 2.72 $ mu{hbox {m}}$ have been grown by molecular beam epitaxy. The devices show ultralow threshold current densities of 44 $hbox{A}/{hbox {cm}}^{2}$ (${L}rightarrow infty $) for a single QW device at 2.51 $ mu{hbox {m}}$, which is the lowest reported value in continuous-wave operation near room temperature (15 $^{circ}hbox{C}$) at this wavelength. The devices have an internal loss of 3 ${hbox {cm}}^{-1}$ and a characteristic temperature of 42 K. By using broader QWs, wavelengths up to 2.72 $mu{hbox {m}}$ could be achieved.      

2 MHz AO $Q$ -switched ${rm TEM}_{00}$ Grazing Incidence Laser With 3 at.% Neodymium Doped Nd:YVO$_{4}$

We present a detailed experimental and theoretical study of the ultrahigh repetition rate AO $Q$ -switched ${rm TEM}_{00}$ grazing incidence laser. Up to 2.1 MHz $Q$-switching with ${rm TEM}_{00}$ output of 8.6 W and 2.2 MHz $Q$ -switching with multimode output of 10 W were achieved by using an acousto-optics $Q$ -switched grazing-incidence laser with optimum grazing-incidence angle and cavity configuration. The crystal was 3 at.% neodymium doped Nd:YVO$_{4}$ slab. The pulse duration at 2 MHz repetition rate was about 31 ns. The instabilities of pulse energy at 2 MHz repetition rate were less than ${pm}6.7hbox{%}$ with ${rm TEM}_{00}$ operation and ${pm}3.3hbox{%}$ with multimode operation respectively. The modeling of high repetition rate $Q$-switched operation is presented based on the rate equation, and with the solution of the modeling, higher pump power, smaller section area of laser mode, and larger stimulated emission cross section of the gain medium are beneficial to the $Q$-switched operation with ultrahigh repetition rate, which is in consistent with the experimental results.      

High-Performance Metal/High-$k$ n- and p-MOSFETs With Top-Cut Dual Stress Liners Using Gate-Last Damascene Process on (100) Substrates

Newly proposed mobility-booster technologies are demonstrated for metal/high- $k$ gate-stack n- and pMOSFETs. The process combination of top-cut SiN dual stress liners and damascene gates remarkably enhances local channel stress particularly for shorter gate lengths in comparison with a conventional gate-first process. Dummy gate removal in the damascene gate process induces high channel stress, because of the elimination of reaction force from the dummy gate. PFETs with top-cut compressive stress liners and embedded SiGe source/drains are performed by using atomic layer deposition TiN/$ hbox{HfO}_{2}$ gate stacks with $T_{rm inv} = hbox{1.4} hbox{nm}$ on (100) substrates. On the other hand, nFETs with top-cut tensile stress liners are obtained by using $hbox{HfSi}_{x}/hbox{HfO}_{2}$ gate stacks with $T_{rm inv} = hbox{1.4} hbox{nm}$. High-performance n- and pFETs are achieved with $I_{rm on} = hbox{1300}$ and 1000 $muhbox{A}/muhbox{m} hbox{at} I_{rm off} = hbox{100} hbox{nA}/mu hbox{m}$, $V_{rm dd} = hbox{1.0} hbox{V}$, and a gate length of 40 nm, respectively.