VCS Observed Coverage技术的评估

1.0简介 当前,设计验证已经成为半导体芯片设计过程所面临的主要难题之一.如何确认芯片能够在相关应用中正确运行?除了需要写出尽可能多的测试向量来验证芯片的各方面功能以外,下列问题也变得日益重要:如何测定这些测试的质量?测试包到底覆盖了多大范围的芯片功能?对于这些问题,传统的解决方法是应用代码覆盖率分析工具.利用这些工具可以测量出在仿真状态下实际执行了设计的多大部分,并能提供有关代码行覆盖率、条件覆盖率、信号翻转覆盖率的报告.但是,代码覆盖率分析工具所能给出的覆盖率数值在本质上属于乐观性的估计:举例来说,它们可以指出一条代码行得到了执行,但是却不能指出这条代码行上的代码,其正确性是否得到了验证.因此,有可能出现这种情况,即有报告显示一条代码行已经在仿真状态下得以覆盖,但是由此产生的效果却未在仿真中检查出来,并未检查到这条代码行的错误功能.测试结果可能会显示"合格",但却没有察觉到错误的功能行为.     

数字中频芯片的仿真研究

数字中频芯片通常间接地采取matlab的方式进行datapath滤波器等功能的设计和验证。在此基础上直接对数字中频RTL代码进行仿真验证研究,分别从单音、宽带、delay测试等方面进行阐述,结合快速傅立叶变换,综合运用python脚本工具分析结果。研究结果表明,相对于间接采用matlab仿真,直接的RTL代码仿真不仅能实现同样的测试功能,而且可以更好地提升代码覆盖率和功能覆盖率,进一步提升了验证质量。     

SRAM的设计验证

介绍了两种SRAM的设计验证方法:1.用PERL编写的应用程序按设计要求自动生成仿真测试文件完成全芯片功能/时序分析.2.形式验证的方法的应用--Synopsys公司先进的EDA软件ESP-CV来实现对较大容量的SRAM的功能验证.文章在简述两种方法的基础上,用具体实例详细描述了两种方法在电路仿真测试中的应用,并给出了电路的部分测试文件及仿真结果,进一步论述了该方法的可行性及实用性.     

无线通信系统维特比译码的FPGA仿真验证

在设计宽带无线通信系统的基带平台中,采用一种基于FPGA仿真工具Active HDL和目前广泛用于数字信号处理、数值分析等的实用软件Matlab相结合的方法,通过实现(2,1,7)卷积编码的全并行维特比软判决译码的FPGA设计仿真和算法验证,提出一种利用Matlab进行测试向量的生成和验证,以简化仿真测试序列的手工输入,提高FPGA设计进程和保证代码质量的方法。     

分布式馈线自动化仿真测试平台设计与应用

针对配电网分布式馈线自动化动作逻辑的现场测试存在较大的困难。基于电力系统仿真工具实时数字仿真仪RTDS,设计了一种配电自动化系统分布式馈线自动化仿真测试平台。通过接口模块可实现RTDS中电气信号与分布式馈线自动化智能终端控制信号的同步和交互,从而构建了实时闭环的高保全仿真测试平台,能够逼真地模拟分布式馈线自动化系统的故障形态和逻辑处理功能。最后通过对某城市实际配电网的测试应用,验证了所设计平台的可行性和有效性。     

基于串行通讯的FPGA片上RAM数据下载与系统调试

本文开发了一种内嵌2kB RAM的UART控制模块,可实现从PC机发送代码至控制模块内部的RAM中,再将代码读取至需要进行功能验证的系统,可以进行RAM数据下载与系统调试。控制模块利用开源的MC8051 IP核进行系统的功能验证,并成功进行了Modelsim下的仿真和FPGA与PC机的实际通信测试,效果良好。     

数字下变频的一种新型设计方法

阐述了雷达中频正交采样的原理,研究了使用System Generator实现数字下变频的一种自顶向下的新型设计方法。在Simulink中进行了功能仿真验证,生成了HDL代码,并在Xilinx FPGA中进行了RTL的时序仿真分析。     

PCI Express协议实现与验证

称为第3代I/O接口技术的PCI Express总线规范的出现,从结构上解决了带宽不足的问题,有着极为广阔的发展前景。基于Verilog HDL硬件描述语言及可综合化设计理念,完成了PCI Express IP核RTL代码的设计。IP核代码使用Verilog HDL语言编写,分模块、分层次地设计了事务层、数据链路层和物理层的逻辑子层,并进行了可综合化设计与代码风格检查。对设计的PCI Express IP核的功能分别从协议层次和应用层次进行了验证。具体实现上,采用Denali公司的PureSuite测试套件对IP核的协议兼容性进行验证,验证范围覆盖了IP核的3个层次以及配置空间,采用QuestaSim仿真工具对IP核的应用层进行验证。仿真结果表明,设计的PCI Express IP核工作正常,性能优良。     

SoC中多层AHB总线的断言验证应用

随着SoC设计复杂程度的不断提高,芯片的功能验证面临的挑战越来越大。断言作为一种描述属性的方法,可以快速地验证设计代码是否满足系统要求。基于断言的验证方法学近年来发展极为迅速,应用也越来越广泛。在基于Multi-layer AHB总线架构上的SoC系统验证过程中,采用System Verilog Assertion验证方法,证明SVA是SoC设计过程中功能验证的一种有效的验证方法。     

基于属性的形式验证技术及应用

为了提高产品的验证覆盖率和首次流片成功率,越来越多的验证技术和衡量标准被采纳。传统的仿真验证技术很难达到验证的快速收敛,而静态验证技术采用数学穷举的方法,利用断言对cornerco．se进行快速验证,有效避免了一些设计缺陷。Mentor公司的QuestaFormal工具可以对代码进行常规的功能检查,并可用Formal引擎证明设计代码及其断言的一致性,可极大地提高复杂设计的验证效率和鲁棒性。     

An Automatic Functional Coverage for Digital Systems Through a Binary Particle Swarm Optimization Algorithm with a Reinitialization Mechanism

At present, functional verification represents the most expensive part of the digital systems design. Moreover, different problems such as: clock synchronization, code compatibility, simulation automation, new design methodologies, proper use of coverage metrics, among others represent challenges in this area. The automated test vector generation is involved in these problems. In this work, an automated functional test sequences generation for digital systems based on the use of coverage models and a binary Particle Swarm Optimization algorithm with a reinitialization mechanism (BPSOr) is described. Also, a comparison with other meta-heuristic algorithms such as: Genetic algorithms (GA) and pseudo-random generation is presented using different fitness functions, coverage models and devices under verification. The main strategy is based on the combination of the simulation and meta-heuristic algorithms to test the device behavior through the generation of test vector sequences. According to the results, the proposed test generation method represents a good alternative to increase the functional coverage during the automated functional verification of block-level digital systems verification.     

Verification Simulation Acceleration Using Code-Perturbation

We propose a simulation approach that can take a large design and swiftly cover its valid code-level operating states. The approach perturbs the program-control flow during the simulation to dynamically exhaust all branching possibilities in a verification code/program. The heuristic uses the program branching information from preprocessing the test/verification code. Using the branching information the simulation allows automatic run-time forced branching to make possible a full coverage of the instruction space spanned by the verification code/program. The aim is (1) to improve the verification simulation speed and (2) to get higher coverage rate for large core-base designs such as microprocessors or digital-signal-processing (DSP) products. A case study of a 32-bit RISC processor, used in a network system, is conducted. The application code for the processor (MCP, Myrinet control program) is used as a verification program. Despite the deviation from the valid software-reachable state of the system due to forced branching, a significant number of hard-to-reach hardware states (that can be reached only through the right mix of codes, often the code segments of an application software) are covered. Using the MCP program over 30% additional coverage is achieved with the proposed approach over ordinary code-based simulation for a fixed verification time. Further, compared to the conventional simulation approach, the proposed heuristic takes about 43% less compute-cycles to achieve same state coverage level.     

Cohesive Coverage Management: Simulation Meets Formal Methods

It has been advocated by many experts in design verification that the key to successful verification convergence lies in developing the verification plan with adequate formal rigor. Traditionally, the verification plans for simulation and formal property verification (FPV) are developed in different ways, using different formalisms, and with different coverage goals. In this paper, we propose a framework where the difference between formal properties and simulation test points is diluted by using methods for translating one form of the specification to the other. This allows us to reuse simulation coverage to facilitate formal verification and to reuse proven formal properties to cover simulation test points. We also propose the use of inline assertions in procedural (possibly randomized) test benches, and show that it facilitates the use of hybrid verification techniques between simulation and bounded model checking. We propose the use of promising combinations of formal methods presented in our earlier papers to shape a hierarchical verification flow where simulation and formal methods aim to cover a common design intent specification. The proposed flow is demonstrated using a detailed case study of the ARM AMBA verification benchmark. We believe that the methods presented in this work will stimulate new thought processes and ultimately lead to wider adoption of cohesive coverage management techniques in the design intent validation flow.     

基于覆盖率驱动的SoC验证技术研究

覆盖率数据是验证工程师判定SoC验证完备程度的定性度量,为SoC验证完全性提供了保障,指明了方向．文中以SoC总线仲裁器验证为例,对其结构覆盖率、功能覆盖率、断言覆盖率等多种覆盖率进行了全面的分析,然后根据覆盖率分析结果反馈到RTL设计代码和测试激励进行修正,直到验证的完整性满足设计的要求．     

IPOA组包功能的验证系统

介绍一种对IPOA应用中的组包功能进行RTL功能验证的系统。该验证系统可根据用户输入数据自动产生ATM信元作为激励 ,并对被测系统的输出进行自动验证。通过该验证系统大大提高了验证效率 ,缩短了仿真时间。同时 ,该系统产生的激励可对被测系统进行彻底的功能验证 ,提高了验证过程中代码覆盖率     

On Design Validation Using Verification Technology

Despite great advances in the area of Formal Verification during the last ten years, simulation is currently the primary means for performing design verification. The definition of an accurate and pragmatic measure for the coverage achieved by a suite of simulation vectors and the related problem of coverage directed automatic test generation are of great importance. In this paper we introduce a new set of metrics, called the Event Sequence Coverage Metrics (ESCMs). Our approach is based on a simple and automatic method to extract the control flow of a circuit so that the resulting state space can be explored for validation coverage analysis and automatic test generation. During simulation we monitor, in addition to state and transition coverage, whether certain control event sequences take place or not. We then combine formal verification techniques, using BDDs as the underlying representation, with traditional ATPG and behavioral test generation techniques to automatically generate additional sequences which traverse uncovered parts of the control state graph, or exercise an uninstantiated control event sequence.     

Functional verification of instruction processing units through control flow modeling

The design verification of state-of-the-art high-performance microprocessors has become a significant challenge for test engineers. Deep pipelines, multiple execution units, out-of-order and speculative execution techniques, typically found in such microprocessors, contribute much to this complexity. Conventional methods, which treat the processor as a logic state machine or apply architectural level tests, fail to provide coverage of all possible corner cases in the design. This paper presents a functional verification method for modern microprocessors, which is based on innovative models of the microprocessor architecture, intended to cover the testing of all corner cases. In order to test the models presented in this work, an architecture independent coverage measurement system has been developed. The models were tested with both random code and real world applications in order to determine which of the two achieves higher coverage.