RFI-induced distortion in switched-capacitor circuits

The errors which are induced by radio-frequency interference (RFI) in switched-capacitor (SC) circuits are discussed and the main role played by the distortion of MOS switches in the on-state is highlighted. Furthermore, a new simple analytical model, which enables one to predict RFI-induced errors in SC circuits is proposed and it is validated by the comparison of its predictions with time-domain computer simulation results.     

MOSFET-only switched-capacitor circuits in digital CMOS technology

Design techniques are described for the realization of precision high linearity switched-capacitor (SC) stages constructed entirely from MOS transistors. The proposed circuits use the gate-to-channel capacitance of MOSFET's for realizing all capacitors. As a result, they can be fabricated in any inexpensive basic digital CMOS technology, and the chip area occupied by the capacitors can be reduced. A number of different SC stages have been designed and fabricated using the proposed techniques. These included SC amplifiers, gain/loss stages, and data converters. Both the simulations and the experimental results obtained indicate that very high linearity (comparable to that achieved using analog fabrication processes with two poly-Si layers) can be achieved in these circuits using basic CMOS technology     

Simple method for obtaining the equations of switched-capacitor circuits

A systematic method for writing the time-domain equations of switched-capacitor circuits is presented. By following four well-defined steps, as many linearly independent equations are obtained as there are capacitors in the circuit. The method is especially well suited for hand analysis, and relies on the intuitively appealing concept of identifying physical regions where charge is trapped.     

Design for testability and DC test of switched-capacitor circuits

The authors present a design for testability (DFT) technique for switched-capacitor circuits. The principle is to reconfigure the SC circuit so that it realises a cascade of DC voltage amplifiers in which all capacitors are represented in a simple form. Then, the transfer function becomes a product of the ratio of two capacitors and the sensibility of the DC gain to each capacitor is close to unity. Consequently, a simple test with partial diagnosis is realised with some DC voltage stimuli and gives an accurate test result at the output of the last voltage amplifier     

A tutorial on computer-aided analysis of switched-capacitor circuits

In this paper, various formulation techniques for analyzing switched-capacitor circuits have been described and compared. Some basic pcoperties of the time-, z-, and frequency-domain solutions have been presented. Analysis techniques for handling nonideal op-amps, switch resistances, and noise and distortion effects are discussed. Methods for sensitivity analysis have been briefly mentioned and, finally, an overview of computer-aided analysis techniques has been given.     

Design of CMOS three-stage amplifiers for fast-settling switched-capacitor circuits

In this paper, a time-domain design procedure for fast-settling three-stage amplifiers is presented. In the proposed design approach, the amplifier is designed to settle within a specific time with a given settling accuracy and circuit noise budget by optimizing both the power consumption and silicon die area. Both linear and nonlinear settling regions of three-stage amplifiers are considered and optimal values of the amplifier stages transconductance and compensation capacitors are obtained using the genetic algorithm optimization. Detailed design equations are provided and circuit level simulation results using a 90 nm CMOS technology are presented to evaluate the usefulness of the proposed design scheme respected to the previously reported design approaches.     

Simple approach to analysis of switched-capacitor circuits with nonideal op-amps

A possible method for the simulation of nonideal op-amps with a finite gain and bandwidth by means of an equivalent SC circuit, containing ideal components, is presented. The approach is extended by the case of an op-amp with non-switched input SC building blocks.     

Modelling noise and delay in VLSI circuits

New models for estimating delay and noise in VLSI circuits, based on closed form expressions for the first and second moment of the impulse response in coupled RC trees are reported. The effect of crosstalk on delay and noise can be accurately estimated with a complexity only marginally higher than the Elmore delay.     

On the optimal design of switched-capacitor filter circuits for analog and mixed-signal integrated circuit realization

This contribution describes developments in the use of numerical optimization techniques as part of a package whose function is to generate silicon-level layout for general analog functional modules from high-level specifications. The investigation is using switched-capacitor filters as a case study that is representative, in terms of its associated physical layout problems, of many classes of analog circuits.     

Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doubler

Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doublers based on cross-coupled structure are presented. The intuitive analysis of the shoot-through current and switching noise generation processes in the doubler is first reported. Break-before-make mechanism is adopted to minimize the shoot-through current, thereby greatly reducing the no-load supply current dissipation and improving the light-load power efficiency of the voltage doubler. In addition, by employing gate-slope reduction technique at the serial power transistor during turn-on, the switching noise of the voltage doubler is significantly lowered. Two voltage doublers with and without the proposed circuit techniques have been fabricated in a 0.6-/spl mu/m CMOS process. Experimental results verify that the total supply current at no-load condition of the proposed voltage doubler is reduced by two fold and its switching noise is decreased by 2.5 times.     

Computation of harmonic comb filter weights

Harmonic comb filters are characterized in the frequency domain by notches arranged at equal intervals, and centered about DC. For a finite impulse response harmonic comb filter, the characteristic polynomial has its roots on the unit circle at equal angular intervals, symmetrically about 1+j0. A simple formula for the coefficients of such a polynomial and for their derivatives with respect to the frequency interval is presented. This result is applied as well to the computation of Butterworth filter parameters     

A single-stage operational amplifier with enhanced transconductance and slew rate for switched-capacitor circuits

The DVB-T2 standard for digital terrestrial broadcasting supports the use of quadrature amplitude modulation constellations where the constellation points are rotated in the I–Q plane. This combined with a cyclic delay of the Q component provides improved performance in some fading channels. The complexity of the optimal demapping process for rotated constellations is however significantly higher than for non-rotated constellations. This makes the DVB-T2 demapper one of the most computationally complex parts of a receiver. In this article, we examine possible simplifications of the demapping process suitable for implementation on a general purpose computer containing a modern graphics processing unit (GPU). Furthermore, we measure the performance in terms of throughput, as well as accuracy, of the implemented algorithms. The implementations are designed to interface efficiently to a previously implemented real-time capable GPU-based low-density parity-check channel decoder.     

Least-square estimation of average power in digital CMOS circuits

The estimation of average-power dissipation of a circuit through exhaustive simulation is impractical due to the large number of primary inputs and their combinations. In this work, two algorithms based on least square estimation are proposed for determining the average power dissipation in complementary metal-oxide-semiconductor (CMOS) circuits. Least square estimation converges faster by attempting to minimize the mean square error value during each iteration. Two statistical approaches namely, the sequential least square (SLS) estimation and the recursive least square estimation are investigated. The proposed methods are distribution independent in terms of the input samples, unbiased and point estimation based. Experimental results presented for the MCNC'91 and the ISCAS'89 benchmark circuits show that the least square estimation algorithms converge faster than other statistical techniques such as the Monte Carlo method and the DIPE     

Realistic scalability of noise in dynamic circuits

The usage of noise-sensitive dynamic circuits has become commonplace due to speed and area requirements, making the noise issue even more prominent. This paper focuses on the trends of coupling and its effects on dynamic circuits. It presents closed form analytical solutions for noise, as well as noise tolerance metrics for dynamic circuits. These solutions are within 5% of dynamic simulations. It is shown that not all scaling trends are negative for noise, and that the scaling down of supply voltage and increasing frequency, help improve certain aspects of the noise immunity of dynamic circuits. Most of the works treated the noise immunity and the noise content separately. This paper introduces an analysis of noise scalability by looking at the noise immunity and the noise content simultaneously.     

Reduction of popcorn noise in integrated circuits

Popcorn (burst) noise continues to deteriorate the operation of linear IC devices. Reduction of popcorn noise by a few simple modifications in the manufacturing process is reported in this paper. Annealing in an HC1 atmosphere to getter metal impurities and slow pulling after emitter deposition to diminish stress-induced junction defects appear to reduce the popcorn noise significantly.     

A new simple method for analysing of thermal noise in switched-capacitor filters

Thermal noise is one of the most important challenges in analogue integrated circuits design. This problem is more crucial in switched-capacitor (SC) filters due to the aliasing effect of wide-band thermal noise. In this article, a new simple method is proposed for estimating the power spectrum density of output thermal noise in SC filters, which have acceptable accuracy and short running time. In the proposed method, first using HSPICE simulator, accurate value of accumulated sampled noise on sampler capacitors in each clock state is achieved. Next, using difference equations of the SC filter, frequency response of the SC filter is shaped by time domain analysis. Based on the proposed method, a SC low-pass filter and a second-order SC band-pass filter are analysed. The results are validated by comparing to the previously measured data.     

Matrix synthesis of harmonic oscillator circuits †

A synthesis method is given for oscillators of the type that may be represented as a single two-port network with a transmission matrix [T]=[A, B;C, D] having its output fed directly back to its input, thereby imposing the condition:

A+D?Δ?1=0,

where ΔΞAD? BC. To obtain sustained oscillation at a single real frequency ω₀ this condition is interpolated at ω₀ by a polynomial equation in s. By identifying the two equations a set of functional values may be obtained for the [T] matrix elements. Four sots of basic circuit are developed in detail from the quadratic or cubic polynomial equation, with Δ = 0 or Δ≠0. Those having Δ = 0 arc well-known forms, but those with Δ =0 are novel.     

A programmable clock generator that uses noise shaping and itsapplication in switched-capacitor filters

A programmable digital clock generator that produces a wide range of clock frequencies with fine resolution is described. The clock generator consists of a noise-shaping control loop and a number-controlled oscillator. The generated clock has a time-varying period. When this clock is used as the sampling clock in a switched-capacitor filter (SCF) to set its frequency response, the time-varying period causes nonuniform sampling, which is acceptable under certain conditions that are described. Measured performance of a 2-μm CMOS implementation of the clock generator is presented. Also, measured data for the clock generator driving two SCF's are reported