Flip chip on board solder joint reliability analysis using 2-D and3-D FEA models

This study investigates the effects of employing different two-dimensional (2-D) and three-dimensional (3-D) finite element analysis (FEA) models for analyzing the solder joint reliability performance of a flip chip on board assembly. The FEA models investigated were the 2-D-plane strain, 2-D-plane stress, 3-D-1/8th symmetry and 3-D-strip models. The different stress and strain responses generated by the four different FEA models were applied to various solder joint low cycle fatigue life prediction relationships. The investigation shows that the 2-D-plane strain and 2-D-plane stress models gave the highest and lowest solder joint strains, respectively. The 3-D-strip and 3-D-1/8th symmetry model results fall in between the 2-D-plane strain and 2-D-plane stress model results. The 3-D-1/8th symmetry model agrees better with the 2-D-plane strain model, while the 3-D-strip model agrees better with the 2-D-plane stress model results. The results for the fatigue life prediction analyses also show similar trends     

Flip chip solder joint reliability analysis using viscoplastic and elastic-plastic-creep constitutive models

Both elastic-plastic-creep and viscoplastic constitutive models may be used for inelastic deformation analysis of solder joints. In this paper, a phenomenological approach using elastic-plastic-creep analysis and an Anand viscoplastic model is reported for solder joint reliability. Flip chip soldered assemblies with 63Sn-37Pb solder joints were subjected to a thermal cyclic loading condition of -40 to +125/spl deg/C to assess the solder joint fatigue performance. In the finite-element modeling, the viscoplastic strain energy density per cycle obtained from the viscoplastic analysis is compared with the inelastic (plastic and creep) strain energy density per cycle calculated from the elastic-plastic-creep analysis. The inelastic (plastic+creep and viscoplastic) strain energy density extracted from the finite-element analysis results, at the critical solder joint location, were used as a failure parameter for solder fatigue models employed. It was found that the predicted solder joint fatigue life has a better correlation to the first failure or first-time-to-failure result.     

Board level reliability assessment of chip scale packages

A large program had been initiated to study the board level reliability of various types of chip scale package (CSP). The results on six different packages are reported here, which cover flex interposer CSP, rigid interposer CSP, wafer level assembly CSP, and lead frame CSP. The packages were assembled on FR4 PCBs of two different thicknesses. Temperature cycling tests from −40°C to +125°C with 15 min dwell time at the extremes were conducted to failure for all the package types. The failure criteria were established based on the pattern of electrical resistance change. The cycles to failure were analyzed using Weibull distribution function for each type of package. Selected packages were tested in the temperature/humidity chamber under 85°C/85%RH for 1000 h. Some assembled packages were tested in vibration condition as well. In all these tests, the electrical resistance of each package under testing was monitored continuously. Test samples were also cross-sectioned and analyzed under a Scanning Electronic Microscope (SEM). Different failure mechanisms were identified for various packages. It was noted that some packages failed at the solder joints while others failed inside the package, which was packaging design and process related.     

High-temperature reliability of Flip Chip assemblies

Flip Chip technology has been widely accepted within microelectronics as a technology for maximum miniaturization. Typical applications today are mobile products such as cellular phones or GPS devices. For both widening Flip Chip technology’s application range and for addressing the automotive electronics’ volume market, developing assemblies capable of withstanding high temperatures is crucial. A typical scenario for integrating electronics into a car is a control unit within the engine compartment, where ambient temperatures are around 150 °C, package junction temperatures may range from 175 °C to 200 °C and peak temperatures may exceed these values.If Flip Chip technology is used under harsh environment conditions, it is clear that especially the polymeric materials, i.e., underfiller, solder mask or the organic substrate base material, are challenged. Generally, the developmental goal for encapsulants compatible with high-temperature applications are materials with high T_g and low degradation even at temperatures >200 °C.According to these demands, a test group of advanced underfill encapsulants has been used for assembling Flip Chip devices. These test vehicles were built using lead-free and lead-containing solders such as SnAgCu and eutectic PbSn and standard FR4 substrates, for evaluating the reliability potential of state-of-the-art underfillers. Material analysis is performed for studying both material degradation as well as temperature-dependent thermo-mechanical and adhesive properties. For assessing reliability, temperature cycling is performed with different maximum test temperatures ranging from 150 °C to 175 °C. The device status is intermediately analyzed by using electrical measurement for detecting bond integrity and acoustomicroscopy for determining the occurrence and growth of delaminations. Extensive failure analysis is added to investigate device failure mechanisms, especially related to the respective test temperature.In summary, an empirical status of the high-temperature potential of state-of-the-art underfillers and material combinations is attained and an outlook on future demands and developments is provided.     

现代微光电子封装中的倒装焊技术

结合我们设计制作的倒装焊光电子器件-智能像素面阵,对倒装焊的工艺过程作了简要的介绍.该面阵采用铟做凸点材料,制作了输入输出数达64×64的凸点电极阵列,并采用回流焊的方式,将光电调制器面阵与对应的处理电路芯片对准后加热回流实现焊接,形成输入输出引线间距只有80μm的面阵器件.     

现代微光电子封装中的倒装焊技术

结合我们设计制作的倒装焊光电子器件—智能像素面阵 ,对倒装焊的工艺过程作了简要的介绍。该面阵采用铟做凸点材料 ,制作了输入输出数达 6 4× 6 4的凸点电极阵列 ,并采用回流焊的方式 ,将光电调制器面阵与对应的处理电路芯片对准后加热回流实现焊接 ,形成输入输出引线间距只有 80 μm的面阵器件     

Flip chip attachment on flexible LCP substrate using an ACF

In this study the reliability of a flip chip bonding process using anisotropic conductive adhesives (ACA) was evaluated. The flexible substrates used were made of liquid crystal polymer (LCP), which is an interesting new material having excellent properties for flexible printed circuit boards. The test samples were prepared using two different anisotropic conductive films (ACF) having the same fast-cure resin matrix, but different conductive particles. The reliability of the test samples was studied by accelerated environmental tests. In the constant humidity test the temperature was 85 °C and the relative humidity was 85%. The temperature cycling test was carried out between temperatures of −40 °C and 85 °C. To determine the exact time of a failure the resistance of each test sample was measured using continuous real-time measurement. A clear difference between the behaviour of the conductive particles was seen in the test. While the adhesive having polymer particles had only one failure during testing, the adhesive having nickel particles had a considerable number of failures in both tests. Cross sections of the samples were made to analyze the failure mechanisms.     

印制板上形成凸块的倒芯片安装技术

该文概述了在印制板(PWB)上形成倒芯片安装用的凸块的方法和工艺条件,并进行可靠性试验和评价,确认了Boss B~2it 技术可以实现低成本倒芯片安装。     

芯片封装互连新工艺热超声倒装焊的发展现状

介绍了一种芯片封装互连新工艺热超声倒装芯片连接工艺.在比较当前多种芯片封装方式的基础上,总结了这一工艺的特点及优越性,并详细论述了当前这一工艺的技术进展与理论研究状况,指出该工艺是芯片封装领域中具有发展潜力的新工艺.     

Effects of underfill material properties on the reliability ofsolder bumped flip chip on board with imperfect underfill encapsulants

Three different types of underfill imperfections were considered; i.e., (1) interfacial delamination between the underfill encapsulant and the solder mask on the PCB (crack initiated at the tip of underfill fillet), (2) interfacial delamination between the chip and the underfill encapsulant (crack initiated at the chip corner), and (3) the same as (2) but without the underfill fillet. Five different combinations of coefficient of thermal expansion (CTE) and Young's modulus with the aforementioned delaminations were investigated. A fracture mechanics approach was employed for computational analysis. The strain energy release rate at the crack tip and the maximum accumulated equivalent plastic strain in the solder bumps of all cases were evaluated as indices of reliability. Besides, mechanical shear tests were performed to characterize the shear strength at the underfill-solder mask interface and the underfill-chip passivation interface. The main objective of the present study is to achieve a better understanding in the thermo-mechanical behavior of flip chip on board (FCOB) assemblies with imperfect underfill encapsulants     

宇航用微波芯片电容器电极镀层可靠性评价方法研究

微波芯片电容器作为一种新型的电容器,已被广泛应用于宇航,而国军标和行业标准中目前并无适用的评价方法。针对宇航用芯片电容器的应用方式和失效模式,设计了一套宇航用微波芯片电容器镀层可靠性的评价方法,用以评价其可靠性是否满足宇航应用需求。以国产芯片电容器为例对该评价方法进行验证。结果表明,该评价方法可有效评价和验证芯片电容器电极镀层的可靠性。     

Impact of probing procedure on flip chip reliability

Probe-after-bump is the primary probing procedure for flip chip technology, since it does not directly contact the bump pad, and involves a preferred under bump metallurgy (UBM) step coverage on the bump pads. However, the probe-after-bump procedure suffers from low throughputs and high cost. It also delays the yield feedback to the fab, and makes difficult clarification of the accountability of the low yield bumped wafer between the fab and the bumping house. The probe-before-bump procedure can solve these problems, but the probing tips may over-probe or penetrate the bump pads, leading to poor UBM step coverage, due to inadequate probing conditions or poor probing cards. This work examines the impact of probing procedure on flip chip reliability, using printing and electroplating bumpings on aluminum and copper pads. Bump height, bump shear strength, die shear force, UBM step coverage, and reliability testing are used to determine the influence of probing procedure on flip chip reliability. The experimental results reveal that bump quality and reliability test in the probe-before-bump procedure, under adequate probing conditions, differ slightly from the corresponding items in the probe-after-bump procedure. UBM gives superior step coverage of probe marks in both probe-before-bump and probe-after-bump procedures, implying that UBM achieves greater adhesion and barrier function between the solder bump and the bump pad. Both printing and electroplating bump processes slightly influence all evaluated items. The heights of probe marks on the copper pads are 40–60% lower than those on the aluminum pads, indicating that the copper pad enhances UBM step coverage. This finding reveals that adequate probing conditions of the probe-before-bump procedure are suited to sort flip chip wafers and do not significantly affect bump height, bump shear strength, die shear force, or flip chip reliability.     

The cellular phone industry in Malaysia: toward IMT-2000

Explosive growth of the cellular phone industry in Malaysia has been witnessed in the 1990s. Eight nationwide cellular phone operators with different technology bases exist in a single market. This article provides an overview of the telecommunications industry, especially the cellular phone sector, and also the activities on IMT-2000 in Malaysia     

The physics of determining chip reliability

We have indicated the necessity for using statistical models to determine the reliability of deep-submicron MOSFETs. We have presented a methodology by which the reliability can be determined from short-time tests if the defect generation statistics are linked to variations in defect activation energies. We have shown that enhanced latent failures follow from our model for deep-submicron MOSFETs. Therefore, more stringent reliability standards are required, which can be validated by the use of short-time tests. Our model provides the means to calculate these novel reliability demands quantitatively     

Effects of build-up printed circuit board thickness on the solderjoint reliability of a wafer level chip scale package (WLCSP)

The creep analyses of solder-bumped wafer level chip scale package (WLCSP) on build-up printed circuit board (PCB) with microvias subjected to thermal cyclic loading are presented. The emphasis of this study is placed on the effects of the thickness of the PCB with a microvia build-up layer on the solder joint reliability of the WLCSP assembly. The 62Sn-2Ag-36Pb solder joints are assumed to follow the Garofalo-Arrhenius creep constitutive law. The shear stress and creep shear strain hysteresis loops, shear stress range, creep shear strain range, and creep strain energy density range at different locations in the corner solder joint are presented for a better understanding of the thermal-mechanical behaviors of the solder-bumped WLCSP on build-up PCB with microvias. It is found that, due to the large coefficient of thermal expansion of the build-up resin, the effects of thickness of the PCB with microvia build-up layer become much more significant than that without the microvia build-up layer     

基于多核手机芯片的TD-SCDMA非信令模式下行同步方案

随着TD-SCDMA无线通信系统商用的成熟,研究多核手机芯片的非信令模式符合终端测试发展需求。通过对TD-SCDMA下行同步过程的研究,设计了快速的非信令模式下行同步实现方案,同时结合多核手机芯片的特点充分优化下行同步过程的实现。实现结果表明,该下行同步方案处理时延40 μs左右,频偏估计结果的均值和标准差分别稳定在10 Hz、32 Hz左右,能够用于简化多核终端生产测试过程,具有一定的工程应用价值。     

Lead-free chip scale packages: assembly and drop test reliability

Three underfill options compatible with lead-free assembly have been evaluated: capillary underfill, fluxing underfill, and corner bond underfill. Chip scale packages (CSPs) with eutectic Sn/Pb solder were used for control samples. Without underfill, lead-free and Sn/Pb eutectic drop test results were comparable. Capillary flow underfills, dispensed and cured after reflow, are commonly used in CSP assembly with eutectic Sn/Pb solder. With capillary flow underfill, the drop test results were significantly better with lead-free solder assembly than with Sn/Pb eutectic. Fluxing underfill is dispensed at the CSP site prior to CSP placement. No solder paste is printed at the site. The CSP is placed and reflowed in a standard reflow cycle. A new fluxing underfill developed for compatibility with the higher lead-free solder reflow profiles was investigated. The fluxing underfill with lead-free solder yielded the best drop test results. Corner bond underfill is dispensed as four dots corresponding to the four corners of the CSP after solder paste print, but before CSP placement. The corner bond material cures during the reflow cycle. It is a simpler process compared to capillary or fluxing underfill. The drop test results with corner bond were intermediate between no underfill and capillary underfill and similar for both lead-free and Sn/Pb eutectic solder assembly. The effect of aging on the drop test results with lead-free solder and either no underfill or corner bond underfill was studied. Tin/lead solder with no underfill was used for control. This test was to simulate drop performance after the product has been placed in service for some period of time. There was degradation in the drop test results in all cases after 100 and 250 h of storage at 125/spl deg/C prior to the drop test. The worst degradation occurred with the lead-free solder with no underfill.     

Parametric reliability analysis of no-underfill flip chip package

This research proposes a parametric analysis for a flip chip package with a constraint-layer structure. Previous research has shown that flip-chip type packages with organic substrates require underfill for achieving adequate reliability life. Although underfill encapsulant is needed to improve the reliability of flip chip solder joint interconnects, it will also increase the difficulty of reworkability, increase the packaging cost and decrease the manufacturing throughput. This research is based on the fact that if the thermal mismatch between the silicon die and the organic substrate could be minimized, then the reliability of the solder joint could be accordingly enhanced. This research proposes a structure using a ceramic-like material with CTE close to silicon, mounted on the backside of the substrate to constrain the thermal expansion of the organic substrate. The ceramic-like material could reduce the thermal mismatch between silicon die and substrate, thereby enhancing the reliability life of the solder joint. Furthermore, in order to achieve better reliability design of this flip chip package, a parametric analysis using finite element analysis is performed for package design. The design parameters of the flip chip package include die size, substrate size/material, and constraint-layer size/material, etc. The results show that this constraint-layer structure could make the solder joints of the package achieve the same range of reliability as the conventional underfill material. More importantly, the flip chip package without underfill material could easily solve the reworkability problem, enhance the thermal dissipation capability and also improve the manufacturing throughput     

晶体管电流增益的表达式修正及电流增益在可靠性评估中的应用

Considering the impacts of ideal factor n, VBE and band gap changes with the temperature on current gain, the current gain expression has been corrected to make the results closer to the actual test. Besides, the accelerating lifetime study method in the constant temperature-humidity stress is used to estimate the reliability of the same batch transistors. Applying the revised findings from the expression, the current gains before and after the test are compared and analyzed, and, according to the degradation data of the current gain, the transistor lifetimes in the test stress are respectively extrapolated in the different failure criteria.     

Optical interconnects at the chip and board level: challenges andsolutions

This paper discusses short-distance optical interconnects for general-purpose distributed digital systems. We describe the technology required to optically interconnect elements that are distributed across multiple packaging layers. This includes chips on a board, boards in a backplane, and shelves within a bay. The focus of this paper will be on technology capable of supporting high-data-rate, two-dimensional, optical communication using two-dimensional parallel optical interconnects