A 1000 FPS at 128/spl times/128 vision processor with 8-bit digitized I/O

This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple data (SIMD) computing architectures. This chip, implemented in a 0.35-/spl mu/m fully digital CMOS technology, contains /spl sim/ 3.75 M transistors and exhibits peak performance figures of 330 GOPS (8-bit equivalent giga-operations per second), 3.6 GOPS/mm/sup 2/ and 82.5 GOPS/W. It includes structures for image acquisition and for image processing, meaning that it does not require a separate imager for operation. At the sensory side, integration and log-compression sensing circuits are embedded, thus allowing the chip to handle a large variety of illumination conditions. At the processing plane, analog and digital circuits are employed whose parameters can be programmed and their architecture reconfigured for the realization of software-coded processing algorithms. The chip provides, and accepts, 8-bit digitized data through a 32-bit bidirectional data bus which operates at 120 MB/s. Experimental results show that frame rates of 1000 frames per second (FPS) can be achieved under room illumination conditions; applications using exposures of about 50 /spl mu/s have been recently reached by using special illumination setups. The chip can capture an image, run approximately 150 two-dimensional linear convolutions, and download the result in 8-bit digital format, in less than 1 ms. This feature, together with the possibility of executing sequences of user-definable instructions (stored on a full-custom 32-kb on-chip memory), and storing intermediate results (up to 8 grayscale images) makes the chip a true general-purpose sensory/processing device.     

A VLSI chip set for a large-scale parallel inference machine: PIM/m

The authors present three VLSI chips-a processor (PU) chip, a cache memory (CU) chip, and a network control (NU) chip-for a large-scale parallel inference machine. The PU chip has been designed to be adapted to logic programming languages such as PROLOG. The CU chip implements a hardware support called `trial buffer' which is suitable for the execution of the PROLOG-like languages. The NU chip makes it possible to connect 256 processing elements in a mesh network. The parallel inference machine (PIM/m) runs a PROLOG-like network-based operating system called PIMOS as well as many applications and has a peak performance of 128 mega logical inferences per second (MLIPS). The PU chip containing 384000 transistors is fabricated in a 0.8 μm double-metal CMOS technology. The CU chip and the NU chip contain 610000 and 329000 transistors, respectively. They are fabricated in a 1.0 μm double-metal CMOS technology. A cell-based design method is used to reduce the layout design time     

Low-power InP-HEMT switch ICs integrating miniaturized 2/spl times/2 switches for 10-Gb/s systems

This paper presents a wideband cold-FET switch with virtually zero power dissipation. The use of InP HEMTs with a low R/sub on//spl middot/C/sub off/ product enables us to configure a DC-to-over-10-GHz single-pole double-throw (SPDT) switch without using a shunt FET. The series-FET configuration offers a logic-level-independent interface and makes possible positive control voltage operation in spite of using depletion-mode FETs. A miniaturized 2/spl times/2 switch using two SPDT switches yields an insertion loss of less than 1.16 dB and isolation of more than 21.2 dB below 10 GHz, which allows us to increase the scale of the switch in a single chip easily. The add-drop operation combining two 2/spl times/2 switches in a single chip and a 4/spl times/4 switch IC integrating four 2/spl times/2 switches are presented. The packaged ICs achieve error-free operation up to 12.5 Gb/s with either positive or negative logic-level input. Extremely fast switching of /spl sim/140 ps is also successfully demonstrated.     

A 5-bit building block for 20 MHz A/D converters

Describes a monolithic, fully parallel 5-bit A/D converter. The chip is fabricated using a standard metal-gate enhancement depletion NMOS technology with 7 /spl mu/m minimum features. The chip contains 31 strobed comparators, latches, combinational logic, a 5/spl times/31 bit ROM, TTL buffers and a 4-bit DAC. This makes it a building block for two-step parallel 8-bit A/D converters. Maximum conversion rate is 20 MHz and DC linearity is better than /SUP 1///SUB 4/ LSB for 80 mV quantization step size.     

基于DTW/SVM的语音识别系统在DSP中的实现

采用动态时间归正算法(DTW)和支持向量机(SVM)相结合产生一个新的基于径向基函数的DTW核函数实现语音识别,该方法在小词汇量及孤立词识别方面相对传统的隐马尔可夫模型有较大优势。为了满足语音识别系统对实时性和便携性的要求,提出了基于DTW/SVM的混合方法在TMS320C6711DSP芯片中实现的应用研究;给出了语音识别系统的原理框图,其中采用Mel倒谱系数为语音特征参数,应用了可变窗长端点检测技术;阐述了DSP设计中系统的软硬件设计方案及具体的接口电路,该系统使得语音识别更为快速便捷,并且具有一定的通用性。     

555时基芯片及其在A/D转换中的应用

介绍了555时基芯片的功能、主要特性,以及555芯片在0～10Hz、0～10 kHz、10 Hz～10 kHz V/F(电压/频率)转换电路及其在测量中的应用,并给出了实验数据,结果表明,由555芯片组成的转换电路具有价格低、精度高、线性好等特点.     

脉冲跨周期调制开关电源的特性研究

对脉冲跨周期调制(PSM)开关电源的特性进行了研究。这类开关电源的效率比常规的脉冲宽度调制(PWM)高，且基本上与负载无关；通过状态机对负载进行离散侦测以及电流极限模糊控制模式，提高了电源的响应度；通过频率抖劝，降低了开关电源的电磁干扰影响。这类开关电源集远程遥控关断、外部可编程、智能保护、同步等功能于一体，隐现了功率系统级发展的一种途径。     

Ultra CSPTM-a wafer level package

There has been a significant amount of work over the past five years on chip scale packaging. The majority of this work has been an extension of conventional integrated circuit (IC) packaging technology utilizing either wire bonders or tape automated bonding (TAB)-type packaging technology. Handling discrete devices during the IC packaging for these type of chip scale packages (CSPs) has resulted in a relatively high cost for these packages. This paper reports a true wafer level packaging (WLP) technology called the Ultra CSP^TM. One advantage of this WLP concept is that it uses standard IC processing technology for the majority of the package manufacturing. This makes the Ultra CSP ideal for both insertion at the end of the wafer fab as well as the facilitation of wafer level test and burn-in options. This is especially true for dynamic random access memory (DRAM) wafers. Wafer level burn-in and wafer level processing can be used for DRAM and other devices as a way to both reduce cost and improve cycle time. Thermal cycling results for Ultra CSPs with a variety of package sizes and input/output (I/O) counts are presented. These test vehicles, assembled to FR-4 boards without underfill, cover a range of footprints typical of flash memory, DRAM and other devices. The electrical and thermal performance characteristics of the Ultra CSP package technology are discussed     

SG32525芯片在开关(逆变)电源中的应用

在研制开关电源和后备式UPS(不间断电源)的工程实践中,为提高其转换效率,减少外围元器件,减小体积,并提高长时间工作的可靠性与PWM(脉宽调制)的控制精度,对新型PWM集成芯片SG3525的功能特点、控制特性及外围电路进行了研究。讨论了该芯片在UPS逆变电源和开关稳压电源中的应用,利用该芯片设计并制作了高效率的开关电源与UPS逆变电源。     

Design of a cycle-efficient 64-b/32-b integer divisor using a table-sharing algorithm

In new generations of microprocessors, the superscalar architecture is widely adopted to increase the number of instructions executed in one cycle. The division instruction among all of the instructions needs more cycles than the rest, e.g., addition and multiplication. This makes the division instruction an important cycles-per-instruction figure for modern microprocessors. In this paper, a radix-16/8/4/2 divisor is proposed, which uses a variety of techniques, including operand scaling, table partitioning, and, particularly, table sharing, to increase performance without the cost of increasing complexity. A physical chip using the proposed method is implemented by 0.35-/spl mu/m single poly four metal (1P4M) CMOS technology. The testing measurement shows that the chip can execute signed 64-b/32-b integer division between 3-13 cycles with a 80-MHz operating clock.     

A comparison of system performance using two different chip pulsesin multiple-chip-rate DS/CDMA systems

This paper describes a comparison of system performance using two different chip waveforms of spreading sequences in multiple-chip-rate (MCR) direct-sequence (DS)/code-division multiple-access (CDMA) systems. The chip pulses used in this study are closely related to the characteristics of output filter employed at transmitter. In general, the chip waveform is an important factor to determine the link performance. The raised cosine chip pulse with a roll-off factor of α will be adopted for IMT-2000 systems in order to reduce both the intersymbol effect and the spectral width of the modulated signal. However, due to the complexity of obtaining quantitative results on the performance of MCR-DS/CDMA systems, rectangular chip pulses are mainly utilized in performance analysis. Therefore, it is necessary to investigate the effect of the chip pulses used, i.e., a rectangular and a raised cosine chip pulses on system performance in order to evaluate MCR-DS/CDMA systems accurately. Thus, the effect of the chip pulses used on the performance in MCR-DS/CDMA systems is investigated in terms of the system capacity and blocking probability. It is shown that the system using a raised cosine chip pulse (i.e., RC system) supports at least 80% more capacity and 57% more traffic than that using a rectangular chip pulse (i.e., R system)     

基于TPS5461X的FPGA同步降压DC／DC供电模块设计

以同步降压DC／DC控制器芯片TPS54615、TPS54616为核心,设计了一款FPGA（现场可编程门阵列）供电模块。该模块充分利用了内部集成FETs、效率高的特点,使系统可以大大提高空间利用率,硬件结构简单。文中介绍了TPS54616的主要性能,并重点阐述了基于TPS54616的FPGA供电模块的电路设计和PCB设计的方法,并生产出样机,目前在产品中得到应用。     

An 8K/spl times/8 bit static MOS RAM fabricated by n-MOS/n-well CMOS technology

A 64 kbit fully static MOS RAM which contains about 402500 elements on the chip area of 5.44/spl times/5.80 mm has been designed. The memory cell is a basic cross-coupled flip-flop with four n-MOSFETs and two polysilicon load resistors. The memory cell size is decreased to 16/spl times/19 /spl mu/m (304 /spl mu/m/SUP 2/) by using advanced n-MOS technology with double-level polysilicon films and photolithography of 2 /spl mu/m dimensions. By applying n-well CMOS technology fabricated on a high-resistivity p-type silicon substrate to peripheral circuits of the RAM, high performance characteristics with high speed access times and low power dissipation are obtained. The RAM is designed for single 5 V operation. Address and chip select access times are typically 80 ns. Power dissipation in the active and standby mode is typically 300 and 75 mW, respectively.     

PDMS微流控光纤芯片的研制

用集成在芯片上的光纤作为激发光源,可使激发光斑的大小与微流控沟道的深度尺寸相接近,提高了检测灵敏度,省去了光学聚焦系统.利用二次曝光的方法制作了PDMS光纤芯片,实现了光纤与沟道的对准.对PDMS光纤芯片的加工工艺、封装方法和结构特征进行了探讨.用所制作的芯片对FITC（异硫氰酸荧光素）和以FITC标记的氨基酸进行了检测,结果证明了该芯片的可行性.     

A complete monolithic sample/hold amplifier

A monolithic sample/hold amplifier is described which includes the holding capacitor on the chip. System design considerations and tradeoffs are discussed, as well as the circuit design details. High performance is achieved by the use of a process which produces bipolar transistors and p-channel silicon-gate FET's (SIGFET's) on the same chip. Performance characteristics obtained include an acquisition time of 10 /spl mu/s (20-V step), an aperture delay time of 80 ns, and a droop rate of 30 mV/s.     

A 220-mm2, four- and eight-bank, 256-Mb SDRAM withsingle-sided stitched WL architecture

A 220-mm², 256-Mb SDRAM has been fabricated in fully planarized 0.22-μm CMOS technology with buried strap trench cell. The single-sided stitched word-line (WL) architecture employs asymmetric block activation and shared row decoders to realize 86.7% cell/chip-length efficiency (57.3% cell/chip efficiency). A staggered WL driver arrangement makes it possible to build the drivers on a 0.484-μm WL pitch in limited space. An intraunit address increment pipeline scheme having two logical 8-Mb arrays within one physical 16-Mb unit results in a burst frequency up to 200 MHz for single data rate, while allowing four- and eight-bank organizations. A data rate of 270 Mbits/s was confirmed with a 135-MHz frequency doubling test mode. Single-ended addresses and a single ended read-write-drive bus reduce the ICC₄ current to ~90 mA for 100-MHz seamless burst operation. A detailed shmoo analysis demonstrates address-access time of 13.5 ns and clock-access time of 5 ns. This design also uses a selectable row domain and divided column redundancy scheme that repairs up to ~1400 faults/chip with only 8% chip overhead     

A 1.5 V CMOS 4-bit microcomputer needs only 100 /spl mu/W

Describes a new 4-bit microcomputer fabricated using a low-power silicon gate CMOS process and working from a supply voltage down to 1.2 V. The /spl mu/C can directly drive up to seven 3:1 multiplexed LCD digits, scan up 48 keys, and perform 4-bit handshaking data transfer with external devices. 16-bit, single-word instructions and eight stack levels permit efficient use of the 640-word ROM. Operating from a 4.19 MHz crystal, the device has an instruction cycle time of 15 /spl mu/s. An operating power of 100 /spl mu/W at 1.5 W makes the chip ideal for performing control and timing functions in battery operated applications.     

I/O扩展电路GM8166在嵌入式锅炉系统中的应用

介绍了I/O扩展电路GM8166的功能和特点,结合该器件在嵌入式锅炉系统中的应用,侧重说明它通过串行输入并行输出、并行输入串行输出两种转换模式来完成锅炉32路数字输入和32路数字输出控制的I/O口扩展.     

A content addressable memory management unit with on-chip datacache

The design of a single chip (WE-32201) that includes both a content-addressable memory-based management unit and a large data/instruction cache is described. The chip belongs to AT&T's WE-32200 chip set and is fabricated using a 1 μm twin tub CMOS process. It boosts the performance of the entire chip set significantly by providing high memory bandwidth and virtual-memory-management support. The combination of high-performance circuit design and system architectural design techniques makes the chip a major enhancement to the chip set     

An enhanced 16K E/SUP 2/PROM

An enhanced 16K E/SUP 2/PROM is described. It makes the E/SUP 2/PROM to microprocessor interface simple to implement. It frees up the system bus during e/SUP 2/PROM programming by latching addresses, data, and all control signals on chip. It provides minimum ERASE/WRITE, time via a novel feedback subsystem that monitors the amount of charge on the floating gate of the cell and signals to the system by the READY/BUSY output pin when enough charge has been added to or removed from the gate. With an external V/SUB pp/ voltage fixed supply, the E/SUP 2/PROM generates its own RC ramp during ERASE/WRITE, increasing the endurance of the storage cell. On-chip control circuitry provides ERASE before WRITE, making writing appear as a single step to the user.