Investigation of lateral spreading current in the 4H-SiC Schottky barrier diode chip

Lateral current spreading in the 4H-SiC Schottky barrier diode(SBD)chip is investigated.The 4H-SiC SBD chips with the same vertical parameters are simulated and fabricated.The results indicate that there is a fixed spreading resistance at on-state in current spreading region for a specific chip.The linear specific spreading resistance at the on-state is calculated to be 8.6 Ω/cm in the fabricated chips.The proportion of the lateral spreading current in total forward current(Psp)is related to an-ode voltage and the chip area.Psp is increased with the increase in the anode voltage during initial on-state and then tends to a stable value.The stable values of Psp of the two fabricated chips are 32％and 54％.Combined with theoretical analysis,the pro-portion of the terminal region and scribing trench in a whole chip(Ksp)is also calculated and compared with Psp.The Ksp val-ues of the two fabricated chips are calculated to be 31.94％and 57.75％.The values of Ksp and Psp are close with each other in a specific chip.The calculated Ksp can be used to predict that when the chip area of SiC SBD becomes larger than 0.5 cm2,the value of Psp would be lower than 10％.     

A low-power and compact CDMA matched filter based on switched-current technology

A low-power and compact code-division multiple-access (CDMA) matched filter has been developed using the switched-current technology. On-chip V-I and I-V converters featuring moderate linear characteristics have been developed for the chip. The low-power operation has been achieved by the sub-block architecture, which reduced the current flowing in current-memory cells. A low-power clock-on-demand shift register has also been developed. The 256-chip matched filter fabricated in a 0.35-/spl mu/m technology demonstrated the power dissipation of 1.95 mW at the chip rate of 8 Mchip/s under 2-V power supply. The chip occupies the area of 0.54 mm/sup 2/.     

Current monitoring circuit for fault detection in CMOS integrated circuit

This article presents a built-in current sensor (BICS), which detects faults using the current testing technique in CMOS integrated circuits. This circuit employs cross-coupled PMOS transistors, which are used as current comparators. The proposed circuit has a negligible impact on the performance of the circuit under test (CUT). In addition, no extra power dissipation and high-speed fault detection are achieved. It can be applied to deep sub-micron processes. The validity and effectiveness are verified through the HSPICE simulation on circuits with faults. The entire area of the test chip is 116×65 μm². The BICS occupies only 41×17 μm² of the area of the test chip. The area overhead of a BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix 0.35 μm 2-poly-4-metal N-well CMOS process.     

一种BUCK型开关稳压器负载电流检测电路

针对Buck型开关稳压器的断续工作模式(DCM),基于CSMC0.5μm CMOS工艺设计实现了一种新颖的负载电流检测电路。同传统的电感电流采样方式不同,该结构直接应用与负载电流变化几乎同步的同步管栅极驱动信号作为"电流采样"信号,实现了负载平均电流的检测。经投片验证,提出的电流检测电路工作良好,且面积仅占芯片的1.5%,同传统采样方式相比,面积减小了21%,静态时的耗电仅为原来的40%。     

A CMOS transistor-only 8-b 4.5-Ms/s pipelined analog-to-digitalconverter using fully-differential current-mode circuit techniques

Fully-differential current-mode circuit techniques are developed for the design of a pipelined current-mode analog-to-digital converter (IADC) in the standard CMOS digital processes. In the proposed IADC, the 1-b-per-stage architecture based on the reference nonrestoring algorithm is adopted. Thus large component ratios can be avoided and the linearity errors caused by device mismatches can be minimized. As one of the key subcircuits in the IADC, an offset-canceled high speed differential current comparator (CCMP) is proposed and analyzed. In the CCMP, the subtractions of offsets are performed in the current domain without floating capacitors. Moreover, the other key subcircuit, the current sample-and-hold amplifier (CSHA), is also developed to realize the pipeline architecture. An experimental chip for the proposed IADC has been fabricated in 0.8-μm n-well CMOS technology. Using a single 5-V power supply, the fabricated IADC can be operated at 4.5-Ms/s conversion rate with a signal-to-noise-and-distortion-ratio (SNDR) of 51 db (effective 8.2-b) for the input signal at 453 kHz. For 8-b resolution, the fabricated IADC can be operated at 4.5-Ms/s conversion rate with both differential nonlinearity (DNL) and integral nonlinearity (INL) below +/-0.6 LSB. The power consumption and the active chip area are 16 mW/b and 0.73 mm²/b, respectively     

A compact large voltage-compliance high output-impedance programmable current source for implantable microstimulators

A new CMOS current source is described for biomedical implantable microstimulator applications, which utilizes MOS transistors in deep triode region as linearized voltage controlled resistors (VCR). The VCR current source achieves large voltage compliance, up to 97% of the supply voltage, while maintaining high output impedance in the 100 MOmega range to keep the stimulus current constant within 1% of the desired value irrespective of the site and tissue impedances. This approach improves stimulation efficiency, extends power supply lifetime, and saves chip area especially when the stimulation current level is high in the milliampere range. A prototype 4-channel microstimulator chip is fabricated in the AMI 1.5-microm, 2-metal, 2-poly, n-well standard CMOS process. With a 5-V supply, each stimulating site driver provides at least 425-V compliance and > 10 MOmega output impedance, while sinking up to 210 microA, and occupies 0.05 mm2 in chip area. A modular 32-site wireless neural stimulation microsystem, utilizing the VCR current source, is under development.     

Precise CMOS current sample/hold circuits using differential clockfeedthrough attenuation techniques

New CMOS current sample/hold (CSH) circuits capable of overcoming the accuracy limitations in conventional circuits without significantly reducing operating speed are proposed and analyzed. A novel differential clock feedthrough attenuation (DCFA) technique is developed to attenuate the signal-dependent clock feedthrough errors. Unlike conventional techniques, the DCFA circuit allows the use of dynamic mirror techniques, and results in no additional finite output resistance errors or device mismatch errors. The test chip of the proposed fully differential CSH circuit with multiple outputs has been fabricated in 1.2-μm CMOS technology. Using a single 5-V power supply, experimental results show that the signal-dependent clock feedthrough error current is less than ±0.4 μA for the input currents from -550 μA to 550 μA. The acquisition time for a 900-μA step transition to 0.1% settling accuracy is 150 ns. For a 410-μA_p-p input at 250 MHz with the fabricated fully-differential CSH circuit clocked at 4 MHz, a total harmonic distortion of -60 dB, and a signal-to-noise ratio of 79 dB have been obtained. The active chip area and power consumption of the fabricated CSH circuit are 0.64 mm² and 20 mW, respectively. Both simulation and experimental results have successfully verified the functions and performance of the proposed CSH circuits     

Studies of the light output properties for a GaN based blue LED using an electro-optical simulation method

In this study, an electro-optical simulation method is developed to predict the light intensity distribution and luminous flux of an in-house fabricated GaN based blue LED chip. The entire modeling process links an electrical simulation with ANSYS and optical simulation with LightTools, by assuming a proportional relation between the distributed current density and light emission energy on the multiple quantum well (MQW) layer. Experimental results show that the proposed simulation method can give a good prediction on the light intensity distribution for a semi-packaged GaN based blue LED chip. Further analysis on the simulation results reveals that an increase of at most 8% of the luminous flux can be achieved when the current density is controlled to evenly distribute on the MQW layer whereas the chip structure and electro pattern remains the same.     

A single-chip CMOS APS camera with direct frame difference output

A complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) camera chip with direct frame difference output is reported in this paper. The proposed APS cell circuit has in-pixel storage for previous frame image data so that the current frame image and the previous frame image can be read out simultaneously in differential mode. The signal swing of the pixel circuit is maximized for low supply voltage operation. The pixel circuit occupies 32.2×32.2 μm² of chip area with a fill factor of 33%. A 128×98 element prototype camera chip with an on-chip 8-bit analog-to-digital converter has been fabricated in a 0.5-μm double-poly double-metal CMOS process and successfully tested. The camera chip consumes 56 mW at 30 frames/s with 3.3 V power supply     

基于电流矢量和的多模QAM直接数字调制器

 本文提出了一种新型直接数字正交幅度调制器(QAM),可用于4-QAM,16-QAM或更高阶调制方式.其基于电流矢量相加的原理,首次采用一对跨导可调的高速运算跨导放大器产生幅值可控的基本电流矢量,开关网络在电流域中选择矢量相加,减小了非线性失真.该芯片采用0.13μm CMOS工艺进行流片.在5.4GHz载波频率、16Mbps数据率时的测试结果显示,16-QAM调制的EVM为6.2%,芯片面积0.09mm²,在1.2V电源电压下总直流功耗为20mA.     

A 50-MHz 8-Mbit video RAM with a column direction drive senseamplifier

An 8-Mb (1-Mwords×8-b) dynamic RAM which utilizes a column direction drive sense amplifier to obtain low peak current is described. The power supply peak current is about one fourth of that for conventional circuits. The chip operates at 50-MHz and is fabricated with a 0.7-μm n-well CMOS, double-level polysilicon, single-polycide, and double-level metal technology. The memory cell is a surrounding hi-capacitance cell structure. The cell size is 1.8×3.0 μm², and the chip area is 12.7×16.91 mm²     

A new complementary bipolar transistor structure

A novel complementary monolithic bipolar transistor structure has been developed. By adding one extra diffusion to the standard monolithic bipolar transistor process, a complementary pair of high current gain and very low saturation resistance n-p-n and p-n-p transistors can be fabricated on the same chip. High sheet resistances are also present in this structure. Novel low-voltage (1.3 V) complementary digital circuits have been fabricated by this new process.     

An 8-bit parallel DAC with segmented architecture

An 8-bit parallel DAC with a segmented architecture that employs a 4-bit binary and an unary segments is presented. A switched current source and a thermometric decoder are discussed. A test chip is fabricated using a 180-nm CMOS technology. Measured results show higher conversion rate and smaller chip area in comparison with other papers.     

S 频段pHEMT 双通道低噪声放大器芯片的设计

采用GaAs 0.13μmp HEMT MMIC流片工艺设计和制作了一种S频段双通道低噪声放大器芯片,芯片内部集成了两个低噪声放大器通道、一级单刀双掷(SPDT)开关和一个晶体管-晶体管逻辑(TTL)电平转换电路。低噪声放大器电路采用一级共源共栅场效应管(Cascode FET)结构实现,使其具有比单管更高的增益,简化了芯片拓扑,降低了芯片设计难度。经流片测试,在1.9~2.1GHz的工作频带内,芯片噪声系数优于1.4dB,增益大于22.5dB,输入驻波优于1.8,输出驻波优于1.4,输出1dB压缩点(P1dB)为10dBm。大量芯片样本在片测试统计数据表明该低噪声放大器成品率大于90%,性能指标优于目前同类商业芯片指标。     

A 125 μW , Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications

A low-power dual-standard video decoder has been developed for mobile applications. It supports MPEG-2 SP@ML and H.264/AVC BL@L4 video decoding in a single chip and features a scalable architecture to reach area/power efficiency. This chip integrates diverse algorithms of MPEG-2 and H.264/AVC to reduce silicon area. Three low-power techniques are proposed. First, a domain-pipelined scalability (DPS) technique is used to optimize the pipelined structure according to the number of processing cycles. Second, bandwidth scalability is implemented via a line-pixel-lookahead (LPL) scheme to improve the external bandwidth and reduce the internal memory size, leading to 51% of memory power reduction compared to a conventional design. Third, low-power motion compensation and deblocking filter are designed to reduce the operating frequency without degrading system performance. A test chip is fabricated in a 0.18mum one-poly six-metal CMOS technology with an area of 15.21 mm². For mobile applications, H.264/AVC and MPEG-2 video decoding of quarter-common intermediate format (QCIF) sequences at 15 frames per second are achieved at 1.15 MHz clock frequency with power dissipation of 125 muW and 108 muW, respectively, at 1V supply voltage     

An SC Voltage Doubler with Pseudo-Continuous Output Regulation Using a Three-Stage Switchable Opamp

This paper presents a switched-capacitor voltage doubler using pseudo-continuous control (PCC). The proposed PCC does not require extra power transistor to continuously regulate the output of the doubler, thereby saving chip area. The PCC also allows the doubler to operate at lower switching frequencies without sacrificing transient response. The light-load efficiency of the regulated doubler can thus be enhanced by reducing the switching power loss. In addition, a three-stage switchable opamp with time-multiplexed enhanced active-feedback frequency compensation is developed to implement the controller. The proposed implementation enhances the speed of the loop response and then improves the load transient response of the regulated doubler. The SC voltage doubler with the proposed PCC controller has been fabricated in a 0.6-mum CMOS process. The regulated doubler achieves >87% power efficiency even for the load current of 5 mA. By operating the doubler at switching frequency of 200 kHz and using a output capacitor of 2.2 muF, a maximum output ripple of 20mV is maintained for the load current changing from 50 mA to 150 mA. The output transient recovery time of the regulated doubler is ~25 mus with load-current step changes of 100 mA/1 mus     

Design and implementation of PFM mode high efficiency boost regulator

This paper presents the design and implementation of a low voltage DC?CDC asynchronous boost regulator that works in PFM (pulse frequency modulation) mode. The booster is designed to supply low load condition of up to 20 mA with high efficiency. The total bias current of the chip is only 5 ??A when operating with 1 mA load and the number goes to maximum of 18 ??A with maximum load condition of 20 mA. The ultra low bias current enables the chip to maximize its efficiency in the entire load range. The chip features on-chip over current protection scheme and thermal protection scheme. The boost regulator is implemented in 0.5 ??m BiCMOS process technology. The maximum measured efficiency of the fabricated chip is 86%.     

A static random-access memory with normally-off-type Schottky barrier FET's

A large-scale integrated memory with lower power consumption and high operating speed has been developed and evaluated. A fully decoded 256-b static random-access memory chip was fabricated by using the Enhancement-type Schottky Barrier gate FET's, having a threshold voltage of 0.1 V, obtained by ion-implantation. The memory chip was successfully operated with an access time of less than 150 ns, and with active power consumption of 15 mW/chip. A single power supply of -1.3 V and current mode logic input levels are additional features of the memory chip.     

A low-power microcontroller having a 0.5-/spl mu/A standby current on-chip regulator with dual-reference scheme

We present a microcontroller having a 0.5-/spl mu/A standby current on-chip regulator. To break through the area overhead problem which a conventional regulator scheme suffers from to achieve small standby current, we propose a dual-reference scheme in which one voltage reference circuit is provided for active mode and another voltage reference circuit is provided for standby mode. For the voltage reference circuit for standby mode, a resistor-free circuit was used to achieve small current consumption without occupying large area. The microcontroller was fabricated in a 0.18-/spl mu/m CMOS process. The implementation and measurement results show that the dual-reference scheme achieves 0.5-/spl mu/A current consumption of the regulator in standby mode with 50% smaller area than the conventional scheme. The measured standby current of the whole chip was 2.0 /spl mu/A.     

A 0.5 μm Concurrent Testable Chip of a Fifth-Order g m -C Filter

In this paper, we describe a testable chip of a fifth-order g _m -C low-pass filter that has a passband from 0 to 4.5 MHz. We use a current-mode method for the error detection of this filter. By comparing the current consumed by the circuit under test (CUT) and the current converted from the voltage levels of the CUT, abnormal function of circuit components can be concurrently and efficiently detected. A test chip has been fabricated using a 0.5 m, 2P2M CMOS technology. Measurement results show that this current-mode approach has little impact on the performance of the filter and can detect faults in the filter effectively. The area overhead of the circuitry for testing in this chip is about 18%.