一种高精度带隙基准电压源电路设计

针对传统CMOS带隙电压基准源电路电源电压较高,基准电压输出范围有限等问题,通过增加启动电路,并采用共源共栅结构的PTAT电流产生电路,设计了一种高精度、低温漂、与电源无关的具有稳定电压输出特性的带隙电压源.基于0.5μm高压BiCMOS工艺对电路进行了仿真,结果表明,在-40℃～85℃范围内,该带隙基准电路的温度系数为7ppm/℃,室温下的带隙基准电压为1.215 V.     

基于新型非制冷IRFPA读出电路的带隙基准源

设计了一种用于新型非制冷IRFPA读出电路的低温漂的低压带隙基准电路.提出了同时产生带隙基准电压源和基准电流源的技术,通过改进带隙基准电路中的带隙负载结构以及基准核心电路,基准电压和基准电流可以分别进行温度补偿.在0.5 μm CMOS N阱工艺条件下,采用spectre进行模拟验证.仿真结果表明,在3.3 V条件下,在-20℃～100℃范围内,带隙基准电压源和基准电流源的温度系数分别为35.6×10-6℃-1和37.8×10-6℃-1.当电源电压为3.3V时,整个电路的功耗仅为0.17mW.     

一种利用比较器实现可靠启动的带隙基准电压源

提出一种在启动电路中使用比较器配置的带隙基准电压源,解决了带隙基准电压源由于使用双极型晶体管而存在的潜在启动失败问题.该带隙基准电压源通过启动电路的比较器来正确判断启动和关闭点以保证电路启动到理想的工作点,并在电路启动后正常关闭启动电路以缩减功耗消耗,同时避免了其它启动电路存在的问题:引起电路抖动或者求助一些系统中很少使用的上电复位信号等.该带隙电压基准电路提供0.9V的带隙基准电压时,可以工作的电压范围和温度范围分别是1.2V～3.6V和-40～110℃,而且该输出电压在给定的电压和温度范围内仅有5％的变化.     

带隙电压基准源的设计与分析

介绍了基准源的发展和基本工作原理以及目前较常用的带隙基准源电路结构。设计了一种基于Banba结构的基准源电路,重点对自启动电路及放大电路部分进行了分析,得到并分析了输出电压与温度的关系。文中对带隙电压基准源的设计与分析,可以为电压基准源相关的设计人员提供参考。可以为串联型稳压电路、A/D和D/A转化器提供基准电压,也是大多数传感器的稳压供电电源或激励源。     

一种高性能欠压封锁电路

基于0.6μm BiCMOS工艺设计了一种无需基准电压源和比较器的高性能欠压封锁电路(UVLO)。利用带隙基准电压源的原理,实现了欠压封锁的阈值点和迟滞量;而且带隙基准电压源结构自身的稳定性决定了欠压封锁能够稳定工作。仿真验证结果表明,该欠压封锁电路的翻转阈值点几乎不随温度变化。     

一种新型CMOS带隙基准电压源

传统带隙基准源电路采用PNP型三极管来产生ΔVbe,此结构使运放输入失调电压直接影响输出电压的精度。文章在对传统CMOS带隙电压基准源电路原理的分析基础上,提出了一种综合了一阶温度补偿和双极型带隙基准电路结构优点的高性能带隙基准电压源。采用NPN型三极管产生ΔVbe,消除了运放失调电压影响。该电路结构简洁,电源抑制比高。整个电路采用SMIC 0.18μmCMOS工艺实现。通过Cadence模拟软件进行仿真,带隙基准的输出电压为1.24V,在-40℃~120℃温度范围内其温度系数为30×10-6/℃,电源抑制比(PSRR)为-88 dB,电压拉偏特性为31.2×10-6/V。     

一种用于非致冷红外焦平面读出电路的带隙基准源

设计了一种用于新型非致冷红外焦平面阵列读出电路的低温漂低压带隙基准电路.提出了同时产生带隙基准电压源和基准电流源的技术.通过改进带隙基准电路中的带隙负载结构及基准核心电路,可以分别对基准电压和基准电流进行温度补偿.在0.5μm CMOS N阱工艺条件下,采用Spectre软件进行了模拟验证.仿真结果表明,在3.3 V条...     

一种适用于低压差分信号驱动电路的带隙基准源设计

针对低压差分信号驱动电路对共模电压和参考电流的需求,提出了一种新型带隙基准源结构,可在一个基准模块内同时提供带隙基准电压和基准电流.对传统带隙基准进行了改进,优化了基准电压和基准电流的温度特性.仿真结果显示,所设计的基准源电路具有较好的温度特性,在温度范围为-40℃～125℃时,基准电压的温漂系数为17.4 ppm/℃,电流基准的温漂系数为63.3 ppm/℃.作为参考电压与电流基准,可有效保证LVDS信号的稳定性.     

一种低电压低功耗带隙基准电压源的设计

在分析典型带隙基准电压源的基础上,设计了一种低电压、低功耗的带隙基准电压源,采用二次分压技术降低了输出电压;采用亚阈值技术降低了电路的电源电压,进而降低了电路的功耗,通过PSpice的仿真证明该电压源具有较低的输出电压、较低的功耗和较低的温度系数.     

一种高性能CMOS带隙电压基准源设计

采用一级温度补偿和电阻二次分压技术设计了一种高性能CMOS带隙电压基准源电路,其输出电压为0.20～1.25V,温度系数为2.5×10-5/K.该带隙电压基准源电路中的深度负反馈运算放大器为低失调、高增益的折叠型共源共栅运算放大器.采用Hspice进行了运算放大器和带隙电压基准源的电路仿真,用TSMC 0.35μm CMOS工艺实现的带隙基准源的版图面积为645μm×196μm.     

A novel uniplanar compact photonic bandgap power plane with ultra-broadband suppression of ground bounce noise

A novel /spl pi/-bridged photonic bandgap (PBG) power/ground planes is proposed with ultra-broadband suppression of the ground bounce noise(GBN) in the high-speed printed circuit boards. The S-parameters of the proposed low-period structures show that the novel uniplanar compact photonic bandgap (UC-PBG) structures could omni-directionally suppress the GBN in RF/analog circuits and digital circuits. The high omnidirectionally suppressions of the GBN for the proposed structure are validated both experimentally and numerically in the noise bandwidth from 300MHz to 6GHz, almost the whole noise band.     

CMOS带隙基准电压源中的曲率校正方法

基准电压源是集成电路系统中一个非常重要的构成单元。结合近年来的设计经验,首先给出了带隙基准源曲率产生的主要原因,而后介绍了在高性能CMOS带隙基准电压源中所广泛采用的几种曲率校正方法。给出并分析了一些近年来采用曲率校正方法的CMOS带隙基准电压源核心电路以及他们的设计原理、理论推导、参考电路和特点。最后,对于所讨论的基准源电路进行了性能比较和优缺点分析。     

一种具有高电源抑制比的低功耗CMOS带隙基准电压源

文章设计了一种适用于CMOS工艺的带隙基准电压源电路，该电路采用工作在亚阈值区的电路结构，并采用高增益反馈回路，使其具有低功耗、低电压、高电源电压抑制比和较低温度系数等特点。     

Investigation on RFI effects in bandgap voltage references

In this paper the susceptibility of integrated bandgap voltage references to Radio Frequency Interference (RFI) is investigated by on-chip measurements carried out on Kuijk and Tsividis bandgap circuits. These measurements highlight the offset in the reference voltage induced by continuous wave RFI and the complete failures which may be experienced by bandgap circuits. The role of the susceptibility of the startup circuit and of the operational amplifier which are included in such circuits is also focused.     

Low-voltage and low-power circuit design for mixed analog/digitalsystems in portable equipment

This paper describes low-voltage and low-power (LV/LP) circuit design for both analog LSI's and digital LSI's which are used in mixed analog/digital systems in portable equipment. We review some LV/LP circuits used in digital LSI's, such as general logic gate, DSP, and DRAM, and others used in analog LSI's, such as operational amplifiers, video-signal processing circuits, A/D and D/A converters, filters, and RF circuits, along with a wide range of items used in recently developed LSI's. Since analog circuits have fundamental difficulties in reducing the operating voltage and the power consumption, in spite of recent progress in LV/LP circuit techniques, these difficulties will be a major issue for decreasing the total power consumption of some mixed analog/digital systems used in portable equipment     

Reanalyzing the basic bandgap reference voltage circuit considering thermal dependence of bandgap energy

The basic bandgap reference voltage generator, BGR, is thoroughly analyzed and relations are reconstructed considering dependency of bandgap energy, E_g, to absolute temperature. The previous works all consider E_g as a constant, independent of temperature variations. However, E_g varies around 25 meV when the temperature is increased from 2 to 92 °C. In this paper the dependence of E_g to absolute temperature, based on HSPICE mosfet models in HSPICE MOSFET Models Manual (Version X-2005.09, 2005), is approximated by a third-order polynomial using Lagrangian interpolating method within the temperature range of 2–92 °C. Accurate analysis on the simplified polynomial reveals that the TC of V_BE must be corrected to ?1.72 mV/°K at 27 °C which has been formerly reported about ?1.5 mV/°K in Razavi (Design of analog CMOS integrated circuits, 2001) and Colombo et al. (Impact of noise on trim circuits for bandgap voltage references, 2007), ?2 mV/°K in Gray et al. (Analysis and design of analog integrated circuits, 2001), Leung and Mok (A sub-1-V 15-ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device, 2002), Banba et al. (A CMOS bandgap reference circuit with sub-1-V operation, 1999), and ?2.2 mV/°K in Jones and Martin (Analog integrated circuit design, 1997), Tham and Nagaraj (A low supply voltage high PSRR voltage reference in CMOS process, 1995). Another important conclusion is that the typical weighting coefficient of TC+ and TC? terms is modified to about 19.84 at 27 °C temperature from otherwise 16.76, when E_g is considered constant, and also 17.2, in widely read literatures, (Razavi in Design of analog CMOS integrated circuits, 2001). Neglecting the temperature dependence of E_g might introduce a relative error of about 20.5 % in TC of V_BE. Also, resistance and transistor size ratios, which denote the weighting coefficient of TC+ term, might be encountered to utmost 20.3 % error when the temperature dependence of E_g is ignored.     

Statistical Analysis and Optimization of a Bandgap Reference for VLSI Applications

Voltage and current references are widely needed for all kinds of integrated circuits, as most applications require temperature-independent references with a high reproducibility in mass production. For this purpose normally bandgap references are used. Though it is a common task to set up an application specific bandgap circuit, handling of the statistical design aspects is often not a standardized step in the design flow. This article describes some of the steps that were taken during the design of a bandgap reference for a given VLSI application. All statistical simulations were carried out with the simulation tool GAME (General Analysis of Mismatch Effects) which is used at Infineon/Düsseldorf since 1999.     

Op-amps and startup circuits for CMOS bandgap references with near 1-V supply

The design of bandgap-based voltage references in digital CMOS raises several design difficulties, as the supply voltage is lower than the silicon bandgap in electron volts, i.e., 1.2 V. A current-mode architecture is used in order to address the main issues posed by the low supply, but the implementation of the operational amplifier and of dedicated startup circuits deserves some attention. Even if nonstandard devices such as depletion-mode MOS transistors may be helpful to manage the supply scaling, they are seldom available and poorly characterized. Therefore, they must be avoided in a robust design featuring a high portability. This paper proposes some circuit solutions suitable for very low-supply-voltage operation and addresses the main issues of achieving the correct bias point at the power on. A few bandgap references were implemented in digital 0.35- and 0.18-/spl mu/m technologies featuring a nominal output voltage of about 500 mV and minimum supplies from 1.5 to 0.9 V.